A HEMT structure with integrated electrostatic protection and a method for manufacturing the same

Abstract

The present invention discloses a HEMT structure with integrated electrostatic protection and a manufacturing method thereof, wherein an ESD epitaxial structure is formed on a HEMT epitaxial structure, wherein an additional layer is provided on the top of the ESD epitaxial structure, and after a HEMT device region and an ESD device region are formed by etching and isolation, metal is deposited simultaneously in the HEMT region to make source metal and drain metal, and a first electrode is made in the ESD region; then, the additional layer and a cap layer of the HEMT epitaxial structure are etched simultaneously to form an opening, metal is deposited simultaneously in the opening of the additional layer to make a second electrode, and a gate metal is made in the opening of the cap layer. The present invention reduces the electrode manufacturing process requiring a photolithography process, reduces capacity occupancy, and shortens the production cycle.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a HEMT structure with integrated electrostatic protection and a manufacturing method thereof. Background Art

[0002] With the demand for miniaturization and integration of semiconductor devices, the integrated circuit industry, which forms multiple semiconductor functional components in a small area of ​​semiconductor chips, has experienced rapid development.

[0003] High electron mobility transistor (HEMT) is a heterojunction field effect transistor. Due to the large spontaneous polarization and piezoelectric polarization discontinuity between the barrier and channel layer interface, there is a large amount of residual polarization charge at the heterojunction interface, thus forming a high concentration of two-dimensional electron gas at the interface. HEMT has the advantages of high concentration of two-dimensional electron gas (2DEG), high mobility, and strong breakdown electric field, and is widely used in high-temperature, high-frequency and high-voltage microwave devices, and is applied to aerospace, radar, medical treatment and microwave communications. HEMT is easily damaged by high voltage due to electrostatic discharge (EDS) events, so a protection circuit that does not affect the operation of the device is needed to be used with HEMT or similar devices.

[0004] Integrating the ESD structure into the HEMT structure can meet the requirements of semiconductor device integration and miniaturization, but it also adds multiple photolithography steps, prolongs the production cycle, and reduces production capacity. Therefore, streamlining the process is of great significance. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a HEMT structure with integrated electrostatic protection and a method for manufacturing the same.

[0006] In order to achieve the above purpose, the technical solution of the present invention is:

[0007] A method for manufacturing a HEMT structure with integrated electrostatic protection, comprising:

[0008] 1) providing or forming a HEMT epitaxial structure and an ESD epitaxial structure located on the HEMT epitaxial structure through an epitaxial process, wherein the top of the HEMT epitaxial structure includes a cap layer, and the ESD epitaxial structure includes a first material layer, a second material layer and an additional layer from bottom to top, and the first material layer and the second material layer form a PN junction;

[0009] 2) etching the additional layer and the second material layer using photolithography technology;

[0010] 3) etching the first material layer using photolithography technology to form a mesa;

[0011] 4) Separate the HEMT area and the ESD area through device isolation;

[0012] 5) Simultaneously depositing metal on the cap layer of the HEMT region to form source metal and drain metal, and forming a first electrode on the table of the first material layer;

[0013] 6) Using photolithography technology, the additional layer and the cap layer are etched simultaneously to form an opening, metal is deposited simultaneously in the opening of the second material layer to form a second electrode, and gate metal is formed in the opening of the cap layer.

[0014] Optionally, the HEMT epitaxial structure further includes a first etch stop layer, and the cap layer is disposed on the first etch stop layer; the additional layer includes a second etch stop layer and a sacrificial layer disposed on the second etch stop layer.

[0015] Optionally, the sacrificial layer has the same etching characteristics as the cap layer.

[0016] Optionally, the HEMT epitaxial structure is a GaAs-based pHEMT epitaxial structure, the material of the cap layer and the first material layer is n+ type GaAs, the material of the second material layer is p-type GaAs, the material of the sacrificial layer is p-type GaAs, and the material of the first etch stop layer and the second etch stop layer is InGaP or AlAs.

[0017] Optionally, the cap layer has a thickness of 20 to 80 nm, the first etch stop layer has a thickness of 1 to 20 nm, the sacrificial layer has a thickness of 5 to 30 nm, and the second etch stop layer has a thickness of 1 to 20 nm.

[0018] Optionally, it also includes a third etch stop layer disposed between the cap layer and the first material layer and a fourth etch stop layer disposed between the first material layer and the second material layer.

[0019] Optionally, step 6) further includes the step of etching away the first etch stop layer and the second etch stop layer in the opening.

[0020] Optionally, in step 6), after depositing the metal, an alloying process is also included to make the gate metal form a Schottky contact with the first etch stop layer, and the second electrode diffuses through the second etch stop layer to form an ohmic contact with the second material layer.

[0021] A HEMT structure with integrated electrostatic protection comprises a HEMT epitaxial structure, the top of the HEMT epitaxial structure is a cap layer, the HEMT epitaxial structure forms a HEMT region and an ESD region through device isolation, and the ESD epitaxial structure is arranged on the ESD region; the ESD epitaxial structure comprises a first material layer, a second material layer and an additional layer from bottom to top, the first material layer and the second material layer form a PN junction, a first electrode is arranged on a table of the first material layer, the additional layer is provided with an opening, and the second electrode is arranged in the opening of the additional layer; a source metal and a drain metal are arranged on the cap layer of the HEMT region, the cap layer is provided with an opening, and a gate metal is arranged in the opening of the cap layer.

[0022] Optionally, the first electrode, the source metal and the drain metal have the same material or stacked structure, and the second electrode and the gate metal have the same material or stacked structure.

[0023] The beneficial effects of the present invention are:

[0024] 1) The ESD epitaxial structure is integrated on the HEMT epitaxial structure, and the ESD epitaxial structure is provided with an additional layer, and the additional layer is etched synchronously with the cap layer of the HEMT epitaxial structure, so that one metal electrode of the ESD can be synchronously manufactured with the source metal and drain metal of the HEMT, and the other metal electrode can be synchronously manufactured with the gate metal of the HEMT, thereby reducing the electrode manufacturing process requiring the photolithography process, reducing the capacity occupation, shortening the production cycle, and improving the economic benefits;

[0025] 2) Meet the requirements of integration and miniaturization and be suitable for actual production applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a process flow chart of a method for manufacturing a HEMT structure with integrated electrostatic protection according to Example 1, wherein the structure obtained in each step is shown in the figure;

[0027] Figure 2 is a process flow chart of the sub-steps of step 6 in Example 1, showing the structures obtained in each sub-step;

[0028] Figure 3 This is a schematic diagram of the structure of a HEMT with integrated electrostatic protection according to Example 1;

[0029] Figure 4 Schematic diagram of the HEMT structure with integrated electrostatic protection in Example 2. DETAILED DESCRIPTION

[0030] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The drawings of the present invention are only for illustration to make it easier to understand the present invention, and the specific proportions thereof do not represent the actual proportions. The upper and lower relationships of the relative components and the definitions of the front and back sides in the figures described herein should be understood by those skilled in the art to refer to the relative positions of the components, and therefore, they can all be flipped over to present the same components, which should all fall within the scope disclosed in this specification.

[0031] Example 1

[0032] refer to Figure 1 Example 1 takes a GaAs-based epitaxial structure as an example to illustrate a method for manufacturing a HEMT structure with integrated electrostatic protection, the steps of which are:

[0033] Step 1, reference Figure 1 a, providing or forming a HEMT epitaxial structure 1 and an ESD epitaxial structure 2 located on the HEMT epitaxial structure 1 through an epitaxial process. The HEMT epitaxial structure 1 is a GaAs pHEMT epitaxial structure, for example, including from bottom to top a substrate 11, a GaAs buffer layer 12, an InGaAs channel layer 13, an AlGaAs barrier layer 14, an InGaP first etch stop layer 15 and an n+GaAs cap layer 16, in addition, other conventional structures may also be used; more specifically, the first etch stop layer 15 has a thickness of 1 to 20 nm, and the n+GaAs cap layer 16 has a thickness of 20 to 80 nm. The ESD epitaxial structure 2 includes, from bottom to top, an InGaP third etch stop layer 21, an n+GaAs first material layer 22, an InGaP fourth etch stop layer 23, a p GaAs second material layer 24 and an additional layer 25, wherein the additional layer 25 further includes an InGaP second etch stop layer 251 and a p GaAs sacrificial layer 252; more specifically, the p GaAs second material layer 24 has a thickness of 60 to 200 nm, the second etch stop layer 251 has a thickness of 1 to 20 nm, and the p GaAs sacrificial layer 252 has a thickness of 5 to 30 nm.

[0034] Step 2, reference Figure 1 b. Using photolithography technology, coating a photoresist layer, exposing, developing, etching the additional layer 25, the second material layer 24 to the fourth etching stop layer 23 from top to bottom, removing the photoresist layer, and exposing the surface of the first material layer 22 outside the preset area;

[0035] Step 3, reference Figure 1 c. Using photolithography technology, coating a photoresist layer, exposing, developing, etching the first material layer 22 and the third etching stop layer 21, removing the photoresist layer, and exposing the cap layer 16 outside the preset area; the remaining area of ​​the first material layer 22 is larger than the remaining area of ​​the second material layer 24, so that a table is formed on the upper surface of the first material layer 22;

[0036] Step 4, reference Figure 1 d, the HEMT region and the ESD region are separated by device isolation, and it can be understood that the remaining ESD epitaxial structure is located on the ESD region. Conventional device isolation processes, such as ion implantation isolation or etching mesa isolation, can be used to form the above two regions by insulating and isolating the HEMT epitaxial structure, which is achieved by using isolation region I in the figure.

[0037] Step 5, reference Figure 1 e, using photolithography technology, coating a photoresist layer, exposing, and developing to form multiple deposition windows, and simultaneously depositing metal in the windows on the table of the first material layer 22 to form the first electrode 3, and in the windows on the cap layer 16 of the HEMT region to form the source metal 4 and the drain metal 5, and removing the photoresist layer; the deposited metal is exemplified by Au / Ge / Ni / Au, which forms N-type ohmic contacts with the first material layer 22 and the cap layer 16, respectively.

[0038] Step 6, Reference Figure 1 Next, photolithography technology is used to simultaneously etch the additional layer 25 and the cap layer 16 to form an opening, and metal is simultaneously deposited in the opening of the second material layer 24 to form the second electrode 6, and the gate metal 7 is formed in the opening of the cap layer 16.

[0039] Specifically, refer to Figure 2 , the following explains step 6 in detail:

[0040] Step 6.1, reference Figure 2 a, coating a photoresist layer R, and forming a window R1 located on the sacrificial layer 252 and a window R2 located on the cap layer 16 by exposure and development, wherein the window R2 is located between the source metal 4 and the drain metal 5;

[0041] Step 6.2, reference Figure 2 b. A wet etching process is used to etch the sacrificial layer 252 through the window R1 and the cap layer 16 through the window R2. Since the sacrificial layer 252 and the cap layer 16 are both made of GaAs materials and have almost similar etching rates, preferably, the sacrificial layer 252 and the cap layer 16 have the same thickness or the thickness of the cap layer 16 is greater than the thickness of the sacrificial layer 252, so as to ensure that the sacrificial layer 252 is also etched when the cap layer is etched, and an opening 252A is formed in the sacrificial layer 252 and an opening 16A is formed in the cap layer 16; the etching liquid can be a ratio of citric acid, hydrogen peroxide, ammonia water and deionized water, or a ratio of succinic acid, hydrogen peroxide, ammonia water and deionized water, or a ratio of phosphoric acid, hydrogen peroxide and deionized water; these etching liquids have a good selectivity between GaAs and the etching stop layer;

[0042] Step 6.3, reference Figure 2c, depositing metal to form a second electrode 6 in the opening 252A through the window R1, and forming a gate metal 7 in the opening 16A through the window R2; in this embodiment, the metal is a Pt / Ti / Pt / Au / Ti stack;

[0043] Step 6.4, removing the photoresist layer R;

[0044] Step 6.5, using alloy process, the bottom Pt diffuses at high temperature; the gate metal 7 forms a Schottky contact with the first etching stop layer 15, and the Pt in the second electrode 6 passes through the second etching stop layer 251 to form an ohmic contact with the second material layer 24; the thickness ratio of the bottom Pt and the second etching stop layer 251 is greater than 2:1 for optimal; finally, Figure 1 The structure of f.

[0045] refer to Figure 3 The obtained HEMT structure 100 with integrated electrostatic protection includes a HEMT epitaxial structure 1, which includes a substrate 11, a GaAs buffer layer 12, an InGaAs channel layer 13, an AlGaAs barrier layer 14, an InGaP first etch stop layer 15 and an n+GaAs cap layer 16 from bottom to top. The HEMT epitaxial structure 1 forms a HEMT region and an ESD region through device isolation (isolation region I), and an ESD epitaxial structure 2 is provided on the ESD region; the ESD epitaxial structure 2 includes an InGaP third etch stop layer 21, an n+GaAs first material layer 22, an InGaP fourth etch stop layer 23, a p GaAs second material layer 24 and an additional layer 25 from bottom to top, and the additional layer 25 further includes an InGaP second etch stop layer 251 and a p GaAs sacrificial layer 252. The first material layer 22 and the second material layer 24 form a PN junction, the first electrode 3 is arranged on the table of the first material layer 22, the additional layer 25 is provided with an opening 252A, and the second electrode 6 is arranged in the opening 252A of the additional layer; the cap layer 16 of the HEMT region is provided with a source metal 4 and a drain metal 5, the cap layer 16 is provided with an opening 16A, and the gate metal 7 is arranged in the opening 16A of the cap layer. The first electrode 3, the source metal 4 and the drain metal 5 are made in the same process and have the same material or laminated structure. Similarly, the second electrode 6 and the gate metal 7 have the same material or laminated structure.

[0046] Example 2

[0047] refer to Figure 4 The difference between the HEMT structure 200 with integrated electrostatic protection of Example 2 and Example 1 is that the materials of the first etching stop layer 15 and the second etching stop layer 251 are AlAs, and the first etching stop layer 15 and the second etching stop layer 251 in the opening 16A and the opening 252A are removed, and the second electrode 6 and the gate metal 7 are in direct contact with the underlying material layer.

[0048] The difference between Example 2 and Example 1 lies in step 6. Step 6 of this embodiment is specifically as follows:

[0049] Step 6.1, same as in Example 1;

[0050] Step 6.2 is different from Example 1 in that the etching solution used is a mixture of citric acid, hydrogen peroxide, ammonia water and deionized water, or a mixture of succinic acid, hydrogen peroxide, ammonia water and deionized water;

[0051] Step 6.3, removing the first etching stop layer 15 and the second etching stop layer 251 in the opening 16A and the opening 252A by using a mixture of HCl and deionized water;

[0052] Step 6.4, depositing metal to form a second electrode 6 in the opening 252A through the window R1, and a gate metal 7 in the opening 16A through the window R2; the deposited metal is a Ti / Pt / Au / Ti stack or a Pt / Ti / Pt / Au / Ti stack;

[0053] Step 6.5, removing the photoresist layer R.

[0054] Comparative Example

[0055] The difference between the comparative example and the above-mentioned embodiment is that no additional layer is set. In order to ensure that the ESD structure has the preset performance and function, it is necessary to first make a P-type ohmic contact metal located on the p GaAs second material layer as the second electrode, and then make a depletion-type gate metal according to the above-mentioned steps 2 to 5. Compared with the embodiment, the comparative example separately makes the second electrode, and an additional photolithography process needs to be added. A photolithography process includes process steps such as making a mask, coating a photoresist, exposing, developing, and removing the photoresist.

[0056] Compared with the comparative example, the embodiment combines the second electrode and gate metal processes into one process, thereby reducing production capacity occupancy and shortening the production cycle.

[0057] The above embodiments are only used to further illustrate a HEMT structure with integrated electrostatic protection and a manufacturing method thereof of the present invention, but the present invention is not limited to the embodiments. Any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a HEMT structure with integrated electrostatic protection, characterized in that: include: 1) providing or forming a HEMT epitaxial structure and an ESD epitaxial structure located on the HEMT epitaxial structure through an epitaxial process, wherein the top of the HEMT epitaxial structure includes a cap layer, and the ESD epitaxial structure includes a first material layer, a second material layer and an additional layer from bottom to top, and the first material layer and the second material layer form a PN junction; 2) etching the additional layer and the second material layer using photolithography technology; 3) etching the first material layer using photolithography technology to form a mesa; 4) Separate the HEMT area and the ESD area through device isolation; 5) Simultaneously depositing metal on the cap layer of the HEMT region to form source metal and drain metal, and forming a first electrode on the table of the first material layer; 6) Using photolithography technology, the additional layer and the cap layer are etched simultaneously to form an opening, metal is deposited simultaneously in the opening of the second material layer to form a second electrode, and gate metal is formed in the opening of the cap layer.

2. The method according to claim 1, characterized in that: The HEMT epitaxial structure further includes a first etch stop layer, and the cap layer is arranged on the first etch stop layer; the additional layer includes a second etch stop layer and a sacrificial layer arranged on the second etch stop layer.

3. The method according to claim 2, characterized in that: The sacrificial layer has the same etching characteristics as the cap layer.

4. The method according to claim 3, characterized in that: The HEMT epitaxial structure is a GaAs-based pHEMT epitaxial structure, the materials of the cap layer and the first material layer are n+ type GaAs, the material of the second material layer is p type GaAs, the material of the sacrificial layer is p type GaAs, and the materials of the first etch stop layer and the second etch stop layer are InGaP or AlAs.

5. The method according to claim 4, characterized in that: The thickness of the cap layer is 20-80 nm, the thickness of the first etch stop layer is 1-20 nm, the thickness of the sacrificial layer is 5-30 nm, and the thickness of the second etch stop layer is 1-20 nm.

6. The method according to claim 1, characterized in that: The method also includes a third etch stop layer disposed between the cap layer and the first material layer and a fourth etch stop layer disposed between the first material layer and the second material layer.

7. The method according to claim 2, characterized in that: Step 6) further includes the step of etching away the first etching stop layer and the second etching stop layer in the opening.

8. The method according to claim 2, characterized in that: In step 6), after depositing the metal, an alloying process is also included to make the gate metal form a Schottky contact with the first etch stop layer, and the second electrode diffuses through the second etch stop layer to form an ohmic contact with the second material layer.

9. A HEMT structure with integrated electrostatic protection, characterized in that: It includes a HEMT epitaxial structure, the top of the HEMT epitaxial structure is a cap layer, the HEMT epitaxial structure forms a HEMT region and an ESD region through device isolation, and the ESD epitaxial structure is arranged on the ESD region; The ESD epitaxial structure comprises, from bottom to top, a first material layer, a second material layer and an additional layer, the first material layer and the second material layer form a PN junction, the first electrode is arranged on the table of the first material layer, the additional layer is provided with an opening, and the second electrode is arranged in the opening of the additional layer; A source metal and a drain metal are provided on a cap layer of the HEMT region, the cap layer is provided with an opening, and a gate metal is provided in the opening of the cap layer; The additional layer includes a second etch stop layer and a sacrificial layer arranged on the second etch stop layer, the sacrificial layer has the same etching characteristics as the cap layer and is synchronously etched to form an opening; the first electrode, source metal and drain metal have the same material or stacked structure and are synchronously manufactured, and the second electrode and gate metal have the same material or stacked structure and are synchronously manufactured.

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