Method of fabricating a semiconductor structure and transistor having a shielded gate trench structure

Abstract

The application provides a preparation method of a semiconductor structure and a transistor with a shield gate trench structure, and is applied to the technical field of semiconductors. Specifically, the application provides a preparation method of a semiconductor structure. In the process of forming a gate oxide layer of an SGT structure, an ISSG process and a thermal oxidation process are combined, so that the characteristics of the respective formation of the oxide layers by the ISSG process and the thermal oxidation process are utilized, thereby ensuring that the thickness of the oxide film grown on an epitaxial layer EPI is unchanged, and the uniformity of the gate oxide layer of the formed SGT structure in the trench is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and a transistor with a shielded gate trench structure. Background Technology

[0002] Power semiconductor devices are semiconductor devices that process electrical energy. They serve as a bridge between weak current control and strong current operation. More than 75% of the electrical energy consumed by humans needs to be converted by power semiconductor devices before it can be used. Power semiconductor technology makes electrical energy more efficient, energy-saving, and environmentally friendly. It provides users with more convenience, so it is a basic and core technology for energy conservation and emission reduction. At present, power MOS devices are often used in the power supply and load control of circuits. The smaller the on-resistance of the device, the larger the current it can carry. It is currently the product with the largest market capacity and the fastest demand growth among power semiconductor switching devices. Trench MOSFET technology is one of the most important technological driving forces to achieve this goal. Initially, the invention of Trench MOSFET technology was to increase the channel density of planar devices to improve the current handling capability of the devices. However, the improved new Trench MOS structure can not only reduce the channel density, but also further reduce the drift region resistance. The main goals of the development of Trench MOSFET technology are: (1) to reduce the forward conduction resistance to reduce static power loss; (2) to increase the switching speed to reduce transient power loss.

[0003] In the field of low-to-medium voltage devices with a withstand voltage of 20V to 200V, SGT devices are widely used due to their low specific on-resistance and low gate-drain coupling capacitance. The gate structure of an SGT device includes a shielded polysilicon (SPS) and a polysilicon gate. The SPS, often referred to as source polysilicon, is formed in a trench. Depending on the arrangement of the SPS and the polysilicon gate within the trench, they are typically classified as either a top-bottom structure or a left-right structure. In a top-bottom structure, the SPS is located at the bottom of the trench, and the polysilicon gate is located at the top, with the polysilicon gate and SPS in a top-bottom relationship. In a left-right structure, the SPS typically extends from the bottom to the top of the trench, and the polysilicon gate is positioned on either side of the SPS in the top region of the trench, splitting the polysilicon gate within the same trench into two structures.

[0004] However, Split Gate Trench MOSFETs (SGTs), currently the most mainstream power MOSFET devices, are extremely prone to ESD (Electro-Static Discharge) failure. Researchers have discovered that the cause of this failure is that the gate oxide thickness at the corner of the SGT device is too thin, leading to ESD failure. Since practical design requirements dictate that the turn-on voltage of the SGT device cannot be changed, it is necessary to increase the oxide film thickness at the gate oxide corner while maintaining the same oxide film thickness on the epitaxial EPI layer. Therefore, it is crucial to improve the uniformity of the oxide film growth within the trench. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a semiconductor structure to solve the problem of thin gate oxide layer at the corners of transistor SGT devices with shielded gate trench structure, which leads to electrostatic discharge (ESD) problems.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for preparing a semiconductor structure, which may include at least the following steps:

[0007] A semiconductor substrate is provided, in which a first trench is formed, and a shielding dielectric layer is covered on the inner surface of the lower space of the first trench, the shielding dielectric layer surrounding and forming a first accommodating space.

[0008] A shielding gate is formed in the first accommodating space, and the shielding gate continues to extend upward along the upper surface of the semiconductor substrate until the top of the shielding gate is flush with the upper surface of the semiconductor substrate. A second accommodating space is formed on both sides of the shielding gate in the first trench, which is surrounded by the semiconductor substrate, the shielding dielectric layer and the shielding gate.

[0009] A first oxide layer and a second oxide layer are sequentially formed on the inner surface of each of the second accommodating spaces, and the stacked first oxide layer and second oxide layer are used as the gate oxide layer of the semiconductor structure.

[0010] Furthermore, the process for forming the first oxide layer can be the ISSG process.

[0011] Furthermore, the process for forming the second oxide layer can be a thermal oxidation process.

[0012] Furthermore, the thickness range of the first oxide layer can be:

[0013] Furthermore, the thickness range of the second oxide layer can be:

[0014] Furthermore, after forming a shielding barrier within the first accommodating space and before forming a first oxide layer on the inner surface of each second accommodating space, the method may further include forming a SAC protective layer on the inner surface of each second accommodating space.

[0015] Furthermore, the material of the SAC protective layer may include silicon dioxide.

[0016] Furthermore, before forming the first oxide layer on the inner surface of each of the second accommodating spaces, the preparation method may further include: removing the SAC protective layer using an etching process, so that the sidewalls of the second accommodating spaces after the SAC protective layer has been removed retract in a direction parallel to the semiconductor substrate.

[0017] Furthermore, after forming the second oxide layer on the inner surface of each of the second accommodating spaces, the preparation method may further include forming a polysilicon gate within the second accommodating space, such that the formed polysilicon gate at least fills the remaining space in the second accommodating space after the second oxide layer has been formed.

[0018] Secondly, based on the same inventive concept as the semiconductor structure fabrication method described above, the present invention also provides a transistor with a shielded gate trench structure, which can be fabricated using the semiconductor structure fabrication method described above. The specific fabrication method will not be repeated here.

[0019] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0020] This invention proposes a method for fabricating a semiconductor structure. By combining the ISSG process and the thermal oxidation process during the formation of the gate oxide layer of the SGT structure, the unique characteristics of the ISSG process and the thermal oxidation process in forming the oxide layer are utilized to improve the uniformity of the gate oxide layer of the formed SGT structure in the trench while ensuring that the thickness of the oxide film grown on the epitaxial layer EPI remains unchanged. Attached Figure Description

[0021] Figure 1 This is a schematic flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention.

[0022] Figures 2a-2e This is a schematic diagram of the semiconductor structure fabrication method in one embodiment of the present invention during its fabrication process.

[0023] The accompanying figure is labeled as follows:

[0024] 100 - Semiconductor substrate; 110 - Shielding dielectric layer;

[0025] 120 - Shielding grid; 130 - SAC protective layer;

[0026] 140 - First oxide layer; 150 - Second oxide layer;

[0027] 160 - Polysilicon gate; 101 - First trench;

[0028] 102 - First accommodating space; 103 - Second accommodating space. Detailed Implementation

[0029] As described in the background section, Split Gate Trench MOSFETs (SGTs), currently the most mainstream power MOSFET devices, are extremely prone to ESD (Electro-Static Discharge) failure. Researchers have discovered that the cause of this failure is that the Gate Oxide thickness at the corner of the SGT device is too thin, leading to ESD failure. However, since practical design requirements dictate that the turn-on voltage of the SGT device cannot be changed, it is necessary to increase the oxide film thickness at the Gate Oxide corner while maintaining the same oxide film thickness on the epitaxial EPI layer. Therefore, it is essential to improve the uniformity of the oxide film grown within the trench.

[0030] To address this issue, the present invention provides a method for fabricating a semiconductor structure to solve the problem of thin gate oxide layer at corners in transistor SGT devices with shielded gate trench structures, which leads to electrostatic discharge (ESD) problems.

[0031] For details, please refer to... Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, the method for fabricating the semiconductor structure provided by the present invention may include at least the following steps:

[0032] Step S1: A semiconductor substrate is provided, and a first trench is formed in the semiconductor substrate. A shielding dielectric layer is covered on the inner surface of the lower space of the first trench, and the shielding dielectric layer surrounds and forms a first accommodating space.

[0033] Step S2: A shielding gate is formed in the first accommodating space, and the shielding gate continues to extend upward along the upper surface of the semiconductor substrate until the top of the shielding gate is flush with the upper surface of the semiconductor substrate. A second accommodating space is formed on both sides of the shielding gate in the first trench, which is surrounded by the semiconductor substrate, the shielding dielectric layer and the shielding gate.

[0034] Step S3: A first oxide layer and a second oxide layer are sequentially formed on the inner surface of each of the second accommodating spaces, and the stacked first oxide layer and second oxide layer are used as the gate oxide layer of the semiconductor structure.

[0035] That is, the present invention proposes a method for fabricating a semiconductor structure. By combining the ISSG process and the thermal oxidation process during the formation of the gate oxide layer of the SGT structure, the characteristics of the oxide layer formed by the ISSG process and the thermal oxidation process are utilized to improve the uniformity of the gate oxide layer of the formed SGT structure in the trench while ensuring that the thickness of the oxide film grown on the epitaxial layer EPI remains unchanged.

[0036] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the method for fabricating the semiconductor structure and the transistor with a shielded gate trench structure proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0037] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0038] The following is a detailed description of a method for fabricating a semiconductor structure provided by this invention. Figures 2a-2e This is a schematic diagram of the semiconductor structure fabrication method in one embodiment of the present invention during its fabrication process.

[0039] In step S1, please refer to the following for details. Figure 2aAs shown, a semiconductor substrate 100 is provided, which serves as an operating platform for subsequent processes to generate a transistor SGT device with a shielded gate trench structure. The semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. For example, in this embodiment, the semiconductor substrate 100 is a silicon wafer.

[0040] A first trench 101 is formed downward along the upper surface of the semiconductor substrate 100. A shielding dielectric layer 110 is then formed on the inner surface of the lower space of the first trench 101. Since the shielding dielectric layer 110 does not completely fill the lower space of the first trench 101, it surrounds and forms a first accommodating space 102 with a width of d1 in the lower space of the first trench 101. For example, the material of the shielding dielectric layer 110 can be silicon dioxide.

[0041] In this embodiment, the process for forming the first trench 101 can be a wet etching process, a dry etching process, or a hybrid process of wet and dry etching. The process for forming the shielding dielectric layer 110 can be other existing deposition processes such as chemical vapor deposition or physical vapor deposition; this invention does not specifically limit the process in this regard.

[0042] In step S2, please refer to the following for details. Figure 2b As shown, a shielding gate 120 is formed in the first accommodating space 102, and the shielding gate 120 continues to extend upward along the upper surface of the semiconductor substrate 100 until the top of the shielding gate 120 is flush with the upper surface of the semiconductor substrate 100. A second accommodating space 103 is formed on both sides of the shielding gate 120 in the first trench 101, which is surrounded by the semiconductor substrate 100, the shielding dielectric layer 110 and the shielding gate 120.

[0043] In this embodiment, a shielding gate material can be deposited within the first accommodating space 102 using a deposition process. The shielding gate material can be, for example, polysilicon. Specifically, the top surface of the shielding dielectric layer 110 can be covered with a photoresist layer, and then polysilicon material can be deposited within the first accommodating space 102 with a width of d2. The polysilicon shielding gate material continues to extend upwards along the upper surface of the semiconductor substrate 100 until a shielding gate is formed. Figure 2b The shielding gate 120 shown is columnar in shape, wherein the width of the shielding gate 120 is the same as the width of the first accommodating space 102, i.e., d2. During the formation of the shielding gate 120, a chemical mechanical polishing (CMP) process is used to make the top surface of the final shielding gate 120 flush with the top surface of the semiconductor substrate 100. Then, since the width of the shielding gate 120 formed in this embodiment is the same as the width of the first accommodating space 102, i.e., d2, a second accommodating space 103, surrounded by the semiconductor substrate 100, the shielding dielectric layer 110, and the shielding gate 120, can be formed within the first trench 101 simultaneously with the formation of the shielding gate 120. The second accommodating space 103 is used to form the control gate of the SGT device provided by this invention, also referred to as a polysilicon gate.

[0044] For further details, please refer to [link / reference]. Figure 2c As shown, after forming the shielding gate 120 in the first accommodating space 102 in the preparation method provided by the present invention, and before forming the first oxide layer 140 on the inner surface of each of the second accommodating spaces 103, the preparation method may further include the following steps:

[0045] Step S2.1: A SAC protection layer 130 is formed on the inner surface of each of the second accommodating spaces 103. For example, the material of the SAC protection layer 130 may include silicon dioxide.

[0046] In this embodiment, a thermal oxidation process can be used. That is, after the semiconductor structure formed in step S2 above, the structure is heated to thermally oxidize the silicon material of the semiconductor substrate 100 on the inner surface of each second accommodating space 103, thereby forming the SAC protective layer 130 on the inner surface of each second accommodating space 103. The SAC protective layer 130 is mainly used to repair the surface of the semiconductor substrate it covers.

[0047] For further details, please refer to [link / reference]. Figure 2d As shown, before forming the first oxide layer 140 on the inner surface of each of the second accommodating spaces 103, the preparation method provided by the present invention may further include the following steps:

[0048] Step S2.2: Remove the SAC protective layer 130 using an etching process, so that the sidewall of the second accommodating space 103 after the SAC protective layer 130 has been removed retracts in a direction parallel to the semiconductor substrate 100.

[0049] In this embodiment, as Figure 2b As shown, the sidewall of the second accommodating space 103 formed in the first trench 101 in the above steps is flush with the sidewall of the shielding dielectric layer 110. Since the SAC protective layer 130 is subsequently formed using a thermal oxidation process, after removing the SAC protective layer 130 in step S2.2 of this invention, [the following will occur]. Figure 2d A second accommodating space 103' is formed in the middle, which is to shrink back in a direction parallel to the semiconductor substrate 100, that is, to expand the second accommodating space 103 in a direction parallel to the surface of the semiconductor substrate 100.

[0050] In step S3, please refer to the following for details. Figure 2e As shown, a first oxide layer 140 and a second oxide layer 150 are sequentially formed on the inner surface of each of the second accommodating spaces 103, and the stacked first oxide layer 140 and second oxide layer 150 serve as the gate oxide layer OX of the semiconductor structure. For example, the material of the first oxide layer 140 and / or the second oxide layer 150 may be silicon dioxide.

[0051] For example, the process for forming the first oxide layer 140 can be an ISSG process, while the process for forming the second oxide layer 150 can be a thermal oxidation process. Specifically, the thickness range of the formed first oxide layer 140 can be: The thickness range of the second oxide layer 150 formed can be:

[0052] In this embodiment, since the process for forming the first oxide layer 140 is the ISSG process, its characteristics allow for a very uniform film thickness at the corners of the first oxide layer 140 within the second accommodating space 103. This, in turn, improves the uniformity of the gate oxide layer in the trench while maintaining a constant oxide film thickness on the epitaxial EPI layer. Preferably, in this embodiment, the thickness of the first oxide layer 140 is... In other embodiments, the thickness of the first oxide layer 140 may also be and The process for forming the second oxide layer 150 is a thermal oxidation process, and preferably, the thickness of the second oxide layer 150 is [missing information]. In other embodiments, the thickness of the second oxide layer 150 can also be... and

[0053] Further reference Figure 2e As shown, after forming the second oxide layer 150 on the inner surface of each of the second accommodating spaces 103, the preparation method provided by the present invention may further include the following steps:

[0054] Step S3.1: A polysilicon gate 160 is formed in the second accommodating space 103, such that the formed polysilicon gate 160 at least fills the remaining space in the second accommodating space 103 after the second oxide layer 150 is formed.

[0055] Furthermore, based on the same inventive concept as the semiconductor structure fabrication method described above, the present invention also provides a transistor with a shielded gate trench structure, which can be fabricated using the semiconductor structure fabrication method described above. The specific fabrication method will not be repeated here.

[0056] In summary, in the semiconductor structure fabrication method proposed in this invention, the ISSG process and the thermal oxidation process are combined during the formation of the gate oxide layer of the SGT structure. By utilizing the characteristics of the oxide layer formation of the ISSG process and the thermal oxidation process, the uniformity of the gate oxide layer of the formed SGT structure in the trench is improved while ensuring that the oxide film thickness grown on the epitaxial layer EPI remains unchanged.

[0057] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0058] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0059] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, It should include at least the following steps: A semiconductor substrate is provided, in which a first trench is formed, and a shielding dielectric layer is covered on the inner surface of the lower space of the first trench, wherein the shielding dielectric layer and the semiconductor substrate surround to form a first accommodating space. A shielding gate is formed in the first accommodating space, and the shielding gate continues to extend upward along the upper surface of the semiconductor substrate until the top of the shielding gate is flush with the upper surface of the semiconductor substrate. A second accommodating space is formed on both sides of the shielding gate in the first trench, which is surrounded by the semiconductor substrate, the shielding dielectric layer and the shielding gate. A first oxide layer and a second oxide layer are sequentially formed on the inner surface of each second accommodating space, and the stacked first oxide layer and second oxide layer are used as the gate oxide layer of the semiconductor structure. The process for forming the first oxide layer is the ISSG process, and the process for forming the second oxide layer is the thermal oxidation process.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The thickness of the first oxide layer ranges from 250 Å to 350 Å.

3. The method for preparing the semiconductor structure as described in claim 1, characterized in that, The thickness of the second oxide layer ranges from 400 Å to 500 Å.

4. The method for preparing the semiconductor structure according to claim 1, characterized in that, After forming a shielding barrier within the first accommodating space and before forming a first oxide layer on the inner surface of each second accommodating space, the method further includes forming a SAC protective layer on the inner surface of each second accommodating space.

5. The method for preparing a semiconductor structure as described in claim 4, characterized in that, The material of the SAC protective layer includes silicon dioxide.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, Before forming the first oxide layer on the inner surface of each of the second accommodating spaces, the preparation method further includes: removing the SAC protective layer using an etching process, so that the sidewalls of the second accommodating spaces after the SAC protective layer has been removed retract in a direction parallel to the semiconductor substrate.

7. The method for preparing a semiconductor structure as described in claim 1, characterized in that, After forming the second oxide layer on the inner surface of each of the second accommodating spaces, the preparation method further includes forming a polysilicon gate within the second accommodating space, such that the formed polysilicon gate at least fills the remaining space in the second accommodating space after the second oxide layer has been formed.

8. A transistor with a shielded gate trench structure, characterized in that, It is prepared by the semiconductor structure preparation method according to any one of claims 1 to 7.

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