An encapsulation body and a preparation method thereof

Abstract

The present invention discloses an encapsulation body and a preparation method thereof. The preparation method of the encapsulation body includes: obtaining a processing board, the processing board including a carrier plate with pads formed on opposite sides and first plastic encapsulation layers respectively attached to opposite sides of the carrier plate; preparing connectors connecting corresponding pads on one side of each first plastic encapsulation layer away from the carrier plate, and respectively performing depth control on preset positions of each first plastic encapsulation layer until the cross-section of the connector is exposed to form a depth control groove; wherein the preset position partially overlaps with the connector; vertically installing the chip in the corresponding depth control groove, and connecting the side surface of the chip to the connector; respectively forming second plastic encapsulation layers on one side of each first plastic encapsulation layer away from the carrier plate, and dividing the carrier plate to obtain at least two encapsulation bodies. By the above method, the present invention can achieve the vertical installation of the chip, simplify the connection path of the connector, and improve the space utilization rate of the encapsulation body.

Description

Technical Field

[0001] The present invention is applied to the technical field of packages, and particularly relates to a package and a preparation method thereof. Background Art

[0002] Packaging technology is used for the housing for installing semiconductor integrated circuit chips, and plays the roles of placing, fixing, sealing, protecting electronic devices, and enhancing electrothermal performance. Moreover, it is also a bridge connecting the internal circuit and the external circuit of electronic devices.

[0003] Currently, there are certain limitations in the packaging of various components by the existing packages, resulting in insufficient space utilization of the packages. Summary of the Invention

[0004] The present invention provides a package and a preparation method thereof to solve the problem of insufficient space utilization of the package.

[0005] To solve the above technical problems, the present invention provides a preparation method of a package, including: obtaining a processing plate, where the processing plate includes a carrier plate with pads formed on opposite sides and first encapsulation layers respectively disposed on opposite sides of the carrier plate; preparing connectors connecting the corresponding pads on one side of each first encapsulation layer away from the carrier plate, and respectively performing depth control on preset positions of each first encapsulation layer until the cross-section of the connector is exposed to form a depth control groove; where the preset position partially overlaps with the connector; vertically installing the chip in the corresponding depth control groove, and connecting the side surface of the chip to the connector; forming second encapsulation layers on one side of each first encapsulation layer away from the carrier plate, and dividing the carrier plate to obtain at least two packages.

[0006] Among them, the step of obtaining a processing plate, where the processing plate includes a carrier plate with pads formed on opposite sides and first encapsulation layers respectively disposed on opposite sides of the carrier plate, includes: obtaining a carrier plate with pads formed on both opposite sides; performing first double-sided encapsulation on opposite sides of the carrier plate to respectively form first encapsulation layers on opposite sides of the carrier plate to obtain a processing plate.

[0007] Among them, the pads include first pads and second pads; before the step of performing first double-sided encapsulation on opposite sides of the carrier plate to respectively form first encapsulation layers on opposite sides of the carrier plate to obtain a processing plate, it includes: installing components on the second pads.

[0008] Among them, the steps of preparing connectors connecting to corresponding pads on the side of each first encapsulation layer away from the carrier board include: drilling holes in each first encapsulation layer based on the positions of each first pad to obtain blind holes exposing each first pad; metallizing each blind hole until connectors are obtained that are arranged in contact with the side of each first encapsulation layer away from the carrier board; among them, each end of the connector extends along the corresponding blind hole to connect to the corresponding first pad.

[0009] Among them, the steps of forming a second encapsulation layer on the side of each first encapsulation layer away from the carrier board and dividing the carrier board to obtain at least two packages include: performing second double-sided encapsulation on opposite sides of the processed board to form a second encapsulation layer on the side of each first encapsulation layer away from the carrier board; laminating reinforcement sheets and coating solder resist layers in sequence on the side of each second encapsulation layer away from the carrier board; dividing the carrier board to obtain at least two packages.

[0010] Among them, the carrier board includes a substrate and pads formed on opposite sides of the substrate; the substrate of the carrier board includes a conductive layer, a first dielectric layer, and a conductive layer that are sequentially laminated and arranged in contact; or the substrate of the carrier board includes a second dielectric layer, a conductive layer, a first dielectric layer, a conductive layer, and a second dielectric layer; among them, conductive vias are formed on each second dielectric layer to connect the pads of the carrier board and the corresponding conductive layers.

[0011] Among them, the steps of dividing the carrier board to obtain at least two packages include: removing the first dielectric layer to divide the carrier board; etching the exposed conductive layer to obtain at least two packages.

[0012] To solve the above technical problems, the present invention also provides a package, including: an encapsulation layer, a depth control groove is formed inside the encapsulation layer, and a pad is formed on one side of the encapsulation layer; a chip, the chip is vertically placed in the depth control groove; a connector, one end of the connector is connected to the corresponding pad, and the other end of the connector is connected to the side surface of the chip to lead out the electrical signal of the chip from the package.

[0013] Among them, a first pad and a second pad are formed on one side of the encapsulation layer; one end of the connector is connected to the corresponding first pad, and the other end of the connector is connected to the side surface of the chip; a component is installed on the side of the second pad close to the encapsulation layer.

[0014] Among them, a second dielectric layer is formed on one side of the encapsulation layer, a conductive circuit is formed on the side of the second dielectric layer away from the encapsulation layer, and conductive vias are formed on the second dielectric layer; the conductive circuit is connected to the corresponding first pad or second pad through the corresponding conductive via.

[0015] To solve the above technical problems, the method for preparing the package of the present invention prepares connectors on the first encapsulation layers on both sides of the processing board and performs local depth control based on the positions of the connectors to form depth-controlled grooves, so as to vertically install the chip in the depth-controlled grooves. Furthermore, the pads on the side of the chip can be directly connected to the connectors exposed through the depth-controlled grooves, thereby enabling the vertical installation of the chip. The vertical installation of the chip can simplify the connection path of the connectors, improve the space utilization rate of the package, overcome the limitations of system-level packaging and board-level packaging, and expand the application scenarios of the package. And by using a double-sided carrier board for connector preparation, chip installation, and encapsulation, packages can be respectively prepared on opposite sides of the carrier board, which can increase the production volume of package preparation and thus improve the efficiency of package preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic flow chart of an embodiment of the method for preparing the package provided by the present invention;

[0017] Figure 2 is a schematic flow chart of another embodiment of the method for preparing the package provided by the present invention;

[0018] Figure 3 is Figure 2 a schematic structural diagram of one embodiment of the carrier board in the embodiment;

[0019] Figure 4 is Figure 2 a schematic structural diagram of another embodiment of the carrier board in the embodiment;

[0020] Figure 5 is Figure 2 a schematic structural diagram of one embodiment of the processing board in step S21 of the embodiment;

[0021] Figure 6 is Figure 2 a schematic structural diagram of one embodiment of the processing board in step S22 of the embodiment;

[0022] Figure 7 is Figure 2 a schematic structural diagram of one embodiment of the processing board in step S23 of the embodiment;

[0023] Figure 8 is Figure 2 a schematic structural diagram of one embodiment of the processing board in step S24 of the embodiment;

[0024] Figure 9 is a schematic structural diagram of one embodiment of the package provided by the present invention;

[0025] Figure 10 is a schematic structural diagram of another embodiment of the package provided by the present invention. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] It should be noted that if there are directional indications (such as up, down, left, right, front, back,...) involved in the embodiments of the present invention, then the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0028] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, then the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0029] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of an embodiment of the method for preparing a package provided by the present invention.

[0030] Step S11: Obtain a processed board, where the processed board includes a carrier plate with pads formed on opposite sides and a first plastic encapsulation layer respectively attached to opposite sides of the carrier plate.

[0031] Obtain a processed board. Among them, the processed board includes a carrier plate and two layers of first plastic encapsulation layers. The two layers of first plastic encapsulation layers are respectively attached to opposite sides of the carrier plate, that is, the carrier plate is disposed between the two layers of first plastic encapsulation layers, and pads are also formed on opposite sides of the carrier plate. When the first plastic encapsulation layer is attached to the carrier plate, it also covers the pads on the corresponding side.

[0032] The number of pads on each side of the first plastic encapsulation layer may include multiple. The pads on one side of the carrier plate can be used to prepare one package or multiple packages, and the number of pads on one side of the carrier plate corresponding to one package or multiple packages is different, which can be specifically set based on actual needs and will not be limited here.

[0033] The first encapsulation layer may specifically include one or more of epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic matrix. There is no limitation here.

[0034] The carrier board is used to support the preparation of the package body, and its material itself may include a glass plate, a metal plate, a plastic plate, etc. There is no limitation here.

[0035] Step S12: On the side of each first encapsulation layer away from the carrier board, prepare connectors connecting to the corresponding pads respectively, and perform depth control on the preset positions of each first encapsulation layer until the cross-section of the connector is exposed to form a depth control groove; wherein, the preset position partially overlaps with the connector.

[0036] After obtaining the processed board, on the side of each first encapsulation layer of the processed board away from the carrier board, prepare connectors connecting to the corresponding pads respectively.

[0037] In a specific application scenario, the first encapsulation layer can be drilled from the side away from the carrier board until the pad is exposed, and then the hole is metallized until a connector connecting to the corresponding pad is formed.

[0038] In another specific application scenario, it is also possible to perform depth control on the first encapsulation layer from the side away from the carrier board until the pad is exposed, and then weld a wire or a metal part on the pad for connection. The method of preparing the connector is not limited here.

[0039] After the connector is prepared, perform depth control on the preset positions of each first encapsulation layer until the cross-section of the connector is exposed to form a depth control groove; wherein, the preset position partially overlaps with the connector. The depth control groove is opened on the connector, that is, local depth control is performed based on the position of the connector until the cross-section of the connector is exposed to form a depth control groove.

[0040] The depth control groove is used to install the chip. When multiple package bodies are to be prepared on one side of the carrier board and / or multiple chips need to be installed on one package body, this step can prepare multiple depth control grooves on the opposite sides of the carrier board respectively.

[0041] The depth control method in this step can be carried out by laser ablation depth control or mechanical depth control. There is no limitation here.

[0042] Step S13: Vertically install the chip into the corresponding depth control groove, and connect the side of the chip to the connector.

[0043] After the depth-controlled grooves are prepared, the chips are vertically installed in the corresponding depth-controlled grooves, and each depth-controlled groove is installed with a chip. Since the pads of the chip are arranged on its side surface, therefore, when it is vertically arranged in the depth-controlled groove, the pads on the side surface of the chip can be directly connected to the connectors exposed through the depth-controlled grooves, so that the vertical installation of the chip can be realized, and the vertical installation of the chip can simplify the connection path of the connectors and improve the space utilization rate of the package.

[0044] In a specific application scenario, the pads on the side surface of the chip can be welded to the connectors exposed through the depth-controlled grooves to achieve direct connection. In another specific application scenario, the pads on the side surface of the chip can be directly connected to the connectors exposed through the depth-controlled grooves by bonding with conductive adhesive. This is not limited here.

[0045] Step S14: Second plastic packages are respectively formed on the sides of the first plastic packages away from the carrier board, and the carrier board is divided to obtain at least two packages.

[0046] After the chips are installed, second plastic packages are respectively formed on the sides of the first plastic packages away from the carrier board, so as to plastic package the connectors and the chips.

[0047] And the carrier board in this embodiment is a double-sided carrier board, and the preparation of connectors, the installation of chips and the plastic packaging are all carried out on each side of the carrier board. Therefore, packages are prepared on the opposite sides of the carrier board respectively. Therefore, by dividing the carrier board, at least two packages can be obtained. Among them, the carrier board can also be used to prepare a batch of packages. After dividing the board, the two divided board pieces are respectively cut to obtain a plurality of independent packages.

[0048] Through the setting of the double-sided carrier board, the production volume of package preparation can be increased, and then the efficiency of package preparation can be improved.

[0049] The above package can also expand the size of the system-level package to exceed 100*300 mm, meeting more application requirements.

[0050] Through the above steps, the method for preparing the package body of this embodiment prepares connection components on the first encapsulation layers on both sides of the processing board, and performs local depth control based on the positions of the connection components to form depth-controlled grooves, so as to vertically install the chip in the depth-controlled grooves. Furthermore, the pads on the side of the chip can be directly connected to the connection components exposed through the depth-controlled grooves, thereby enabling the vertical installation of the chip. The vertical installation of the chip can simplify the connection path of the connection components, improve the space utilization rate of the package body, improve the limitations of system-level packaging and board-level packaging, and expand the application scenarios of the package body. Moreover, by using a double-sided carrier board for preparing connection components, installing the chip, and performing encapsulation, package bodies can be respectively prepared on the opposite sides of the carrier board, which can increase the production volume of package body preparation and thus improve the efficiency of package body preparation.

[0051] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of another embodiment of the method for preparing the package body provided by the present invention.

[0052] Step S21: Obtain a carrier board with pads formed on both opposite sides; perform the first double-sided encapsulation on both opposite sides of the carrier board to respectively form first encapsulation layers on both opposite sides of the carrier board, and obtain a processing board.

[0053] Obtain a carrier board with pads formed on both opposite sides. Among them, the carrier board includes a substrate and pads formed on both opposite sides of the substrate. The number of pads on each side of the substrate can be multiple, for example: 4, 8, 11, etc., and can be specifically set based on actual requirements.

[0054] In a specific application scenario, the substrate of the carrier board includes a conductive layer, a first dielectric layer, and a conductive layer that are sequentially stacked and adhered.

[0055] Please refer to Figure 3 , Figure 3 is Figure 2 a schematic structural diagram of one embodiment of the carrier board in the embodiment.

[0056] The carrier board 100 of this embodiment includes a substrate 110 and pads 113 formed on both opposite sides of the substrate 110.

[0057] Among them, the substrate 110 includes a conductive layer 112, a first dielectric layer 111, and a conductive layer 112 that are sequentially stacked and adhered.

[0058] The number of pads 113 on each side of the substrate 110 can be multiple.

[0059] The carrier board 100 of this embodiment can facilitate the miniaturization and light weight of the package body.

[0060] In another specific application scenario, the substrate of the carrier board includes a second dielectric layer, a conductive layer, a first dielectric layer, a conductive layer, and a second dielectric layer; wherein, conductive vias are formed on each of the second dielectric layers to connect the pads of the carrier board and the corresponding conductive layers.

[0061] Please refer to Figure 4 , Figure 4 is Figure 2 a schematic structural diagram of another embodiment of the carrier board in the embodiment.

[0062] The carrier board 200 of this embodiment includes a substrate 210 and pads 213 formed on opposite sides of the substrate 210.

[0063] The substrate 210 of the carrier board 200 includes a second dielectric layer 214, a conductive layer 212, a first dielectric layer 211, a conductive layer 212, and a second dielectric layer 214; wherein, a plurality of conductive vias 215 are formed on each of the second dielectric layers 214 to connect the pads 213 of the carrier board 200 and the corresponding conductive layers 212.

[0064] The conductive structure inside the carrier board 200 of this embodiment is in an "I" shape or a "Z" shape, which can enhance the structural stability of the package and improve the reliability of the package.

[0065] The pads on the carrier board may include a first pad and a second pad. Among them, the first pad refers to the pad used to prepare a connecting member for conducting the chip in the future; the second pad refers to the pad used to install components in the future. Among them, the number of the first pads and the second pads on the carrier board is determined based on the number of chips and components, and is not limited herein.

[0066] In a specific application scenario, before the first encapsulation, components can be installed on the second pads. Specifically, the pads of the components can be soldered to the corresponding second pads, or the components can be connected to the corresponding second pads by wire bonding. The components can include any active / passive devices such as chips, resistor-capacitor devices, power supplies, switches, etc., and the specific types and quantities can be set based on actual requirements.

[0067] Perform the first double-sided encapsulation on opposite sides of the carrier board simultaneously to form a first encapsulation layer on each of the opposite sides of the carrier board, obtaining a processed board piece. The first encapsulation layer fills the gap between the components and the pads.

[0068] Since the first encapsulation in this step is double-sided encapsulation, when encapsulating, force is applied to both sides of the carrier board simultaneously, so that the pads and the conductive layers on the carrier board are in balanced force during the encapsulation process, and thus the problem of warping generated during the production of the package can be reduced, and the structural stability and reliability of the package can be improved.

[0069] Please refer toFigure 5 , Figure 5 is Figure 2 A schematic structural diagram of one embodiment of the processing plate in step S21 of the embodiment.

[0070] In this embodiment, Figure 4 On the basis of the embodiment, the solder pad 213 is divided into a first solder pad 241 and a second solder pad 242. Among them, this embodiment takes both the first solder pad 241 and the second solder pad 242 as 2 for example. In other embodiments, the numbers of the first solder pad 241 and the second solder pad 242 can also be other numbers, which are not limited herein.

[0071] Components 220 are installed on the side of each second solder pad 242 away from the carrier 200. Specifically, the components 220 can be soldered to the corresponding second solder pads 242 through solder paste.

[0072] First encapsulation layers 230 are respectively and adhesively disposed on opposite sides of the carrier 200. The first encapsulation layers 230 respectively wrap the corresponding components 220 and solder pads 213, and fill the gaps between the components 220 and the solder pads 213.

[0073] When subsequent preparation is carried out based on the carrier of Figure 3 the embodiment, its structure is similar to that based on Figure 4 the carrier of the embodiment for subsequent preparation, and will not be elaborated here.

[0074] Step S22: Drill holes in each first encapsulation layer based on the positions of the first solder pads to obtain blind holes respectively exposing the first solder pads; metallize each blind hole until a connection member is obtained that is adhesively disposed on the side of each first encapsulation layer away from the carrier.

[0075] Drill holes in each first encapsulation layer based on the positions of the first solder pads to obtain blind holes respectively exposing the first solder pads. Laser drilling can be used during drilling.

[0076] Metallize each blind hole until a connection member is obtained that is adhesively disposed on the side of each first encapsulation layer away from the carrier. Electroplating, sputtering or evaporation can be performed on opposite sides of the processing plate until each blind hole is filled and an electroplated metal layer is formed on the side of each first encapsulation layer away from the carrier. In a specific application scenario, the electroplated metal layer can be etched to remove unnecessary parts to form a connection member. In another specific application scenario, the electroplated metal layer can also be directly used as the connection member to improve the heat dissipation efficiency of the package by increasing the area of the connection member.

[0077] Among them, the middle part of the connecting member is attached to the side of each first plastic encapsulation layer away from the carrier board, and each end thereof extends along the corresponding blind hole to the corresponding first pad for connection. Among them, one connecting member may include at least two ends, and at least one connecting member may be provided on the side of each first plastic encapsulation layer away from the carrier board.

[0078] Please refer to Figure 6 , Figure 6 is Figure 2 a schematic structural diagram of a processing board in one implementation manner of step S22 of the embodiment.

[0079] Based on the processing board 202 of this implementation manner on Figure 5 the basis of the implementation manner, blind holes 251 are respectively prepared on two first plastic encapsulation layers 230. Among them, each blind hole 251 exposes a corresponding first pad 241. A connecting member 260 is also attached to the side of each first plastic encapsulation layer 230 away from the first pad 241. Each end of the connecting member 260 extends along the corresponding blind hole 251 to the corresponding first pad 241 for connection.

[0080] Step S23: Perform depth control on the preset positions of each first plastic encapsulation layer until the cross-section of the connecting member is exposed to form a depth-controlled groove; vertically install the chip in the corresponding depth-controlled groove, and connect the side surface of the chip to the connecting member.

[0081] Perform depth control on the preset positions of each first plastic encapsulation layer until the cross-section of the connecting member is exposed to form a depth-controlled groove, where the preset position partially overlaps with the connecting member. Among them, the depth-controlled groove can be depth-controlled by mechanical, laser or chemical means.

[0082] The depth-controlled groove is opened on the connecting member, that is, local depth control is performed based on the position of the connecting member until the cross-section of the connecting member is exposed to form a depth-controlled groove. The groove wall of the depth-controlled groove is formed by the connecting member and the first plastic encapsulation layer.

[0083] The depth-controlled groove is used to install the chip. When multiple packages are to be prepared on one side of the carrier board and / or multiple chips need to be installed on one package, this step prepares multiple depth-controlled grooves on the opposite sides of the carrier board respectively.

[0084] Vertically install the chip in the corresponding depth-controlled groove, and connect the side surface of the chip to the connecting member. A chip is installed in each depth-controlled groove. Since the pads of the chip are arranged on its side surface, therefore, by vertically arranging it in the depth-controlled groove, the pads on the side surface of the chip can be directly connected to the connecting member exposed through the depth-controlled groove, so as to realize the vertical installation of the chip, and the vertical installation of the chip can simplify the connection path of the connecting member and improve the space utilization rate of the package.

[0085] After the chip is installed, the chip can be electrically connected to the connecting member, the first pad, the conductive layer, the second pad, and the component in sequence.

[0086] Please refer to Figure 7 , Figure 7 which Figure 2 is a schematic structural diagram of an implementation manner of the processing board in step S23 of the embodiment.

[0087] On the basis of the embodiment, at least one depth control groove (not marked in the figure) is opened on each first encapsulation layer 230, and the chip 270 is vertically installed in the depth control groove. Among them, the inner wall of the depth control groove is composed of the connecting member 260 and the first encapsulation layer 230. The pads of the chip 270 are formed on the side surface of the chip 270 and are connected to the connecting member 260 on the inner wall of the depth control groove. In this embodiment, pads can be provided on both opposite side surfaces of the chip 270, so as to be respectively connected to both sides of the connecting member 260 that is disconnected by depth control. In other embodiments, the chip 270 can be provided with pads on only one side, and it is connected to one side of the connecting member 260 that is disconnected by depth control. Among them, the chip 270 can be welded and fixed to the connecting member 260. Figure 6

[0088] By vertically arranging the chip 270 in the depth control groove, the pads on the side surface of the chip 270 can be directly connected to the connecting member 260 exposed through the depth control groove, so as to realize the vertical installation of the chip 270, and the vertical installation of the chip 270 can simplify the connection path of the connecting member 260 and improve the space utilization rate of the package.

[0089] Step S24: Perform second double-sided encapsulation on the opposite sides of the processing board to respectively form second encapsulation layers on the sides of each first encapsulation layer away from the carrier board; press an enhancement sheet and coat a solder resist layer in sequence on the sides of each second encapsulation layer away from the carrier board; perform sub-board cutting on the carrier board to obtain at least two packages.

[0090] After the chip installation is completed, perform second double-sided encapsulation on the opposite sides of the processing board to respectively form second encapsulation layers on the sides of each first encapsulation layer away from the carrier board. The second encapsulation layer covers the chip and the connecting member.

[0091] The second encapsulation layer can specifically include one or more of epoxy resin type, polyimide type, bismaleimide triazine (BT) type, ceramic matrix type, etc. No limitation is made here.

[0092] ​Because the second plastic encapsulation in this step is double-sided, force is applied simultaneously to both sides of the processed plate during the plastic encapsulation process, ensuring balanced force on the connectors on the processed plate during the plastic encapsulation process. This can reduce warping during the package manufacturing process and improve the structural stability and reliability of the package. The double-sided plastic encapsulation of both the first and second plastic encapsulations in this embodiment can improve balance during the package manufacturing process and reduce the problem of uneven force during the package manufacturing process. After the second plastic encapsulation, the first and second plastic encapsulation layers can form a single plastic encapsulation layer.

[0093] After the second plastic encapsulation, a reinforcement sheet and a solder mask are laminated on the side of each second plastic encapsulation layer away from the substrate. The reinforcement sheet increases the structural rigidity and stability of the package, while the solder mask improves the insulation of the package surface to reduce short circuits with other devices. The solder mask can include an insulating material such as ink.

[0094] See also Figure 8 , Figure 8 yes Figure 2 A structural diagram of an implementation method of processing a plate in step S24 of the embodiment.

[0095] The processing plate 204 of this embodiment is Figure 7 Based on the embodiment, a second plastic packaging layer 280 is laminated on a side of each first plastic packaging layer 230 away from the carrier 200 , and each second plastic packaging layer 280 covers the chip 270 and the connector 260 on the corresponding side.

[0096] A reinforcement sheet 291 is attached to a side of the second plastic layer 280 away from the carrier 200 , and a solder resist layer 292 is attached to a side of the reinforcement sheet 291 away from the carrier 200 .

[0097] The carrier board is separated into at least two packages. Specifically, the first dielectric layer of the carrier board is removed to separate the carrier board, and the exposed conductive layer after separation is pattern-etched to form conductive circuits to obtain at least two packages. The specific shape of the conductive circuits can be set based on actual conditions and is not limited here.

[0098] After the surface of the package is coated with a protective layer, it can be put into storage.

[0099] In a specific application scenario, when a carrier board is used to prepare batch packages, the carrier board can be cut after being separated to obtain multiple independent packages.

[0100] Through the above steps, the method for manufacturing the package of this embodiment forms connectors on the first encapsulation layers on both sides of the processing board and performs local depth control based on the positions of the connectors to form depth-controlled grooves, so as to vertically install the chip in the depth-controlled grooves. Furthermore, the pads on the side of the chip can be directly connected to the connectors exposed through the depth-controlled grooves, thereby enabling the vertical installation of the chip. The vertical installation of the chip can simplify the connection path of the connectors and improve the space utilization rate of the package. Moreover, by using a double-sided carrier board for connector preparation, chip installation, and encapsulation, packages can be respectively manufactured on the opposite sides of the carrier board, which can increase the production yield of package manufacturing and further improve the efficiency of package manufacturing. In addition, the first encapsulation and the second encapsulation in this embodiment are both double-sided encapsulations, which can improve the balance during the package manufacturing process, reduce the problem of uneven stress during the package manufacturing process, reduce the problem of warping generated during the package manufacturing process, and improve the structural stability and reliability of the package.

[0101] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of an embodiment of the package provided by the present invention.

[0102] The package 900 of this embodiment includes an encapsulation layer 980, a chip 970, and a connector 960.

[0103] A depth-controlled groove (not labeled in the figure) is formed inside the encapsulation layer 980, and a pad 940 is formed on one side of the encapsulation layer 980. The chip 970 is vertically accommodated in the depth-controlled groove. The numbers of the chip 970 and the connector 960 can be one or more respectively, which are not limited herein.

[0104] One end of the connector 960 is connected to the corresponding pad 940, and the other end of the connector 960 is connected to the side surface of the chip 970 to lead out the electrical signal of the chip 970 from the package 900.

[0105] When pads are formed on one side of the chip 970, one end of a connector 960 is connected to the corresponding pad 940, and the other end of the connector 960 is connected to the pad on the side surface of the chip 970.

[0106] When pads are formed on both sides of the chip 970, one ends of two connectors 960 are connected to the corresponding pads 940, and the other ends of the two connectors 960 are respectively connected to the pads on the opposite sides of the chip 970.

[0107] Through the above structure, the package of this embodiment can achieve the vertical installation of the chip through the cooperation of the connector and the depth-controlled groove, thereby simplifying the connection path of the connector and improving the space utilization rate of the package.

[0108] In other embodiments, a first pad 941 and a second pad 942 are formed on one side of the plastic encapsulation layer 980, that is, the pad 940 includes the first pad 941 and the second pad 942. The first pad 941 refers to the pad 940 electrically connected to the chip 970 through the connection member 960; the second pad 942 refers to the pad 940 for mounting the component 920.

[0109] One end of the connection member 960 is connected to the corresponding first pad 941, and the other end of the connection member 960 is connected to the side surface of the chip 970;

[0110] The component 920 is mounted on one side of the second pad 942 close to the plastic encapsulation layer 980.

[0111] In other embodiments, a second dielectric layer 914 is formed on one side of the plastic encapsulation layer 980, a conductive circuit 990 is formed on the side of the second dielectric layer 914 away from the plastic encapsulation layer 980, and a conductive via 915 is formed on the second dielectric layer 914.

[0112] The conductive circuit 990 is connected to the corresponding first pad 941 or second pad 942 through the corresponding conductive via 915.

[0113] Then, the component 920 can be externally connected through the second pad 942, the conductive via 915, and the conductive circuit 990 in sequence. The chip 970 can be externally connected through the connection member 960, the first pad 941, the conductive via 915, and the conductive circuit 990 in sequence.

[0114] The package 900 of this embodiment can be prepared based on Figure 4 the carrier board of the implementation manner. The package 900 of this embodiment can enhance the structural stability of the package and improve the reliability of the package.

[0115] Among them, the conductive circuit 990 may include an external pad connected to the pad 940 and a circuit connecting the external pads.

[0116] In other embodiments, a reinforcing sheet 991 may be adhesively disposed on the side of the plastic encapsulation layer 980 away from the conductive circuit 990 to improve the structural rigidity of the package 900.

[0117] In other embodiments, a solder mask layer 992 may be adhesively disposed on the side of the reinforcing sheet 991 away from the conductive circuit 990 to enhance the surface insulation of the package 900.

[0118] Please refer to Figure 10 , Figure 10 which is a schematic structural diagram of another embodiment of the package provided by the present invention.

[0119] The positions and connection relationships among the reinforcing sheet, solder mask, chip 1070, connecting member 1060, encapsulation layer 1080, component 1020, solder pad 1040, first solder pad 1041, and second solder pad 1042 of the encapsulation body 1000 in this embodiment are the same as those in the foregoing embodiments. Please refer to the foregoing text and will not be elaborated herein.

[0120] On one side of the encapsulation layer 1080 in this embodiment, a conductive circuit 1015 is disposed in a fitting manner. The conductive circuit 1015 is connected to at least a part of the first solder pad 1041 and / or the second solder pad 1042. Thereby, the component 1020 can achieve external connection in sequence through the second solder pad 1042 and the conductive circuit 990. The chip 1070 can achieve external connection in sequence through the connecting member 1060, the first solder pad 1041, and the conductive circuit 990.

[0121] Among them, the conductive circuit 1090 may include an external solder pad connected to the solder pad 1040 and a circuit connecting the external solder pads.

[0122] The encapsulation body 1000 in this embodiment is convenient to achieve miniaturization and light weight.

[0123] The encapsulation body 1000 in this embodiment may be prepared based on Figure 3 the carrier board of the implementation manner.

[0124] The above are only the implementation manners of the present invention, and thus do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A method for preparing a package, characterized in that, The method for preparing the package includes: Obtaining a processing board, where the processing board includes a carrier board with pads formed on opposite sides and first encapsulation layers respectively attached to opposite sides of the carrier board, and the pads include a first pad and a second pad; it includes: obtaining a carrier board with pads formed on both opposite sides; mounting components on the second pad; performing first double-sided encapsulation on opposite sides of the carrier board to respectively form first encapsulation layers on opposite sides of the carrier board, thereby obtaining the processing board; Preparing connectors connecting to the corresponding pads on one side of each of the first encapsulation layers away from the carrier board; it includes: drilling holes in each of the first encapsulation layers based on the positions of the first pads to obtain blind holes respectively exposing the first pads; metallizing each of the blind holes until obtaining connectors attached to one side of each of the first encapsulation layers away from the carrier board; wherein, each end of the connector extends along the corresponding blind hole to connect to the corresponding first pad; Performing depth control on preset positions of each of the first encapsulation layers until the cross-section of the connector is exposed to form a depth control groove; wherein, the preset position partially overlaps with the connector; Vertically mounting the chip in the corresponding depth control groove and connecting the side of the chip to the connector; Forming second encapsulation layers on one side of each of the first encapsulation layers away from the carrier board and performing panel cutting on the carrier board to obtain at least two packages.

2. The method for preparing the package according to claim 1, wherein The step of forming second encapsulation layers on one side of each of the first encapsulation layers away from the carrier board and performing panel cutting on the carrier board to obtain at least two packages includes: Performing second double-sided encapsulation on opposite sides of the processing board to respectively form second encapsulation layers on one side of each of the first encapsulation layers away from the carrier board; Pressing reinforcement sheets and coating solder resist layers in sequence on one side of each of the second encapsulation layers away from the carrier board; Performing panel cutting on the carrier board to obtain at least two packages.

3. The method for preparing the package according to claim 1, wherein, The carrier board includes a substrate and pads formed on opposite sides of the substrate; The substrate of the carrier board includes a conductive layer, a first dielectric layer, and a conductive layer that are sequentially laminated and attached; or The substrate of the carrier board includes a second dielectric layer, a conductive layer, a first dielectric layer, a conductive layer, and a second dielectric layer; wherein, conductive holes are formed on each of the second dielectric layers to connect the pads of the carrier board and the corresponding conductive layers.

4. The method for preparing the package according to claim 3, wherein The step of performing panel cutting on the carrier board to obtain at least two packages includes: Removing the first dielectric layer to perform panel cutting on the carrier board; Etching the exposed conductive layer to obtain at least two packages.

5. A package, characterized in that, The package is prepared by the method for preparing the package according to any one of claims 1-4 above, and includes: An encapsulation layer, a depth control groove is formed inside the encapsulation layer, and a pad is formed on one side of the encapsulation layer; A chip, the chip is vertically accommodated in the depth control groove; A connector, one end of the connector is connected to the corresponding pad, and the other end of the connector is connected to the side of the chip to lead out the electrical signal of the chip from the package.

6. The package according to claim 5, wherein: a first pad and a second pad are formed on one side of the plastic encapsulation layer; one end of the connecting member is connected to the corresponding first pad, and the other end of the connecting member is connected to the side surface of the chip; a component is mounted on one side of the second pad close to the plastic encapsulation layer.

7. The package according to claim 6, wherein: a second dielectric layer is formed on one side of the plastic encapsulation layer, a conductive circuit is formed on a side of the second dielectric layer away from the plastic encapsulation layer, and conductive vias are formed on the second dielectric layer; the conductive circuit is connected to the corresponding first pad or second pad through the corresponding conductive via.

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