Chip Stacking Structure and Method of Manufacturing the Same

Abstract

The present invention discloses a wafer stacking structure and a manufacturing method thereof. The wafer stacking structure includes an interposer, a first wafer, and a second wafer. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes a dielectric material layer and a redistribution line layer buried in the dielectric material layer. The first wafer is disposed on the first surface of the interposer. The second wafer is disposed on the second surface of the interposer. The second wafer is electrically connected to the first wafer through the redistribution line layer of the interposer.

Description

Technical Field

[0001] The present invention relates to a wafer structure, and more particularly to a wafer stack structure and a manufacturing method thereof. Background Art

[0002] Generally, a random access memory (RAM) and a logic chip are configured and integrated in a horizontal manner. Specifically, the memory and the logic chip are respectively connected to a substrate through solder bumps or solder balls in a flip-chip manner, and then, the memory and the logic chip can be electrically connected through in-plane routing in the substrate. However, such an integration method will result in a longer electrical transmission path between the memory and the logic chip, a larger interconnection loss, and a larger package size. Summary of the Invention

[0003] The present invention provides a wafer stack structure that can shorten the electrical transmission path between a first wafer and a second wafer to have better power consumption.

[0004] The present invention provides a manufacturing method of a wafer stack structure, which has the effect of simplifying the manufacturing process or improving the production yield of the manufacturing process.

[0005] The wafer stack structure of the present invention includes an interposer, a first wafer, and a second wafer. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes a dielectric material layer and a redistribution layer buried in the dielectric material layer. The first wafer is disposed on the first surface of the interposer. The second wafer is disposed on the second surface of the interposer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interposer.

[0006] In an embodiment of the present invention, the above-mentioned first wafer includes a plurality of first conductive contacts, and the second wafer includes a plurality of second conductive contacts. The first conductive contacts are in contact with the redistribution layer. The second conductive contacts are in contact with the redistribution layer.

[0007] In an embodiment of the present invention, the above-mentioned first conductive contacts are columnar metals protruding from the first wafer, and the second conductive contacts are columnar metals protruding from the second wafer.

[0008] In an embodiment of the present invention, at least one of the first conductive contacts does not overlap at least one of the second conductive contacts in the normal direction of the wafer stack structure.

[0009] In an embodiment of the present invention, the above-mentioned interposer further includes a plurality of openings. The openings are disposed on the first surface and the second surface to expose the redistribution layer.

[0010] In an embodiment of the present invention, the above-mentioned redistribution layer includes a first circuit layer, a second circuit layer, and a plurality of conductive vias. The first circuit layer contacts the first conductive contact. The second circuit layer contacts the second conductive contact. The conductive vias electrically connect the first circuit layer and the second circuit layer.

[0011] In an embodiment of the present invention, the above-mentioned second wafer, interposer, and first wafer overlap in the normal direction of the wafer stack structure.

[0012] In an embodiment of the present invention, the materials of the above-mentioned first wafer and second wafer are different from the material of the dielectric material layer.

[0013] In an embodiment of the present invention, the material of the above-mentioned dielectric layer is an organic or inorganic dielectric material.

[0014] In an embodiment of the present invention, the material of the above-mentioned dielectric layer is aluminum nitride, benzocyclobutene, polyimide, or Ajinomoto IC substrate build-up film.

[0015] In an embodiment of the present invention, the above-mentioned wafer stack structure further includes a first adhesive layer and a second adhesive layer. The first adhesive layer is disposed between the first wafer and the first surface of the interposer. The second adhesive layer is disposed between the second wafer and the second surface of the interposer.

[0016] In an embodiment of the present invention, the above-mentioned interposer further includes a shielding structure and an antenna structure. The shielding structure is buried in the interposer to shield the radiation signal from the second wafer. The antenna structure is disposed on the side of the interposer to transmit and / or receive signals.

[0017] In an embodiment of the present invention, the above-mentioned shielding structure is grounded. The shielding structure and the first wafer and the second wafer form a common ground structure.

[0018] A method for manufacturing the wafer stack structure of the present invention includes the following steps. Provide an interposer. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes a dielectric material layer and a redistribution layer buried in the dielectric material layer. Bond a first wafer on the first surface of the interposer. Bond a second wafer on the second surface of the interposer so that the second wafer is electrically connected to the first wafer through the redistribution layer of the interposer.

[0019] In an embodiment of the present invention, the step of providing the interposer includes the following steps. Provide a wafer or a glass substrate. Form an interposer on the wafer or the glass substrate. Remove the wafer or the glass substrate to expose the second surface of the interposer.

[0020] In an embodiment of the present invention, the step of bonding the first wafer to the first surface of the interposer includes the following steps. Form a plurality of openings in the first surface of the interposer to expose the redistribution layer. Make a plurality of first conductive contacts of the first wafer contact the redistribution layer through the openings.

[0021] In an embodiment of the present invention, the step of bonding the second wafer to the second surface of the interposer includes the following steps. Form a plurality of openings in the second surface of the interposer to expose the redistribution layer. Make a plurality of second conductive contacts of the second wafer contact the redistribution layer through the openings.

[0022] In an embodiment of the present invention, the manufacturing method of the above wafer stack structure further includes the following steps. Form a first adhesive layer between the first wafer and the first surface of the interposer. Form a second adhesive layer between the second wafer and the second surface of the interposer.

[0023] Based on the above, in the wafer stack structure and its manufacturing method according to the embodiments of the present invention, by disposing the first wafer on the first surface of the interposer, disposing the second wafer on the second surface of the interposer, and enabling the second wafer to be electrically connected to the first wafer through the redistribution layer of the interposer, the electrical transmission path between the first wafer and the second wafer can be shortened, so that the wafer stack structure of this embodiment can have better power consumption, and the manufacturing method of the wafer stack structure of this embodiment can have the effects of simplifying the manufacturing process or improving the manufacturing process yield.

[0024] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0025] Figures 1A to 1C is a cross-sectional schematic diagram of a manufacturing method of a wafer stack structure according to an embodiment of the present invention;

[0026] Figures 2A to 2C is a cross-sectional schematic diagram of a manufacturing method of a wafer stack structure according to another embodiment of the present invention;

[0027] Figure 3 is a cross-sectional schematic diagram of a wafer stack structure according to still another embodiment of the present invention.

[0028] Symbol Description

[0029] 10, 10a, 10b: Wafer stack structure

[0030] 100, 100a, 100b: Interposer

[0031] 102: First surface

[0032] 104: Second surface

[0033] 110: Dielectric material layer

[0034] 120: Redistribution layer

[0035] 121: First wiring layer

[0036] 122: Second wiring layer

[0037] 123: Third wiring layer

[0038] 124, 125: Conductive via

[0039] 130: First adhesive layer

[0040] 140: Second adhesive layer

[0041] 150: Shielding structure

[0042] 160: Antenna structure

[0043] 200: First chip

[0044] 202, 302: Front surface

[0045] 204, 304: Back surface

[0046] 210, 310: Substrate structure

[0047] 220, 320: Dielectric layer

[0048] 230: First conductive contact

[0049] 300: Second chip

[0050] 330: Second conductive contact

[0051] 340: Radio frequency circuit

[0052] OP1, OP1a, OP2, OP2a: Opening

[0053] Y: Direction Detailed implementation manners

[0054] Figures 1A to 1C is a cross-sectional schematic view of a manufacturing method of a chip stack structure according to an embodiment of the present invention.

[0055] First, please refer to Figure 1A, an interposer layer 100 is provided. Specifically, in this embodiment, the interposer layer 100 has a first surface 102 and a second surface 104 opposite to the first surface 102, and the interposer layer 100 includes a dielectric material layer 110 and a redistribution layer 120 buried in the dielectric material layer 110. In other words, the redistribution layer 120 can be buried in the dielectric material layer 110 of the interposer layer 100, but is not limited thereto.

[0056] In this embodiment, the redistribution layer 120 may include a first circuit layer 121, a second circuit layer 122, a third circuit layer 123, and a plurality of conductive vias 124, 125. The first circuit layer 121 and the second circuit layer 122 are respectively located on opposite sides of the third circuit layer 123. The first circuit layer 121 and the second circuit layer 122 are respectively adjacent to and do not directly contact the first surface 102 and the second surface 104 of the interposer layer 100. The first circuit layer 121 is connected to the third circuit layer 123 through the conductive via 124, and the second circuit layer 122 is connected to the third circuit layer 123 through the conductive via 125. That is to say, the first circuit layer 121 can be electrically connected to the second circuit layer 122 through the conductive via 124, the third circuit layer 123, and the conductive via 125. Here, the materials of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, and the plurality of conductive vias 124, 125 can be, for example, metal conductive materials such as copper or aluminum, but the present invention is not limited thereto.

[0057] In this embodiment, a single layer of the third circuit layer 123 is schematically shown, but the present invention does not limit the number of the third circuit layers 123. That is to say, in some embodiments, the third circuit layer may not be provided as needed, so that the first circuit layer can be electrically connected to a second circuit layer (not shown) only through a conductive via. In some embodiments, multiple layers of the third circuit layer can be provided as needed, so that the first circuit layer needs to be electrically connected to the second circuit layer through a conductive via and multiple layers of the third circuit layer.

[0058] In this embodiment, the material of the dielectric material layer 110 can be an organic dielectric material or an inorganic dielectric material. For example, the organic dielectric material can be, for example, benzocyclobutene (BCB), polyimide (PI), Ajinomoto Build-up Film (ABF), or other similar materials; the inorganic dielectric material can be, for example, aluminum nitride, an oxide layer, or other similar materials, but the present invention is not limited thereto.

[0059] In this embodiment, the steps of providing the interposer 100 may include, for example, but are not limited to the following steps: First, a wafer (not shown) or a glass substrate (not shown) is provided as a temporary substrate; then, an interposer 100 with a redistributed wiring layer 120 embedded therein is formed on the wafer or the glass substrate, wherein the second surface 104 of the interposer 100 faces the wafer or the glass substrate; thereafter, the wafer or the glass substrate is removed to expose the second surface 104 of the interposer 100.

[0060] Then, refer to Figure 1B , and provide a first wafer 200 and a second wafer 300. Specifically, the first wafer 200 of this embodiment has a front surface 202 and a back surface 204 opposite to the front surface 202. The first wafer 200 includes a substrate structure 210, a dielectric layer 220, and a plurality of first conductive contacts 230. The substrate structure 210 is adjacent to the back surface 204. The substrate structure 210 may include a substrate (e.g., a silicon substrate), a doped region, an electrode, a dielectric layer, a first semiconductor element, an interconnect element, or a combination thereof (not shown), but the present invention is not limited thereto, and those of ordinary skill in the art can adjust the composition of the substrate structure 210 according to product requirements. The dielectric layer 220 is formed on the substrate structure 210 and adjacent to the front surface 202. The material of the dielectric layer 220 may be an oxide layer (e.g., silicon oxide) or polysilicon, but the present invention is not limited thereto. In some embodiments, the material of the dielectric layer 220 may be different from the material of the dielectric material layer 110. In this embodiment, the first conductive contacts 230 may be columnar metals (e.g., copper pillars) or pads protruding from the first wafer 200, and the first conductive contacts 230 are not solder bumps or solder balls that require reflow, thereby reducing the pitch between adjacent first conductive contacts 230 and / or the height of the first conductive contacts 230, and further reducing the package size of the wafer stack structure 10 to meet the requirements of miniaturization. Among them, the first conductive contacts 230 are disposed in the dielectric layer 220 and extend to protrude from the front surface 202 of the first wafer 200. The first conductive contacts 230 may be electrically connected to circuit elements such as semiconductor elements or interconnect elements of the substrate structure 210.

[0061] In this embodiment, the second wafer 300 has a front surface 302 and a back surface 304 opposite to the front surface 302. Specifically, the second wafer 300 includes a substrate structure 310, a dielectric layer 320, and a plurality of second conductive contacts 330. The substrate structure 310 is adjacent to the back surface 304. The substrate structure 310 may include a substrate (e.g., a silicon substrate), a doped region, an electrode, a dielectric layer, a second semiconductor element, an interconnection element, or a combination thereof (not shown), but the present invention is not limited thereto, and those skilled in the art can adjust the composition of the substrate structure 310 according to product requirements. The dielectric layer 320 is formed on the substrate structure 310 and adjacent to the front surface 302. The material of the dielectric layer 320 may be an oxide layer (e.g., silicon oxide) or polysilicon, but the present invention is not limited thereto. In some embodiments, the material of the dielectric layer 320 may be different from the material of the dielectric material layer 110. The second conductive contacts 330 may be columnar metals (e.g., copper pillars) or pads protruding from the second wafer 300, and the second conductive contacts 330 are not solder bumps. Among them, the second conductive contacts 330 may be disposed in the dielectric layer 220 and extend to protrude from the front surface 202 of the second wafer 300. The second conductive contacts 330 may be electrically connected to circuit elements such as semiconductor elements or interconnection elements of the substrate structure 310.

[0062] In this embodiment, the first semiconductor element of the first wafer 200 and the second semiconductor element of the second wafer 300 may perform different functions respectively. For example, the first semiconductor element may be a random access memory (RAM), and the second semiconductor element may be a logic chip, but not limited thereto. That is to say, in some embodiments, the first semiconductor element may be a logic chip, and the second semiconductor element may be a memory.

[0063] Next, please continue to refer to Figure 1B, a plurality of openings OP1 are formed on the first surface 102 of the interposer 100 to expose a part of the first circuit layer 121 in the redistribution layer 120; and a plurality of openings OP2 are formed on the second surface 104 of the interposer 100 to expose a part of the second circuit layer 122 in the redistribution layer 120. Specifically, the interposer 100 includes a plurality of openings OP1 and a plurality of openings OP2. The openings OP1 are disposed on the first surface 102 of the interposer 100, and the openings OP2 are disposed on the second surface 104 of the interposer 100. Each opening OP1 can be respectively corresponding to the first conductive contact 230 of the first wafer 200, so that the first conductive contact 230 can contact the first circuit layer 121 through the corresponding opening OP1 in subsequent steps. Each opening OP2 can be respectively corresponding to the second conductive contact 330 of the second wafer 300, so that the second conductive contact 330 can contact the second circuit layer 122 through the corresponding opening OP2 in subsequent steps. In addition, in this embodiment, the method of forming the openings OP1 and OP2 can be, for example, a photolithography etching manufacturing process, but the present invention is not limited thereto.

[0064] Then, please refer to Figure 1B and Figure 1C simultaneously, bond the first wafer 200 onto the first surface 102 of the interposer 100, and bond the second wafer 300 onto the second surface 104 of the interposer 100, so that the second wafer 300 can be electrically connected to the first wafer 200 through the redistribution layer 120 of the interposer 100. Specifically, the first conductive contact 230 of the first wafer 200 can contact the first circuit layer 121 of the redistribution layer 120 through the opening OP1, and the second conductive contact 330 of the second wafer 300 can contact the second circuit layer 122 of the redistribution layer 120 through the opening OP2. Thus, the front surface 202 of the first wafer 200 and the front surface 302 of the second wafer 300 can respectively contact the first surface 102 and the second surface 104 of the interposer 100, and the first wafer 200 and the second wafer 300 can be respectively disposed on opposite sides of the interposer 100.

[0065] In this embodiment, since the first conductive contact 230 and the second conductive contact 330 can be electrically connected through the redistribution line layer 120 of the interposer 100, at least one of the first conductive contacts 230 in the first conductive contact 230 may not overlap at least one of the second conductive contacts 330 in the second conductive contact 330 in the normal direction (direction Y) of the wafer stack structure 10. In addition, in this embodiment, compared with a wafer stack structure that generally does not provide an interposer and must join two wafers in a pin-to-pin manner (i.e., the first conductive contact of the first wafer needs to be aligned and overlapped with the corresponding second conductive contact in the second wafer), the wafer stack structure 10 of this embodiment can be re-wired through the redistribution line layer 120 of the interposer 100, so that the first conductive contact 230 and the second conductive contact 330 can be electrically connected through the redistribution line layer 120, thereby omitting the manufacturing process of pin docking and having the effect of simplifying the manufacturing process or improving the manufacturing process yield. Thus, wafers manufactured by different wafer foundries can also be easily applied to the wafer stack structure 10 of this embodiment.

[0066] In this embodiment, by disposing the interposer 100 between the first wafer 200 and the second wafer 300, in addition to enabling the wafer stack structure 10 to have a better heat dissipation effect, it can also serve as a stress buffer layer to reduce the stress generated when the first wafer 200 is stacked on the second wafer 300.

[0067] In this embodiment, the first wafer 200, the interposer 100, and the second wafer 300 can be stacked and integrated vertically, and the first wafer 200, the interposer 100, and the second wafer 300 may overlap in the normal direction (direction Y) of the wafer stack structure 10. Thus, the first semiconductor element in the first wafer 200 can be vertically electrically connected to the second semiconductor element disposed in the second wafer 300 through the first conductive contact 230, the redistribution line layer 120, and the second conductive contact 330. Therefore, compared with a packaging structure that generally configures two chips horizontally, the wafer stack structure 10 of this embodiment not only can shorten the electrical transmission path between the first wafer 200 and the second wafer 300 to have better power consumption, but also can simplify the manufacturing process to improve the manufacturing process yield.

[0068] In this embodiment, the first wafer 200 and the second wafer 300 are joined, for example, in a face-to-face manner, that is, the front surface 202 of the first wafer 200 faces the front surface 302 of the second wafer 300, but the present invention is not limited thereto. In some embodiments, the first wafer 200 and the second wafer 300 can also be joined in a face-to-back manner, for example, the back surface 204 of the first wafer 200 faces the front surface 302 of the second wafer 300 (not shown). Thus, the wafer stack structure 10 of this embodiment has been manufactured.

[0069] Other embodiments will be listed below for illustration. It must be noted here that the following embodiments follow the component numbers and some content of the foregoing embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0070] Figures 2A to 2C It is a cross-sectional schematic view of a method for manufacturing a wafer stack structure according to another embodiment of the present invention. Figures 2A to 2C The illustrated embodiment is similar to Figures 1A to 1C the illustrated embodiment, so the same components are denoted by the same numbers, and their detailed content will not be repeated. Figures 2A to 2C The illustrated embodiment is different from Figures 1A to 1C the first embodiment shown in that in the wafer stack structure 10a of this embodiment, a first adhesive layer 130 and a second adhesive layer 140 are further included.

[0071] Specifically, please refer to Figure 2A , compared with Figure 1A , the method for manufacturing the wafer stack structure 10a of this embodiment further includes the following steps: forming a first adhesive layer 130 on the first surface 102 of the interposer 100a, and forming a second adhesive layer 140 on the second surface 104 of the interposer 100a.

[0072] Next, please refer to Figure 2B , compared with Figure 1B , in the method for manufacturing the wafer stack structure 10a of this embodiment, for example, a photolithography etching process is used to etch the first adhesive layer 130, the second adhesive layer 140, and the dielectric material layer 110 to form a plurality of openings OP1a and a plurality of openings OP2a. Among them, a plurality of openings OP1 can expose a part of the first wiring layer 121 in the redistribution layer 120, and a plurality of openings OP2 can expose a part of the second wiring layer 122 in the redistribution layer 120.

[0073] Next, please refer to Figure 2B andFigure 2C , compared with Figure 1B and Figure 1C , in the manufacturing method of the wafer stack structure 10a of the present embodiment, the first conductive contact 230 of the first wafer 200 can contact and bond to the first circuit layer 121 of the redistribution layer 120 through the opening OP1a, and the second conductive contact 330 of the second wafer 300 can contact and bond to the second circuit layer 122 of the redistribution layer 120 through the opening OP2a. Among them, since the first adhesive layer 130 is disposed between the front surface 202 of the first wafer 200 and the first surface 102 of the interposer 100a, and the second adhesive layer 140 is disposed between the front surface 302 of the second wafer 300 and the second surface 104 of the interposer 100a, the adhesion between the first wafer 200 and the interposer 100a can be increased, and the adhesion between the second wafer 300 and the interposer 100a can be increased.

[0074] Figure 3 is a cross-sectional schematic view of a wafer stack structure according to another embodiment of the present invention. Please also refer to Figure 1C and Figure 3 , the wafer stack structure 10b of the present embodiment is similar to the wafer stack structure 10 in Figure 1C , but the main difference between the two is that: in the wafer stack structure 10b of the present embodiment, the interposer 100b further includes a shielding structure 150 and an antenna structure 160.

[0075] Specifically, please refer to Figure 3 , in the present embodiment, the second wafer 300 may further include a radiofrequency circuit 340. Therefore, in order to avoid the radiation signal emitted by the radiofrequency circuit 340 from interfering with the first wafer 200, a shielding structure 150 is further provided in the present embodiment. Among them, since the shielding structure 150 buried in the interposer 100b can be disposed corresponding to the radiofrequency circuit 340 and grounded, it can be used to shield the radiation signal emitted by the radiofrequency circuit 340 of the second wafer 300 as electromagnetic interference shielding (EMI shielding). In the present embodiment, in order to enable the wafer stack structure 10b to be applied to radiofrequency or 5G, etc., an antenna structure 160 is further provided on the side of the interposer 100b to transmit and / or receive signals.

[0076] In addition, in some embodiments, since the shielding structure 150 can also be electrically connected to the first wafer 200 and the second wafer 300 respectively, the first wafer 200 can be grounded through the shielding structure 150, and the second wafer 300 can be grounded through the shielding structure 150. That is to say, the shielding structure 150 can form a common ground structure with the first wafer 200 and the second wafer 300.

[0077] In summary, in the wafer stack structure and its manufacturing method according to the embodiments of the present invention, by disposing the first wafer on the first surface of the interposer, disposing the second wafer on the second surface of the interposer, and enabling the second wafer to be electrically connected to the first wafer through the redistribution layer of the interposer, the electrical transmission path between the first wafer and the second wafer can be shortened, so that the wafer stack structure of the present embodiment can have better power consumption, and the manufacturing method of the wafer stack structure of the present embodiment can have the effect of simplifying the manufacturing process or improving the manufacturing process yield. In addition, by disposing the interposer between the first wafer and the second wafer, in addition to enabling the wafer stack structure to have better heat dissipation effect, it can also serve as a stress buffer layer to reduce the stress generated when the first wafer is stacked on the second wafer. Additionally, through the re-wiring of the redistribution layer of the interposer, the first conductive contact and the second conductive contact can be electrically connected through the redistribution layer, so as to omit the manufacturing process of contact docking, and have the effect of simplifying the manufacturing process or improving the manufacturing process yield.

[0078] Although the present invention is disclosed in combination with the above embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A wafer stacking structure, comprising: An interposer having a first surface and a second surface opposite to the first surface, and comprising a dielectric material layer and a redistribution line layer buried in the dielectric material layer; A first wafer disposed on the first surface of the interposer; and A second wafer disposed on the second surface of the interposer, Wherein the second wafer is electrically connected to the first wafer through the redistribution line layer of the interposer, Wherein the interposer further comprises a shielding structure and an antenna structure, the shielding structure is buried in the interposer to shield the radiation signal from the second wafer, and the antenna structure is disposed on the side of the interposer to transmit and / or receive signals.

2. The wafer stacking structure according to claim 1, wherein the first wafer comprises a plurality of first conductive contacts, the second wafer comprises a plurality of second conductive contacts, the first conductive contacts contact the redistribution line layer, and the second conductive contacts contact the redistribution line layer.

3. The wafer stacking structure according to claim 2, wherein the first conductive contacts are columnar metals protruding from the first wafer, and the second conductive contacts are columnar metals protruding from the second wafer.

4. The wafer stacking structure according to claim 2, wherein at least one of the first conductive contacts does not overlap with at least one of the second conductive contacts in the normal direction of the wafer stacking structure.

5. The wafer stacking structure according to claim 2, wherein the interposer further comprises a plurality of openings disposed on the first surface and the second surface to expose the redistribution line layer.

6. The wafer stacking structure according to claim 2, wherein the redistribution line layer comprises a first line layer, a second line layer, and a plurality of conductive vias, the first line layer contacts the first conductive contacts, the second line layer contacts the second conductive contacts, and the conductive vias electrically connect the first line layer and the second line layer.

7. The wafer stacking structure according to claim 1, wherein the second wafer, the interposer, and the first wafer overlap in the normal direction of the wafer stacking structure.

8. The wafer stacking structure according to claim 1, wherein the materials of the first wafer and the second wafer are different from the material of the dielectric material layer.

9. The wafer stacking structure according to claim 8, wherein the material of the dielectric material layer is an organic or inorganic dielectric material.

10. The wafer stacking structure according to claim 8, wherein the material of the dielectric material layer is aluminum nitride, benzocyclobutene, polyimide, or Ajinomoto IC carrier build-up film.

11. The wafer stacking structure according to claim 1, further comprising: A first adhesive layer disposed between the first wafer and the first surface of the interposer; And A second adhesive layer disposed between the second wafer and the second surface of the interposer.

12. The wafer stacking structure according to claim 11, wherein the shielding structure is grounded, and the shielding structure, the first wafer, and the second wafer form a common ground structure.

13. A manufacturing method of a wafer stacking structure, comprising: Provide an interposer, wherein the interposer has a first surface and a second surface opposite to the first surface, and the interposer includes a dielectric material layer and a redistribution line layer embedded in the dielectric material layer; Bond a first wafer to the first surface of the interposer; and Bond a second wafer to the second surface of the interposer, so that the second wafer is electrically connected to the first wafer through the redistribution line layer of the interposer, wherein the interposer further includes a shielding structure and an antenna structure, the shielding structure is embedded in the interposer to shield the radiation signal from the second wafer, and the antenna structure is disposed on the side of the interposer to transmit and / or receive signals.

14. The method of manufacturing a wafer stack structure according to claim 13, wherein the step of providing the interposer includes: Provide a wafer or a glass substrate; Form the interposer on the wafer or the glass substrate; And Remove the wafer or the glass substrate to expose the second surface of the interposer.

15. The method of manufacturing a wafer stack structure according to claim 13, wherein the step of bonding the first wafer to the first surface of the interposer includes: Form a plurality of openings on the first surface of the interposer to expose the redistribution line layer; Make a plurality of first conductive contacts of the first wafer contact the redistribution line layer through the openings.

16. The method of manufacturing a wafer stack structure according to claim 13, wherein the step of bonding the second wafer to the second surface of the interposer includes: Form a plurality of openings on the second surface of the interposer to expose the redistribution line layer; Make a plurality of second conductive contacts of the second wafer contact the redistribution line layer through the openings.

17. The method of manufacturing a wafer stack structure according to claim 13 further includes: Form a first adhesive layer between the first wafer and the first surface of the interposer; And Form a second adhesive layer between the second wafer and the second surface of the interposer.

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