Display panel and electronic device

Abstract

The application provides a display panel and an electronic device. The display panel comprises a substrate, a first wiring layer, a semiconductor layer, a dielectric layer and a first electrode layer. The first wiring layer is arranged on the substrate. The semiconductor layer is arranged on the side of the first wiring layer away from the substrate, and the semiconductor layer is electrically connected with the first wiring layer. The dielectric layer is arranged between the first wiring layer and the semiconductor layer. The first electrode layer is arranged on the side of the semiconductor layer away from the substrate, and is electrically connected with the semiconductor layer through the first wiring layer. The orthographic projection of the first wiring layer on the substrate covers the orthographic projection of the semiconductor layer on the substrate. The display panel can not only shield the light from the bottom of the semiconductor layer, but also will not increase the preparation cost of the product.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and an electronic device. Background Technology

[0002] Currently, medium and large-sized display panels typically use oxide semiconductors, such as indium gallium zinc oxide (IGZO) devices. Since IGZO devices exhibit photogenerated carrier effects, array designs often incorporate a light-shielding layer beneath the semiconductor device to block light from below. However, fabricating this light-shielding layer adds a masking process, increasing manufacturing costs. Summary of the Invention

[0003] The display panel and electronic device provided in this application can not only shield the semiconductor layer from light, but also do not increase the manufacturing cost of the product.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is to provide a display panel. The display panel includes: a substrate, a first wiring layer, a semiconductor layer, and a first electrode layer; wherein the first wiring layer is disposed on the substrate; the semiconductor layer is disposed on the side of the first wiring layer opposite to the substrate; and the semiconductor layer is electrically connected to the first wiring layer; a dielectric layer is disposed between the first wiring layer and the semiconductor layer; the first electrode layer is disposed on the side of the semiconductor layer opposite to the substrate and is electrically connected to the semiconductor layer through the first wiring layer; wherein the orthographic projection of the first wiring layer on the substrate covers the orthographic projection of the semiconductor layer on the substrate.

[0005] In one specific embodiment, the display panel further includes a second wiring layer stacked between the first wiring layer and the semiconductor layer; the second wiring layer includes a plurality of source electrodes and a plurality of drain electrodes, the drain electrodes of the second wiring layer are electrically connected to the drain portions of the first wiring layer and the semiconductor layer respectively; the first wiring layer is connected to the drain portion through the second wiring layer.

[0006] In one specific embodiment, the orthographic projection of the second wiring layer on the substrate covers at least a portion of the orthographic projection of the semiconductor layer on the substrate;

[0007] Preferably, the orthographic projection of the first wiring layer on the substrate completely covers the orthographic projection of the semiconductor layer on the substrate;

[0008] Preferably, the orthographic projection of the first electrode layer on the substrate completely covers the orthographic projection of the semiconductor layer on the substrate.

[0009] In one specific embodiment, a third wiring layer is further included, the third wiring layer including a plurality of gates; the third wiring layer is disposed between the semiconductor layer and the second wiring layer.

[0010] In one specific embodiment, the second trace layer and the third trace layer are insulated from each other so that the second trace layer and the third trace layer form the two electrode plates of a capacitor.

[0011] In one specific embodiment, one or more of the first wiring layer, the second wiring layer, and the third wiring layer are made of titanium-aluminum-titanium alloy.

[0012] In one specific embodiment, the dielectric layer includes: a first dielectric layer, which is stacked on the side surface of the substrate facing the first wiring layer and covers the first wiring layer;

[0013] The second dielectric layer is stacked on the side of the first dielectric layer facing away from the substrate and covers the second wiring layer.

[0014] A third dielectric layer is stacked on the side of the second dielectric layer facing away from the first dielectric layer and covers the semiconductor layer.

[0015] In one specific embodiment, it further includes: a planarization layer disposed on the side of the third dielectric layer opposite to the substrate; and a first electrode layer disposed on the surface of the planarization layer opposite to the substrate.

[0016] A conductive pillar extends from the planarization layer away from the substrate surface into the first dielectric layer, and the two ends of the conductive pillar contact the first electrode layer and the first wiring layer, respectively, to electrically connect the first electrode layer and the first wiring layer.

[0017] In one specific embodiment, the semiconductor layer is made of indium gallium zinc oxide.

[0018] To solve the aforementioned technical problems, another technical solution adopted in this application is to provide an electronic device. This electronic device includes the display panel described above.

[0019] The beneficial effects of this application, which differ from the prior art, are as follows: The display panel and electronic device provided in the embodiments of this application, by forming a first wiring layer on a substrate, forming a semiconductor layer on the side of the first wiring layer opposite to the substrate, and making the orthogonal projection of the first wiring layer on the substrate cover the orthogonal projection of the semiconductor layer on the substrate, so as to shield the semiconductor layer from below through the first wiring layer. At the same time, by making the first electrode layer electrically connected to the semiconductor layer through the first wiring layer, the electrical connection between the semiconductor layer and the first electrode layer can be realized by using the first wiring layer, and the first wiring layer can be used for light shielding. Compared with the existing solution of adding another light shielding layer, there is no need to add a mask process to prepare the light shielding layer, and the manufacturing cost of the product will not be increased. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of the stacked structure of a display panel provided in a specific embodiment of this application;

[0022] Figure 2 A schematic diagram of the stacked structure of a display panel provided in another specific embodiment of this application;

[0023] Figure 3 A schematic diagram of the stacked structure of a display panel provided in another specific embodiment of this application;

[0024] Figure 4 A schematic diagram of the stacked structure of a display panel provided in another specific embodiment of this application;

[0025] Figure 5 A simplified structural diagram of an electronic device provided in an embodiment of this application.

[0026] Explanation of reference numerals in the attached figures:

[0027] 10-Display panel; 11-Substrate; 111-Flexible substrate; 112-Antistatic layer; 113-Barrier layer; 12-First wiring layer; 13-First dielectric layer; 14-Semiconductor layer; 15-First electrode layer; 16-Second wiring layer; 17-Second dielectric layer; 18-Third wiring layer; 19-Third dielectric layer; 21-Planarization layer; 22-Conductive pillar; 23-Fourth wiring layer; 24-Fourth dielectric layer. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the stacked structure of a display panel according to a specific embodiment of this application. In this embodiment, a display panel 10 is provided, which can be used to display images. The display panel 10 includes a substrate 11, a first wiring layer 12 (M1), a dielectric layer, a semiconductor layer 14, and a first electrode layer 15 stacked together. The dielectric layer is disposed between the first wiring layer 12 and the semiconductor layer 14. Specifically, the dielectric layer includes a first dielectric layer 13, a second dielectric layer 17, and a third dielectric layer 19 stacked sequentially.

[0033] The substrate 11 includes a flexible substrate 111, an antistatic layer 112, and a buffer layer 113, which are stacked sequentially. The flexible substrate 111 may be made of polyimide (PI). The antistatic layer 112 (BL2) may be made of SiOx and is used to prevent external static electricity. The buffer layer 113 may be made of SiNx and / or SiOx and is used to prevent metal ion diffusion and provide thermal insulation.

[0034] The first wiring layer 12 is disposed on the substrate 11 and located on the side surface of the barrier layer 113 facing away from the flexible substrate 111. The first wiring layer 12 may be a copper layer, a silver layer, etc. The first dielectric layer 13 is stacked on the side surface of the substrate 11 facing the first wiring layer 12 and covers the first wiring layer 12. The first dielectric layer 13 is an insulating layer, and the material of the first dielectric layer 13 may specifically be SiNx. In this application, X is a natural number greater than or equal to 1.

[0035] A semiconductor layer 14 is disposed on the side of the first wiring layer 12 facing away from the substrate 11; and the semiconductor layer 14 includes a channel portion and a source portion and a drain portion located on both sides of the channel portion. The drain portion of the semiconductor layer 14 is electrically connected to the first wiring layer 12. The material of the semiconductor layer 14 is indium gallium zinc oxide (IGZO). Of course, the material of the semiconductor layer 14 can also be IGZTO or ITZO.

[0036] The first electrode layer 15 is disposed on the side of the semiconductor layer 14 facing away from the substrate 11, and is electrically connected to the drain portion of the semiconductor layer 14 through the first wiring layer 12. It can be understood that, in this embodiment, the first wiring layer 12 serves as a metal trace to electrically connect the first electrode layer 15 and the semiconductor layer 14. In this embodiment, the first electrode layer 15 is an anode layer.

[0037] Specifically, such as Figure 1 As shown, the orthogonal projection of the first electrode layer 15 on the substrate 11 completely covers the orthogonal projection of the semiconductor layer 14 on the substrate 11, so as to shield the semiconductor layer 14 from the side (i.e. above) away from the substrate 11 by the first electrode layer 15, so as to further reduce the photogenerated carrier effect.

[0038] Specifically, the orthographic projection of the first wiring layer 12 on the substrate 11 covers the orthographic projection of the semiconductor layer 14 on the substrate 11. In one specific embodiment, the orthographic projection of the first wiring layer 12 on the substrate 11 completely covers the orthographic projection of the semiconductor layer 14 on the substrate 11. Thus, the first wiring layer 12 can further serve as a light-shielding layer to shield the semiconductor layer 14 from the side (i.e., below) facing the substrate 11. Therefore, the first wiring layer 12 can be used to achieve electrical connection between the semiconductor layer 14 and the first electrode layer 15, and the first wiring layer 12 can be used to shield the semiconductor layer 14 from below. Compared to the existing scheme that uses a wiring layer on one side to connect the first electrode layer 15 and the semiconductor layer 14, and adds a light-shielding layer to shield the semiconductor layer 14, the solution provided in this application does not require an additional mask process to prepare the light-shielding layer, and does not increase the manufacturing cost of the product.

[0039] In a specific embodiment, see Figure 2 , Figure 2 This is a schematic diagram of the stacked structure of a display panel provided in another specific embodiment of this application; the display panel 10 further includes a second wiring layer 16 (M2). The second wiring layer 16 is disposed on the side surface of the first dielectric layer 13 facing away from the substrate 11. A second dielectric layer 17 is stacked on the side surface of the first dielectric layer 13 facing away from the substrate 11 and covers the second wiring layer 16. The material of the second dielectric layer 17 may be SiOx.

[0040] Specifically, the second wiring layer 16 includes multiple source electrodes and multiple drain electrodes. One drain electrode of the second wiring layer 16 is electrically connected to a drain portion of the semiconductor layer 14 and is also electrically connected to the first wiring layer 12; that is, the first wiring layer 12 is connected to the drain portion of the semiconductor layer 14 through the second wiring layer 16, thereby connecting the first electrode layer 15 through the first wiring layer 12. One source electrode of the second wiring layer 16 is electrically connected to a source portion of the semiconductor layer 14. The material of the second wiring layer 16 may be the same as or similar to the material of the first wiring layer 12.

[0041] In a specific embodiment, the orthographic projection of the second wiring layer 16 on the substrate 11 covers at least a portion of the orthographic projection of the semiconductor layer 14 on the substrate 11, so as to further enhance the light-shielding effect on the semiconductor layer 14.

[0042] In one specific embodiment, the orthographic projection of the first wiring layer 12 on the substrate 11 covers a portion of the orthographic projection of the semiconductor layer 14 on the substrate 11, and the orthographic projection of the second wiring layer 16 on the substrate 11 covers the remaining portion of the orthographic projection of the semiconductor layer 14 on the substrate 11; so that the entire semiconductor layer 14 can be shielded by the first wiring layer 12 and the second wiring layer 16; in this way, the metal traces of the display panel 10 can be reduced, wiring can be facilitated, and space can be saved.

[0043] In another specific embodiment, the orthographic projection of the first wiring layer 12 on the substrate 11 and the orthographic projection of the second wiring layer 16 on the substrate 11 may at least partially overlap; and the orthographic projection of the first wiring layer 12 on the substrate 11 and the orthographic projection of the second wiring layer 16 on the substrate 11 together completely cover the orthographic projection of the semiconductor layer 14 on the substrate 11. Compared with the previous specific embodiment, this can avoid the problem of light shining on the semiconductor layer 14 through the gap between the first wiring layer 12 and the second wiring layer 16.

[0044] In a specific embodiment, see Figure 3 , Figure 3 This is a schematic diagram of the stacked structure of a display panel 10 provided in another specific embodiment of this application; the display panel 10 also includes a third wiring layer 18 (M3) and a planarization layer 21.

[0045] The third wiring layer 18 includes multiple gates. Specifically, the third wiring layer 18 is disposed on the side of the second dielectric layer 17 facing away from the substrate 11. The semiconductor layer 14 is disposed on the side of the third wiring layer 18 facing away from the substrate 11. That is, the third wiring layer 18 is located between the semiconductor layer 14 and the second wiring layer 16 to form a bottom gate structure.

[0046] The third dielectric layer 19 is stacked on the side of the second dielectric layer 17 facing away from the first dielectric layer 13, and covers the semiconductor layer 14 and the third wiring layer 18. The material of the third dielectric layer 19 may be the same as that of the second dielectric layer 17.

[0047] A planarization layer 21 is stacked on the surface of the third dielectric layer 19 facing away from the second dielectric layer 17, and is used to planarize the surface of the third dielectric layer 19. The first electrode layer 15 is specifically disposed on the surface of the planarization layer 21 facing away from the third dielectric layer 19. It is understood that there are no other wiring layers between the first electrode layer 15 and the semiconductor layer 14 provided in this application. The display panel 10 has only three wiring layers: a first wiring layer 12, a second wiring layer 16, and a third wiring layer 18. The first electrode layer 15 is specifically electrically connected to the semiconductor layer 14 through the first wiring layer 12 disposed below the semiconductor layer 14.

[0048] For a detailed description of the specific implementation, please refer to the following documentation. Figure 3The display panel 10 also includes conductive pillars 22, which extend from the surface of the planarization layer 21 away from the substrate 11 into the first dielectric layer 13. A first end of the conductive pillar 22 contacts the first electrode layer 15 for electrical connection. A second end of the conductive pillar 22, opposite to the first end, extends to the surface of the semiconductor layer 14 for contact, thereby achieving electrical connection between the conductive pillar 22 and the semiconductor layer 14; furthermore, the first electrode layer 15 and the first wiring layer 12 are electrically connected through the conductive pillar 22.

[0049] In a specific embodiment, through-holes are formed on the planarization layer 21, the third dielectric layer 19, the second dielectric layer 17, and the first dielectric layer 13. The through-holes extend from the surface of the planarization layer 21 away from the substrate 11 along the stacking direction of the display panel 10 to the surface of the semiconductor layer 14. The through-holes are filled with conductive dielectric to form conductive pillars 22.

[0050] The second wiring layer 16 and the third wiring layer 18 are insulated from each other so that they form the two electrode plates of the capacitor. By using the third wiring layer 18 (serving as the gate) and the second wiring layer 16 (serving as the source and drain electrodes) as the two electrode plates of the capacitor, the fabrication process of the wiring layers for the capacitor can be further eliminated, thereby further reducing the manufacturing cost.

[0051] Furthermore, since the fabrication temperature below semiconductor layer 14 is relatively low, the material of the second wiring layer 16 below semiconductor layer 14 in this embodiment can be a titanium-aluminum-titanium alloy. This reduces the resistance of the capacitor, thereby improving its efficiency while reducing costs; it also provides the possibility of replacing it with a highly conductive metal. Of course, the material of the first wiring layer 12 can also be a titanium-aluminum-titanium alloy.

[0052] Of course, in other specific embodiments, see Figure 4 , Figure 4 This is a schematic diagram of the stacked structure of a display panel provided in another specific embodiment of this application; the display panel 10 may also further include a fourth wiring layer 23 (M4) and a fourth dielectric layer 24 according to actual wiring or other requirements.

[0053] The fourth trace layer 23 can form two electrode plates of the capacitor together with one of the first trace layer, the second trace layer 16, and the third trace layer 18. In this way, compared with the solution of adding two additional trace layers to serve as two electrode plates of the capacitor, one mask process can be saved.

[0054] Specifically, the fourth wiring layer 23 can be disposed on the side surface of the barrier layer 113 facing away from the flexible substrate 111, and the fourth dielectric layer 24 can be disposed on the side surface of the barrier layer 113 facing away from the flexible substrate 111 and cover the fourth wiring layer 23. The material of the fourth wiring layer 23 can also be a titanium-aluminum-titanium alloy to reduce the resistance of the capacitor and improve the working efficiency of the capacitor. In this embodiment, the first dielectric layer 13 is specifically disposed on the side surface of the fourth dielectric layer 24 facing away from the substrate 11.

[0055] Of course, the fourth routing layer 23 may also be located between the first routing layer 12 and the second routing layer 16, or between the second routing layer 16 and the third routing layer 18. This application does not limit this.

[0056] Specifically, the display panel 10 also includes other structures such as a pixel limiting layer (PLN) and support pillars (SPC). These structures can be found in the relevant structures on existing display panels 10 and can achieve the same or similar technical effects, so they will not be described in detail here.

[0057] The display panel 10 provided in this embodiment provides a first wiring layer 12 on a substrate 11, and a semiconductor layer 14 on the side of the first wiring layer 12 facing away from the substrate 11. The orthogonal projection of the first wiring layer 12 on the substrate 11 covers the orthogonal projection of the semiconductor layer 14 on the substrate 11, so that the semiconductor layer 14 is shielded from light by the first wiring layer 12 from below. At the same time, by electrically connecting the first electrode layer 15 to the first wiring layer 12, the first electrode layer 15 is electrically connected to the drain portion of the semiconductor layer 14 through the first wiring layer 12. In this way, the first wiring layer 12 can be used to realize the electrical connection between the semiconductor layer 14 and the first electrode layer 15, and the first wiring layer 12 can be used for light shielding. Compared with the existing solution that adds another light-shielding layer, there is no need to add a mask process to prepare the light-shielding layer, and the manufacturing cost of the product is not increased.

[0058] In one embodiment, see Figure 5 , Figure 5 This is a simplified structural diagram of an electronic device provided according to an embodiment of this application. This application provides an electronic device. The electronic device includes a display panel 10 as described in any of the above embodiments. The display panel 10 can be an organic light-emitting diode (OLED) display panel, an inorganic light-emitting diode (LED) display panel, or a liquid crystal display (LCD) panel.

[0059] The display panel 10 further includes light-emitting elements. Specifically, this embodiment uses an OLED display panel as an example for explanation; the OLED display panel also includes necessary components such as a second electrode layer (not shown) and an encapsulation layer (not shown). The specific structure and function of the display panel 10 can be found in the relevant description of the display panel 10 provided in the above embodiment, and will not be repeated here. The specific structure and function of the light-emitting elements can be found in the specific structure and function of existing OLEDs or LEDs, and can achieve the same or similar technical effects.

[0060] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, characterized in that, include: Substrate; The first wiring layer is disposed on the substrate. A semiconductor layer is disposed on the side of the first wiring layer away from the substrate. Furthermore, the semiconductor layer is electrically connected to the first wiring layer; A dielectric layer is disposed between the first wiring layer and the semiconductor layer; A first electrode layer is disposed on the side of the semiconductor layer away from the substrate and is electrically connected to the semiconductor layer through the first wiring layer; Wherein, the orthogonal projection of the first wiring layer on the substrate covers the orthogonal projection of the semiconductor layer on the substrate; the first wiring layer shields the semiconductor layer from light. The display panel further includes a second wiring layer stacked between the first wiring layer and the semiconductor layer; the second wiring layer includes a plurality of source electrodes and a plurality of drain electrodes, and the drain electrodes of the second wiring layer are electrically connected to the drain portions of the first wiring layer and the semiconductor layer, respectively. The first trace layer is connected to the drain portion through the second trace layer.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the second wiring layer on the substrate covers at least a portion of the orthographic projection of the semiconductor layer on the substrate.

3. The display panel according to claim 2, characterized in that, The orthogonal projection of the first wiring layer on the substrate completely covers the orthogonal projection of the semiconductor layer on the substrate.

4. The display panel according to claim 2, characterized in that, The orthogonal projection of the first electrode layer on the substrate completely covers the orthogonal projection of the semiconductor layer on the substrate.

5. The display panel according to claim 1, characterized in that, It also includes a third wiring layer, which includes a plurality of gates; the third wiring layer is disposed between the semiconductor layer and the second wiring layer.

6. The display panel according to claim 5, characterized in that, The second and third trace layers are insulated from each other so that they form the two electrode plates of a capacitor.

7. The display panel according to claim 5, characterized in that, The material of one or more of the first, second, and third wiring layers is a titanium-aluminum-titanium alloy.

8. The display panel according to claim 5, characterized in that, The dielectric layer includes: A first dielectric layer is stacked on the side surface of the substrate facing the first wiring layer and covers the first wiring layer; The second dielectric layer is stacked on the side of the first dielectric layer facing away from the substrate and covers the second wiring layer. A third dielectric layer is stacked on the side of the second dielectric layer facing away from the first dielectric layer and covers the semiconductor layer.

9. The display panel according to claim 8, characterized in that, Also includes; A planarization layer is disposed on the side of the third dielectric layer opposite to the substrate; the first electrode layer is disposed on the surface of the planarization layer opposite to the substrate. A conductive pillar extends from the planarization layer away from the substrate surface into the first dielectric layer, and the two ends of the conductive pillar contact the first electrode layer and the first wiring layer, respectively, to electrically connect the first electrode layer and the first wiring layer.

10. The display panel according to any one of claims 1-9, characterized in that, The semiconductor layer is made of indium gallium zinc oxide.

11. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1 to 10.

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