Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are disclosed. The semiconductor structure includes a substrate having a first conductivity type, and a LDMOS device on the substrate. The LDMOS device includes a first well region on the substrate, the first well region having the first conductivity type, a second well region within the first well region, and a portion of the second well region is surrounded by the first well region. The second well region has a second conductivity type, the second conductivity type is complementary to the first conductivity type. A source doped region is within the second well region, the source doped region has the first conductivity type. A deep drain doped region is within the first well region, the deep drain doped region has the first conductivity type.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to a laterally diffused metal oxide semiconductor (LDMOS) transistor device and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are a common type of power semiconductor device. Due to their horizontal structure, LDMOS devices are easy to manufacture and integrate with existing semiconductor technologies, thus reducing manufacturing costs. Simultaneously, they can withstand high breakdown voltages and exhibit high output power, making them widely used in power converters, power amplifiers, switches, rectifiers, and other components.

[0003] However, since devices such as LDMOS typically have a large area, they occupy nearly half of the entire semiconductor structure area. Therefore, improving the device structure to reduce the area of ​​LDMOS will be one of the research directions in the industry. Summary of the Invention

[0004] This invention provides a semiconductor structure comprising a substrate having a first conductivity type, a laterally diffused metal-oxide-semiconductor (LDMOS) device located on the substrate, wherein the LDMOS device includes a first well region located on the substrate, the first well region having a first conductivity type, a second well region located within the first well region, wherein a portion of the upper and lower surfaces of the second well region are surrounded by the first well region, wherein the second well region has a second conductivity type complementary to the first conductivity type, a source doped region located within the second well region having the first conductivity type, and a deep drain doped region located within the first well region, the deep drain doped region having the first conductivity type.

[0005] The present invention further provides a method for forming a semiconductor structure, comprising providing a substrate having a first conductivity type, forming a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, wherein the LDMOS device includes forming a first well region on the substrate, the first well region having a first conductivity type, forming a second well region within the first well region, wherein a portion of the upper and lower surfaces of the second well region are surrounded by the first well region, wherein the second well region has a second conductivity type complementary to the first conductivity type, forming a source doped region within the second well region, the source doped region having the first conductivity type, and forming a groove in the first well region, and forming a deep drain doped region within the first well region in the groove, the deep drain doped region having the first conductivity type.

[0006] The present invention is characterized by providing a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS). In the formation of this RESURF LDMOS, a groove is formed in a first well region, and then a highly doped polysilicon material is filled into the groove, or an ion-doped region with a U-shaped profile is formed by doping, thereby forming a deep drain doped region in the first well region. Unlike existing methods that form deep drain doped regions in the first well region through ion implantation and thermal diffusion, the area required for the deep drain doped region in this invention is significantly reduced, thus reducing the overall area of ​​the device and achieving miniaturization. Furthermore, the deep drain doped region has a high doping concentration, making it less prone to voltage drop, thereby improving product quality. Attached Figure Description

[0007] Figures 1 to 7 This is a schematic diagram illustrating the process of forming a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) according to the present invention.

[0008] Figure 8 This is a schematic diagram of a RESURF LDMOS structure in which a deep drain doped region is formed through ion implantation and heating steps;

[0009] Figure 9 This is a schematic diagram of a P-type RESURF LDMOS.

[0010] Figures 10-11These are schematic diagrams of the RESURF LDMOS according to two other embodiments of the present invention;

[0011] Figures 12-14 This is a schematic diagram of the structure of RESURF LDMOS according to another embodiment of the present invention.

[0012] Symbol Explanation

[0013] 1: Laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) structure for reducing surface field

[0014] 10: Base

[0015] 12: First Trap Zone

[0016] 14: Barrier Layer

[0017] 16: Drift Zone

[0018] 20: Second Trap Zone

[0019] 22: Insulation layer

[0020] 24: Groove

[0021] 25: Photoresist layer

[0022] 26: Polycrystalline silicon layer

[0023] 27: Deep drain doped region

[0024] 27A: Deep drain doped region

[0025] 28: Gate Structure

[0026] 29: Gate dielectric layer

[0027] 30: Gate conductive layer

[0028] 32: Source doped region

[0029] 34: Shallow drain doped region

[0030] 34A: Ion-doped region

[0031] 36:Matrix area

[0032] 40: Metal silicide layer

[0033] 42: Dielectric layer

[0034] 44: Contact Structure

[0035] 44A: Contact Structure

[0036] 45: Padding layer

[0037] 46: Conductive layer

[0038] 50: Insulation layer

[0039] 60: Insulation layer

[0040] A: Area

[0041] B: Area

[0042] C: Area

[0043] G: Spacing

[0044] P1: Doping Steps Detailed Implementation

[0045] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0046] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0047] Please refer to Figures 1 to 7 , Figures 1 to 7 This diagram illustrates the process of forming a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) according to the present invention. Figure 1 As shown, a substrate 10 is provided, within which a first well region 12 and a second well region 20 are formed, for example, by doping. Notably, the substrate 10 is, for example, a silicon substrate (single-crystal silicon). The first well region 12 is located on the substrate 10 and includes a first conductivity type (e.g., N-type). The first well region 12 may include a barrier layer 14 and a drift region 16, which are interconnected and have the same conductivity type (e.g., N-type). The second well region 20 includes a second conductivity type (e.g., P-type) complementary to the first conductivity type. In this embodiment, the substrate 10 is, for example, a P-type substrate.

[0048] It is worth noting that, such as Figure 1As shown, a portion of the second well region 20 extends laterally into the first well region 12, and the upper and lower surfaces of a portion of the second well region 20 are surrounded by the first well region 12, forming an interlaced structure of the first well region 12 and the second well region 20. In other words, a portion of the extension of the second well region 20 is located between the barrier layer 14 and the drift region 16 of the first well region 12. In the actual fabrication process, the barrier layer 14 can be formed on the substrate 10 first, followed by the formation of the second well region 20, and then ions can be doped into a portion of the second well region 20 to form the drift region 16.

[0049] In subsequent steps, when this well region distribution structure is fabricated into an LDMOS device, it facilitates the formation of a depletion region at the NP interface to block current flow, allowing the LDMOS to withstand a larger voltage difference in the off state. This structure requires less area than a typical LDMOS; therefore, the aforementioned LDMOS can also be simply referred to as a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (RESURFLDMOS). Further details regarding RESURF LDMOS have been disclosed in some prior art (e.g., US Patent No. 9484454), and will not be elaborated upon here.

[0050] This invention improves upon the RESURF LDMOS architecture to reduce device area and increase device quality. For example... Figure 1 As shown, a patterned insulating layer 22 is formed on the surfaces of the first well region 12 and the second well region 20. The insulating layer 22 is, for example, silicon oxide or silicon nitride, but is not limited thereto. Then, using the insulating layer 22 as a mask, a groove 24 is formed in the first well region 12. The groove 24 can be formed, for example, by patterning and etching, but is not limited thereto. In this embodiment, the width of the groove 24 is preferably less than 0.5 micrometers, and the depth is greater than 8 micrometers, but is not limited thereto. In this embodiment, the width of the groove 24 is approximately 0.3 micrometers, and the depth is preferably greater than the interface between the barrier layer 14 and the second well region 20.

[0051] Then as Figure 3 As shown, a polysilicon layer 26 is formed to fill the groove 24. The polysilicon layer 26 is, for example, a polysilicon layer with a high doping concentration, which can be formed by an in-situ doping process and has a first conductivity type (e.g., N-type). In this embodiment, the concentration of the polysilicon layer 26 is preferably greater than 1E18 cm⁻¹. 3 The concentration mentioned above is higher than that of the doped region formed by existing steps such as ion implantation and heating.

[0052] Then as Figure 4As shown, excess polysilicon layer 26 and insulating layer 22 are removed by means of etch-back or chemical mechanical polishing to expose the surfaces of the first well region 12 and the second well region 20. The polysilicon layer 26 remaining in the groove 24 can also be defined as the deep drain doped region 27, the function of which will be further described in the following paragraphs.

[0053] like Figure 5 As shown, a gate structure 28 is formed on the first well region 12 and the second well region 20. The gate structure 28 includes a gate dielectric layer 29 and a gate conductive layer 30. The gate dielectric layer 29 is thicker above the drift region 16 and thinner near the interface between the surfaces of the first well region 12 and the second well region 20. The gate structure 28 described above is prior art for RESURF LDMOS, and other features will not be elaborated further.

[0054] Continue to refer to Figure 6 After the gate structure 28 is completed, at least a source doped region 32 and a shallow drain doped region 34 are formed in the first well region 12 and the second well region 14 respectively through ion doping and heating steps. Both the source doped region 32 and the shallow drain doped region 34 contain a first conductivity type (e.g., N-type), and the shallow drain doped region 34 is connected to the deep drain doped region 27. It is worth noting that since the source doped region 32 and the shallow drain doped region 34 are formed in a well region composed of monocrystalline silicon through ion doping and heating steps, their material is also monocrystalline silicon, but different from that of the deep drain doped region 27. Furthermore, in this embodiment, the ion doping concentration of the source doped region 32 and the shallow drain doped region 34 is, for example, greater than 1E20 cm⁻¹. 3 In addition, in some embodiments, a body region 36 may be formed next to the source doped region 32, wherein the body region 36 is, for example, a doped region containing a second conductivity type (e.g., P-type).

[0055] like Figure 7As shown, a metal silicide layer 40 can be selectively formed on the surfaces of the gate structure 28, the first well region 12, and the second well region 20. Next, a dielectric layer 42 is formed to cover the device, and a contact structure 44 is formed in the dielectric layer 42, connecting the source doped region 32 and the shallow drain doped region 34. In some embodiments, the metal silicide layer 40 may be omitted, or it may be formed under the contact structure 44 after the dielectric layer 42 is completed. The dielectric layer 42 is, for example, silicon oxide or silicon nitride, and the contact structure 44 may include a pad layer 45, made of, for example, titanium / titanium nitride, and a conductive layer 46, made of, for example, tungsten (W). Other details and fabrication methods of the above-described device are prior art and will not be elaborated here. This completes the RESURF LDMOS structure 1 described in this invention. Since the first well region 12 of the RESURF LDMOS structure 1 in this embodiment is N-type, the RESURF LDMOS structure 1 in this embodiment can also be defined as an N-type RESURF LDMOS structure.

[0056] In the RESURF LDMOS structure 1 of this invention, when the gate structure 28 is off, a potential difference still exists between the source and drain terminals. For example, a high voltage (e.g., 100V) is applied to the contact structure 44 above the drain terminal, while the source terminal maintains a 0 potential. At this time, due to the high doping concentration and good conductivity of the deep drain doped region 27, the voltage conducted downwards only decreases slightly. This voltage causes the first well region 12 to maintain a high potential, while the second well region 20 maintains a low potential, resulting in a depletion region at the NP interface located in the central part of the RESURF LDMOS structure 1. For example... Figure 7 Regions A, B, and C in the diagram are all regions where depletion regions can be generated. In other words, when the gate structure 28 of the RESURF LDMOS structure 1 is turned off, in addition to the isolation caused by the channel region being turned off, the depletion region generated in the center can further isolate the current, allowing the RESURF LDMOS structure 1 to withstand high-voltage operating modes.

[0057] In order for the depletion region to be formed smoothly, it is preferable in the prior art to make the depth of the deep drain doped region deeper so that the voltage can be smoothly conducted to the part near the barrier layer 14 below, and the depletion region can be successfully generated. Figure 8 A schematic diagram of a RESURF LDMOS structure is shown, illustrating the formation of a deep drain-doped region through ion implantation and heating. In existing technologies, ion implantation and heating are used to increase the depth of the deep drain-doped region; however, ions also diffuse laterally during heating, resulting in a relatively large width of the deep drain-doped region in existing technologies (e.g., ...). Figure 8The ion-doped region 34A in the prior art results in an excessively large device area, hindering miniaturization. For example, to achieve a depth of 8 micrometers in the ion-doped region 34A, its width would need to expand to approximately 12 micrometers. Furthermore, the doping concentration of the ion-doped region 34A is lower than that of the deep drain doped region 27 of this invention, resulting in lower conductivity. When a high voltage (e.g., 100V) is applied from above the ion-doped region 34A, the voltage conducted to the area below the ion-doped region 34A will drop significantly, which is detrimental to the formation of a depletion region.

[0058] The main difference between the RESURF LDMOS structure 1 of the present invention and the RESURF LDMOS structure in the prior art lies in the formation of a deep drain doped region 27 replacing part of the ion-doped region. This deep drain doped region 27 is formed by etching a groove 24 and backfilling with a polysilicon layer 26. The width of the groove 24 can be much smaller than the width of the ion-doped region 34A in the prior art. Another feature is the filling of the groove 24 with a higher doping concentration and better conductivity of the polysilicon layer 26. This not only significantly reduces the device area (because the width of the deep drain doped region 27 is smaller), but also improves the conductivity of the deep drain doped region 27, allowing the high voltage from the upper contact structure 44 to be smoothly conducted to the area below the deep drain doped region 27, and further conducted to the first well region 12, enabling the successful formation of the depletion region. In summary, the present invention has advantages such as reducing device area, improving device quality, and compatibility with existing manufacturing processes.

[0059] In the above embodiments ( Figures 1 to 7 Taking the fabrication of an N-type RESURF LDMOS structure as an example, the first well region 12 and the deep drain doped region 27 are N-type, and the second well region 20 is P-type. However, in other embodiments of the present invention, a P-type RESURF LDMOS structure can also be fabricated. Figure 9 As shown, Figure 9 A schematic diagram of a P-type RESURF LDMOS is shown. The structure, materials, and fabrication methods of most components are the same as in the first preferred embodiment described above, and will not be repeated here. The difference lies in that, in this embodiment, the substrate 10, the first well region 12, the deep drain doped region 27, the source doped region 32, and the shallow drain doped region 34 are P-type, while the second well region 20 and the substrate region 36 are N-type. It is worth noting that in this embodiment, the deep drain doped region 27 does not contact the second well region 20, and a distance G is maintained between the deep drain doped region 27 and the second well region 20 to prevent current punch-through between the higher doped deep drain doped region 27 and the lower doped second well region 20 when a high potential is applied to the drain terminal, thus avoiding device breakdown.

[0060] Similarly, in other embodiments of the present invention, to avoid lateral current breakdown, an insulating layer may be provided next to or below the deep drain doped region 27. Please refer to Figures 10-11 , Figures 10-11 Schematic diagrams of the structures of RESURF LDMOS according to two other embodiments of the present invention are shown respectively. Figure 10 As shown, in this embodiment, an additional insulating layer 50 is formed next to the deep drain-doped region 27. The insulating layer 50 is, for example, silicon oxide or a polysilicon layer surrounded by silicon oxide. The depth of the insulating layer 50 can be deeper than the depth of the deep drain-doped region 27, and the insulating layer 50 is disposed within the substrate 10 next to the first well region 12. In some embodiments, deep trench isolation (DTI) can be used as the insulating layer 50 here. The insulating layer 50 has the function of preventing the deep drain-doped region 27 from breaking down the first well region 12 and affecting other adjacent components.

[0061] In another embodiment, such as Figure 11 As shown, in addition to the aforementioned insulating layer 50, in this embodiment, a portion of the barrier layer 14 is replaced by another insulating layer 60. The insulating layer 60 is, for example, silicon oxide. In some embodiments, a silicon on substrate (SOI) substrate can be used to replace the original silicon substrate to achieve the following: Figure 11 The structure is shown. In this embodiment, the insulating layer 60 also prevents current breakdown in the longitudinal direction.

[0062] In other embodiments of the invention, different LDMOS can also be formed on the same substrate. For example, an N-type RESURF LDMOS ( Figure 7 The structure shown) and P-type RESURF LDMOS ( Figure 9 The structures shown are formed together in different regions of the same substrate. This structure also falls within the scope of this invention.

[0063] In the above embodiments, a highly doped polysilicon layer 26 is filled into the groove 24 to form a narrow polysilicon deep drain doped region 27. In other embodiments of the invention, a narrow and sufficiently deep deep drain doped region can also be formed within the first well region 12 by doping or plasma implantation within the groove 24, as detailed below. Figures 12 to 14 As shown.

[0064] like Figure 12 As shown, in this embodiment, after the groove 24 is formed (continuing from the first embodiment) Figure 1 and Figure 1The process involves first forming a photoresist layer 25 covering the first well region 12 and the second well region 20, and simultaneously exposing portions of the first well region 12 and the second well region 20. The exposed areas include the groove 24 and the location in the second well region 20 where the source doped region 32 is to be formed. Next, a doping step P1 is performed to dope the areas not covered by the photoresist layer 25. In this embodiment, high-concentration N-type ions are used as an example, but in other embodiments of the present invention, high-concentration P-type ions may also be used, and the present invention is not limited thereto. Furthermore, the groove 24, the source doped region 32, and the gate structure 28 can also be individually and independently doped using different photomasks, and the present invention is not limited thereto.

[0065] It is worth noting that the doping angle can be adjusted during the ion doping step P1 in this embodiment, for example, doping can be performed at an angle. Therefore, the doped ions can penetrate deep into the bottom surface and sidewalls of the groove 24, forming a deep drain doped region 27A on the bottom surface and sidewalls of the groove 24. Unlike the deep drain doped region 27 mentioned in the previous embodiment, the deep drain doped region 27A in this embodiment is formed around the groove 24 of the first well region 12 by ion doping, and therefore has a U-shaped cross-sectional profile. The material of the deep drain doped region 27A is the same as that of the first well region 12, both being single-crystal silicon. In addition, in this embodiment, the source doped region 32 can also be formed in the second well region 20 at the same time as the deep drain doped region 27A is formed, thus achieving the effect of saving steps. Furthermore, the groove 24 can also be doped using plasma doping, and this invention is not limited thereto.

[0066] Next, as Figure 13 As shown, the photoresist layer 25 is removed, and then a substrate region 36 is formed next to the source doped region 32. This substrate region 36 is, for example, a P-type doped region formed by doping. Then, a metal silicide layer 40 is formed, covering the surfaces of the gate structure 28, the first well region 12, the second well region 20, and the recess 24 (i.e., the deep drain doped region 27A). Alternatively, the invention may omit the formation of a metal silicide layer, or selectively form a metal silicide layer on the substrate, the gate structure, or the inner surface of the recess; the invention is not limited thereto.

[0067] Then as Figure 14As shown, a dielectric layer 42, contact structures 44 and 44A are formed. The dielectric layer 42 is, for example, silicon oxide or silicon nitride, while contact structures 44 and 44A may include a pad layer 45, made of, for example, titanium / titanium nitride, and a conductive layer 46, made of, for example, tungsten (W). The steps for forming the substrate region 36, the metal silicide layer 40, and the contact structures 44 and 44A are similar to those in the above embodiment (see reference). Figure 6 and Figure 7 The description is similar to that of the previous one, so it will not be repeated here. It is worth noting that the contact structure 44A in this embodiment is formed in the groove 24, that is, on the deep drain doped region 27A. The contact structure 44A extends into the first well region 12, that is, the bottom surface of the contact structure 44A is lower than the top surface of the first well region 12, so it can effectively conduct current from other components above to the bottom.

[0068] In summary Figures 12 to 14 This embodiment forms the deep drain doped region 27A in another way, which is formed in the groove by doping or ion implantation. The depth of the deep drain doped region is sufficient to conduct current from above to below. In another embodiment, the width of the deep drain doped region is also less than 0.5 micrometers, similarly saving space. Furthermore, this embodiment is compatible with existing fabrication processes. In addition, this embodiment uses the fabrication of an N-type RESURF LDMOS structure as an example, but the type of dopant ions can be adjusted to fabricate a P-type RESURF LDMOS structure. That is, the method of doping ions in the groove in this embodiment can be applied to... Figure 9 The embodiments described herein are also within the scope of this invention.

[0069] Based on the above description and figures, the present invention provides a semiconductor structure comprising a substrate 10, a laterally diffused metal-oxide-semiconductor (LDMOS) element located on the substrate 10, wherein the LDMOS element comprises: a first well region 12 located on the substrate 10, the first well region 12 having a first conductivity type; a second well region 20 located within the first well region 12, wherein a portion of the upper and lower surfaces of the second well region 20 are surrounded by the first well region 12, wherein the second well region 20 has a second conductivity type complementary to the first conductivity type; a source doped region 32 located within the second well region 20, the source doped region 32 having the first conductivity type; and a deep drain doped region (27 or 27A) located within the first well region 12, the deep drain doped region (27 or 27A) having the first conductivity type. In another embodiment, the width of its deep drain doped region (27 or 27A) is less than 0.5 micrometers.

[0070] The present invention also provides a method for forming a semiconductor structure, comprising providing a substrate 10, forming a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, wherein the step of forming the LDMOS device includes: forming a first well region 12 on the substrate 10, the first well region 12 having a first conductivity type; forming a second well region 20 within the first well region 12, wherein a portion of the upper and lower surfaces of the second well region 20 are surrounded by the first well region 12, wherein the second well region 20 has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type; forming a source doped region 32 within the second well region 20, the source doped region 32 having a first conductivity type; and forming a groove 24 in the first well region 12, and forming a deep drain doped region (27 or 27A) within the groove 24 within the first well region 12, the deep drain doped region (27 or 27A) having a first conductivity type. In another embodiment, the width of its deep drain doped region (27 or 27A) is less than 0.5 micrometers.

[0071] In some embodiments, the first well region 12 and the second well region 20 are both made of monocrystalline silicon, while the deep drain doped region 27 is made of polycrystalline silicon, and the deep drain doped region 27 has a columnar shape.

[0072] In some embodiments, the first well region 12, the second well region 20 and the deep drain doped region 27A are all made of monocrystalline silicon, and the deep drain doped region 27A has a U-shaped profile.

[0073] In some embodiments, a contact structure 44A is further included, located on the first well region 12 and electrically connected to the deep drain doped region 27A, wherein a bottom surface of the contact structure 44A is lower than a top surface of the first well region 12.

[0074] In some embodiments, the doping concentration of the deep drain doped region 27 is higher than 1E18cm. 3 .

[0075] In some embodiments, a shallow drain doped region 34 is further included, located within the first well region 12, and connected to the deep drain doped region 27.

[0076] In some embodiments, the first well region 12 includes a barrier layer 14 and a drift region 16 connected to each other, and a portion of the second well region 20 is located between the barrier layer 14 and the drift region 16.

[0077] In some embodiments, at least one insulating structure 50 is also included, located next to the deep drain doped region 27.

[0078] In some embodiments, the first conductivity type includes N-type and the second conductivity type includes P-type.

[0079] In some embodiments, the first conductivity type includes P-type and the second conductivity type includes N-type.

[0080] The present invention is characterized by providing a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS). In the formation of this RESURF LDMOS, a groove is formed in a first well region, and then a highly doped polysilicon material is filled into the groove, or an ion-doped region with a U-shaped profile is formed by doping, thereby forming a deep drain doped region in the first well region. Unlike existing methods that form deep drain doped regions in the first well region through ion implantation and thermal diffusion, the area required for the deep drain doped region in this invention is significantly reduced, thus reducing the overall device area and achieving miniaturization. Furthermore, the deep drain doped region has a high doping concentration, making it less prone to voltage drop, thereby improving product quality.

[0081] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising: Base; A laterally diffused metal-oxide-semiconductor (LDMOS) device is located on the substrate, wherein the laterally diffused metal-oxide-semiconductor device comprises: A first well region is located on the substrate, and the first well region has a first conductivity type; A second well region is located within the first well region, and a portion of the upper and lower surfaces of the second well region are surrounded by the first well region. The second well region has a second conductivity type, which is complementary to the first conductivity type. The source doped region is located within the second well region, and the source doped region has the first conductivity type. as well as A deep drain doped region is located within the first well region, the deep drain doped region having the first conductivity type, wherein the portion of the substrate located below the first well region is spaced apart from the deep drain doped region.

2. The semiconductor structure as claimed in claim 1, wherein the first well region and the second well region are both made of monocrystalline silicon, the deep drain doped region is made of polycrystalline silicon, and the deep drain doped region has a columnar shape.

3. The semiconductor structure as claimed in claim 1, wherein the first well region, the second well region, and the deep drain doped region are all made of single-crystal silicon, and the deep drain doped region has a U-shaped cross-sectional profile.

4. The semiconductor structure of claim 3 further includes a contact structure located on the first well region and electrically connected to the deep drain doped region, wherein the bottom surface of the contact structure is lower than the top surface of the first well region.

5. The semiconductor structure of claim 1, wherein the doping concentration of the deep drain doped region is higher than 1E18cm. 3 .

6. The semiconductor structure of claim 1 further includes a shallow drain doped region located within the first well region and connected to the deep drain doped region.

7. The semiconductor structure of claim 1, wherein the first well region includes a barrier layer and a drift region interconnected, and a portion of the second well region is located between the barrier layer and the drift region.

8. The semiconductor structure of claim 1 further includes at least one insulating structure located adjacent to the deep drain doped region.

9. The semiconductor structure of claim 1, wherein the first conductivity type comprises N-type and the second conductivity type comprises P-type, or the first conductivity type comprises P-type and the second conductivity type comprises N-type.

10. The semiconductor structure of claim 1, wherein the width of the deep drain doped region is less than 0.5 micrometers.

11. A method for forming a semiconductor structure, comprising: Provide a base; A laterally diffused metal-oxide-semiconductor (LDMOS) device is formed on the substrate, wherein the step of forming the laterally diffused metal-oxide-semiconductor device includes: A first well region is formed on the substrate, and the first well region has a first conductivity type; A second well region is formed within the first well region, and a portion of the upper and lower surfaces of the second well region are surrounded by the first well region, wherein the second well region has a second conductivity type, and the second conductivity type is complementary to the first conductivity type; A source doped region is formed within the second well region, and the source doped region has the first conductivity type. A groove is formed in the first well region; and A deep drain doped region is formed in the groove within the first well region. The deep drain doped region has the first conductivity type, wherein the portion of the substrate located below the first well region is spaced apart from the deep drain doped region.

12. The method of forming as claimed in claim 11, wherein the deep drain doped region is formed by filling the groove with a doped polycrystalline silicon layer, wherein the first well region and the second well region are both made of monocrystalline silicon, and the deep drain doped region is made of polycrystalline silicon, and the shape of the deep drain doped region is columnar.

13. The method of forming as claimed in claim 11, wherein the deep drain doped region is formed by a doping step within the groove, wherein the first well region, the second well region, and the deep drain doped region are all made of monocrystalline silicon, and the deep drain doped region has a U-shaped profile.

14. The forming method of claim 13, further comprising forming a contact structure located on the first well region and electrically connected to the deep drain doped region, wherein the bottom surface of the contact structure is lower than the top surface of the first well region.

15. The formation method of claim 11, wherein the doping concentration of the deep drain doped region is higher than 1E18cm. 3 .

16. The method of forming as claimed in claim 11, further comprising forming a shallow drain doped region located within the first well region and connected to the deep drain doped region.

17. The forming method of claim 11, wherein the first well region comprises a barrier layer and a drift region interconnected, and a portion of the second well region is located between the barrier layer and the drift region.

18. The method of forming as claimed in claim 11, further comprising forming at least one insulating structure located adjacent to the deep drain doped region.

19. The forming method of claim 11, wherein the first conductivity type comprises N-type and the second conductivity type comprises P-type, or the first conductivity type comprises P-type and the second conductivity type comprises N-type.

20. The formation method of claim 11, wherein the width of the deep drain doped region is less than 0.5 micrometers.

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