Method for manufacturing silicon-germanium heterojunction transistor

Abstract

The present invention provides a method for manufacturing a germanium-silicon heterojunction transistor. The method comprises providing a substrate on which an STI is formed to define an active area, forming a first dielectric layer on the substrate, forming a first polysilicon layer on the first dielectric layer, and forming a second dielectric layer on the polysilicon layer. The method then removes portions of the second dielectric layer and the first polysilicon layer through photolithography and etching to form a first stack located above the active area, forming a third dielectric layer covering the first stack and the first dielectric layer, and then etching the third dielectric layer to form sidewalls on the sidewalls of the first stack. A second polysilicon layer covering the first stack and the sidewalls, and a fourth dielectric layer covering the second polysilicon layer are formed on the first dielectric layer, and the fourth dielectric layer is etched until the sidewalls are exposed. The method for manufacturing a germanium-silicon heterojunction transistor reduces the etching process requirements for forming silicon nitride suspended sidewalls, resulting in a simple process and low production cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a germanium-silicon heterojunction transistor. Background Art

[0002] Silicon-germanium heterojunction transistor (SiGe HBT) technology has been widely used in cellular phones / personal communication systems, cordless phones, global positioning system receivers, wireless local area networks, and industrial and medical applications.

[0003] Although the device performance of SiGe heterojunction transistors is excellent, their complex process and high production costs have always restricted the development of such products. Therefore, the optimization of device structure and the simplification of process steps are the main research directions of researchers. The difficulty of selective epitaxy of SiGe layer seriously restricts the development of SiGe heterojunction transistors. Therefore, in order to obtain high-performance SiGe heterojunction transistor devices, on the one hand, it is necessary to improve the level of selective epitaxy technology of SiGe layer; on the other hand, the level of SiGe epitaxial layer technology can be reduced by improving the structure and manufacturing method of SiGe heterojunction transistor devices.

[0004] A local characteristic structure of a germanium-silicon heterojunction transistor is as follows Figure 1 As shown, silicon nitride has a suspended sidewall structure, which undergoes fewer thermal processes and has better performance.

[0005] The prior art methods for forming characteristic structures include:

[0006] S1: Provide a substrate 01, on which an STI is formed to define an active area, form a first oxide layer 011 on the substrate 01, form a polysilicon layer 012 on the first oxide layer 011, and form a second oxide layer 013, a first nitride layer 014, and a third oxide layer 015 stacked from bottom to top on the polysilicon layer 012, i.e., an ONO layer, and then photolithography and etching the ONO layer to expose the polysilicon layer 012 thereunder, forming a structure as shown in FIG. Figure 2 The structure shown;

[0007] S2: Etch the exposed polysilicon layer 012 so that the first oxide layer 011 underneath is exposed, forming Figure 3 The structure shown;

[0008] S3: Etch the exposed first oxide layer 011 to form an inverted T-shaped groove, form an epitaxial layer 016 at the bottom of the groove, and then form a second nitride layer covering the epitaxial layer 016 on the substrate 01. Then, the following steps can be formed by etching: Figure 1 However, the formation of SiN hanging sidewalls requires high etching process technology, and the etching profile must be close to 90 degrees, otherwise the SiN in S3 is easily over-etched and cannot be formed. Figure 1 The suspended side wall structure is shown.

[0009] In order to solve the above problems, it is necessary to propose a new method for manufacturing a germanium-silicon heterojunction transistor. Summary of the Invention

[0010] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for manufacturing a germanium-silicon heterojunction transistor, which is used to solve the problem in the prior art that the formation of SiN suspended sidewalls has high requirements on etching process technology and its etching profile must be close to 90 degrees, otherwise SiN is easily over-etched.

[0011] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a germanium-silicon heterojunction transistor, comprising:

[0012] Step 1: providing a substrate, on which an STI is formed to define an active area, forming a first dielectric layer on the substrate, forming a first polysilicon layer on the first dielectric layer, and forming a second dielectric layer on the polysilicon layer. Then, removing portions of the second dielectric layer and the first polysilicon layer by photolithography and etching to form a first stack located on the active area, forming a third dielectric layer covering the first stack and the first dielectric layer, and then etching the third dielectric layer to form sidewalls on the sidewalls of the first stack.

[0013] Step 2: forming a second polysilicon layer covering the first stack and the sidewalls and a fourth dielectric layer covering the second polysilicon layer on the first dielectric layer; removing a portion of the fourth dielectric layer by photolithography and etching until the sidewalls are exposed;

[0014] Step 3: etching and removing the second dielectric layer and the sidewall spacer to form a first pattern structure;

[0015] Step 4: forming a fifth dielectric layer on the first pattern structure, and then etching the fifth dielectric layer to above the first polysilicon layer;

[0016] Step 5: etching and removing the first polysilicon layer to expose the first dielectric layer thereunder, and then etching the exposed first dielectric layer to form an inverted T-shaped groove;

[0017] Step 6: forming an epitaxial layer at the bottom of the groove, and then forming a third polysilicon layer on the epitaxial layer to fill the remaining groove, so as to form a second pattern structure;

[0018] Step seven: etching the second graphic structure to form a desired device structure.

[0019] Preferably, the substrate in step 1 is a silicon substrate.

[0020] Preferably, the material of the first dielectric layer in step 1 is silicon dioxide.

[0021] Preferably, the material of the second dielectric layer in step 1 is silicon nitride.

[0022] Preferably, the material of the third dielectric layer in step 1 is silicon nitride.

[0023] Preferably, the material of the fourth dielectric layer in step 2 is silicon dioxide.

[0024] Preferably, in step 2, the fourth dielectric layer is etched by wet etching until the sidewalls are exposed.

[0025] Preferably, the material of the fifth dielectric layer in step 4 is silicon nitride.

[0026] Preferably, in step five, the first polysilicon layer is removed by dry etching.

[0027] Preferably, in step five, the exposed first dielectric layer is etched by wet etching to form the inverted T-shaped groove.

[0028] Preferably, the epitaxial layer in step six is a silicon-germanium epitaxial layer.

[0029] Preferably, the method of etching the second graphic structure to form the required device structure in step seven includes: forming a first photoresist layer on the third polysilicon layer, photolithographically opening the first photoresist layer to expose the third polysilicon layer thereunder, and etching the exposed third polysilicon layer and the fifth dielectric layer, the fourth dielectric layer, and the second polysilicon layer thereunder to above the first dielectric layer; removing the remaining first photoresist layer, forming a second photoresist layer on the etched third polysilicon layer, photolithographically opening the second photoresist layer to expose the third polysilicon layer thereunder, and etching the exposed third polysilicon layer and the fifth dielectric layer and the fourth dielectric layer thereunder to above the second polysilicon layer.

[0030] As described above, the method for manufacturing a silicon-germanium heterojunction transistor of the present invention has the following beneficial effects:

[0031] The manufacturing method of the germanium-silicon heterojunction transistor of the present invention reduces the requirements on the etching process when forming the silicon nitride suspension sidewall, and the process is simple and the production cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shown is a schematic diagram of a local characteristic structure of the prior art;

[0033] Figure 2 Shown is a schematic diagram of etching an ONO layer in the prior art;

[0034] Figure 3 Shown is a schematic diagram of etching a polysilicon layer in the prior art;

[0035] Figure 4 Shown is a schematic diagram of a characteristic structure formed by etching according to the present invention;

[0036] Figure 5 Shown is a schematic diagram of the process flow of the present invention;

[0037] Figure 6 Shown is a schematic diagram of forming a first stack of layers according to the present invention;

[0038] Figure 7 Shown is a schematic diagram of forming a sidewall according to the present invention;

[0039] Figure 8 Schematic diagram showing the deposition of a second polysilicon layer and a fourth dielectric layer covering the second polysilicon layer according to the present invention;

[0040] Figure 9 Schematic diagram showing the etching removal of the second dielectric layer and the sidewall spacer according to the present invention;

[0041] Figure 10 It is a schematic diagram showing the formation of a fifth dielectric layer on the first pattern structure of the present invention;

[0042] Figure 11 Shown is a schematic diagram of etching the fifth dielectric layer to the top of the first polysilicon layer according to the present invention;

[0043] Figure 12 Shown is a schematic diagram of an inverted T-shaped groove according to the present invention;

[0044] Figure 13 It is a schematic diagram showing the formation of an epitaxial layer at the bottom of the groove according to the present invention;

[0045] Figure 14 Schematic diagram showing a third polysilicon layer formed on the epitaxial layer to fill the remaining groove according to the present invention;

[0046] Figure 15 Shown is a schematic diagram of the target device structure of the present invention. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] See also Figure 5 The present invention provides a method for manufacturing a germanium-silicon heterojunction transistor, comprising:

[0049] Step 1: Provide a substrate 01. STI is formed on the substrate 01 to define an active area. A first dielectric layer 02 is formed on the substrate 01. A first polysilicon layer 03 is formed on the first dielectric layer 02. The polysilicon layer is usually formed by low-pressure chemical vapor deposition. A second dielectric layer 04 is formed on the first polysilicon layer 03. Then, a portion of the second dielectric layer 04 and the first polysilicon layer 03 are removed by photolithography and etching. Specifically, a photoresist layer is formed on the second dielectric layer 04. The photolithography opens a portion of the photoresist so that the second dielectric layer 04 thereunder is exposed to define an etched area. Then, the exposed second dielectric layer 04 and the first polysilicon layer 03 thereunder are etched to form a first stack located on the active area, forming a structure as shown in FIG. Figure 6 The structure shown in FIG. 1 is formed by forming a third dielectric layer 05 covering the first stack and the first dielectric layer 02, and then etching the third dielectric layer 05 to form a sidewall on the sidewall of the first stack, forming a sidewall as shown in FIG. Figure 7 The structure shown;

[0050] In an embodiment of the present invention, the substrate 01 in step 1 is a silicon substrate 01 .

[0051] In an embodiment of the present invention, the material of the first dielectric layer 02 in step 1 is silicon dioxide, which can be generally formed by oxidizing the silicon substrate 01 in a high-temperature furnace tube.

[0052] In an embodiment of the present invention, the material of the second dielectric layer 04 in step 1 is silicon nitride, which can generally be formed by a chemical vapor deposition method.

[0053] In an embodiment of the present invention, the material of the third dielectric layer 05 in step 1 is silicon nitride, which can usually be formed by a chemical vapor deposition method.

[0054] Step 2: Form a second polysilicon layer 06 covering the first stack and the sidewalls and a fourth dielectric layer 07 covering the second polysilicon layer 06 on the first dielectric layer 02. Remove part of the fourth dielectric layer 07 until the sidewalls are exposed by photolithography and etching. Specifically, form a photoresist layer on the fourth dielectric layer 07, open the photoresist layer at the active area by photolithography to expose the fourth dielectric layer 07 below it, and then etch the exposed fourth dielectric layer 07 by dry etching until the sidewalls are exposed, forming a structure as shown in FIG. Figure 8 The structure shown;

[0055] In an embodiment of the present invention, the material of the fourth dielectric layer 07 in step 2 is silicon dioxide, which can usually be formed by a chemical vapor deposition method.

[0056] In an embodiment of the present invention, in step 2, the fourth dielectric layer 07 is etched by wet etching until the sidewalls are exposed.

[0057] Step 3: Wet etching is used to remove the second dielectric layer 04 and the sidewalls to form a first pattern structure. Figure 9 The structure shown;

[0058] Step 4: forming a fifth dielectric layer 08 on the first pattern structure to form a Figure 10 The structure shown in FIG. 1 is then formed by photolithography to define the etching area of the fifth dielectric layer 08, and the fifth dielectric layer 08 is etched to the top of the first polysilicon layer 03 by dry etching to form the structure shown in FIG. Figure 11 The structure shown;

[0059] In an embodiment of the present invention, the material of the fifth dielectric layer 08 in step 4 is silicon nitride, which can usually be formed into a thin silicon nitride layer by a high-temperature furnace low-pressure chemical vapor deposition method.

[0060] Step 5: The first polysilicon layer 03 is removed by dry etching to expose the first dielectric layer 02 below it. The upper surface of the fifth dielectric layer 08 is also formed into a flat morphology. Then, the exposed first dielectric layer 02 is etched to form an inverted T-shaped groove, forming a Figure 12 The structure shown;

[0061] In an embodiment of the present invention, in step five, the exposed first dielectric layer 02 is etched by wet etching to form an inverted T-shaped groove.

[0062] Step 6: forming an epitaxial layer 09 at the bottom of the groove, forming Figure 13 The structure shown in FIG. 1 is then formed on the epitaxial layer 09 to fill the remaining grooves, thereby forming a second pattern structure. Figure 14 The structure shown;

[0063] Step seven: etching the second pattern structure to form a desired device structure.

[0064] In an embodiment of the present invention, the method of etching the second graphic structure in step seven to form the desired device structure includes: forming a first photoresist layer on the third polysilicon layer 10, photolithographically opening the first photoresist layer to expose the third polysilicon layer 10 thereunder, and etching the exposed third polysilicon layer 10 and the fifth dielectric layer 08, the fourth dielectric layer 07, and the second polysilicon layer 06 thereunder to above the first dielectric layer 02; removing the remaining first photoresist layer, forming a second photoresist layer on the etched third polysilicon layer 10, photolithographically opening the second photoresist layer to expose the third polysilicon layer 10 thereunder, and etching the exposed third polysilicon layer 10 and the fifth dielectric layer 08 and the fourth dielectric layer 07 thereunder to above the second polysilicon layer 06 to form the device structure as shown in FIG. Figure 15 The structure shown.

[0065] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0066] In summary, the present invention's method for fabricating a silicon-germanium heterojunction transistor reduces the etching requirements for forming the silicon nitride overhanging sidewalls, resulting in a simple process and low production costs. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a germanium-silicon heterojunction transistor, characterized in that: At least: Step 1: providing a substrate, on which an STI is formed to define an active area, forming a first dielectric layer on the substrate, forming a first polysilicon layer on the first dielectric layer, and forming a second dielectric layer on the polysilicon layer. Then, removing portions of the second dielectric layer and the first polysilicon layer by photolithography and etching to form a first stack located on the active area, forming a third dielectric layer covering the first stack and the first dielectric layer, and then etching the third dielectric layer to form sidewalls on the sidewalls of the first stack. Step 2: forming a second polysilicon layer covering the first stack and the sidewalls and a fourth dielectric layer covering the second polysilicon layer on the first dielectric layer, and removing a portion of the fourth dielectric layer until the sidewalls are exposed by photolithography and etching, wherein the fourth dielectric layer is etched by wet etching until the sidewalls are exposed; Step 3: etching and removing the second dielectric layer and the sidewall spacer to form a first pattern structure; Step 4: forming a fifth dielectric layer on the first pattern structure, and then etching the fifth dielectric layer to above the first polysilicon layer; Step 5: etching and removing the first polysilicon layer to expose the first dielectric layer thereunder, and then etching the exposed first dielectric layer to form an inverted T-shaped groove; Step 6: forming an epitaxial layer at the bottom of the groove, and then forming a third polysilicon layer on the epitaxial layer to fill the remaining groove, so as to form a second pattern structure; Step seven: etching the second graphic structure to form a desired device structure.

2. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The substrate in step 1 is a silicon substrate.

3. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the first dielectric layer in step 1 is silicon dioxide.

4. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the second dielectric layer in step 1 is silicon nitride.

5. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the third dielectric layer in step 1 is silicon nitride.

6. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the fourth dielectric layer in step 2 is silicon dioxide.

7. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The material of the fifth dielectric layer in step 4 is silicon nitride.

8. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: In step five, the first polysilicon layer is removed by dry etching.

9. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: In step five, the exposed first dielectric layer is etched by wet etching to form the inverted T-shaped groove.

10. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The epitaxial layer in step six is a silicon-germanium epitaxial layer.

11. The method for manufacturing a silicon-germanium heterojunction transistor according to claim 1, wherein: The method of etching the second graphic structure to form the desired device structure in step seven includes: forming a first photoresist layer on the third polysilicon layer, photolithographically opening the first photoresist layer to expose the third polysilicon layer thereunder, and etching the exposed third polysilicon layer and the fifth dielectric layer, the fourth dielectric layer, and the second polysilicon layer thereunder to above the first dielectric layer; removing the remaining first photoresist layer, forming a second photoresist layer on the etched third polysilicon layer, photolithographically opening the second photoresist layer to expose the third polysilicon layer thereunder, and etching the exposed third polysilicon layer and the fifth dielectric layer and the fourth dielectric layer thereunder to above the second polysilicon layer.

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