Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, including: a substrate including a first region and a second region; an initial fin on the substrate; a gate structure on the substrate and covering the initial fin; a first fin on the first region and on both sides of the gate structure; a second fin on the second region and on both sides of the gate structure, the first fin having a width greater than a width of the second fin; a first sidewall on sidewalls of the first fin; a second sidewall on sidewalls of the second fin; a first source / drain doped layer on the first fin and having a bottom between the first sidewall; a second source / drain doped layer on the second fin and having a bottom between the second sidewall; an isolation layer on the substrate, a top surface of the first fin being lower than a top surface of the isolation layer, and a top surface of the second fin being higher than the top surface of the isolation layer; the semiconductor structure and the method of forming the same can effectively improve performance of a final semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the improvement of the integration of semiconductor devices, the critical dimension of the transistor is continuously reduced. However, with the sharp reduction of the transistor size, the difficulty of inhibiting the short channel effect is increased due to the unchangeable thickness of the gate dielectric layer and the working voltage, and the channel leakage current of the transistor is increased.

[0003] The gate of the fin field-effect transistor (FinFET) is a fork-shaped 3D structure similar to a fish fin. The channel of the FinFET protrudes from the substrate surface to form a fin, and the gate covers the top surface and the sidewall of the fin, so that the inversion layer is formed on each side of the channel, and the on and off of the circuit can be controlled on both sides of the fin. This design can increase the control of the gate on the channel region, thereby effectively inhibiting the short channel effect of the transistor. However, the fin field-effect transistor still has the short channel effect.

[0004] In addition, in order to further reduce the influence of the short channel effect on the semiconductor device and reduce the channel leakage current, the strained silicon technology is introduced in the technical field of semiconductor. The method of the strained silicon technology includes: forming a groove in the fin on both sides of the gate structure; and forming a source / drain doped region in the groove by an epitaxial growth process.

[0005] However, with the reduction of the size of the semiconductor device and the improvement of the device density, the performance of the formed fin field-effect transistor is unstable. SUMMARY

[0006] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.

[0007] To solve the above problems, the application provides a semiconductor structure, comprising: a substrate comprising a first region and a second region; an initial fin located on the substrate; a gate structure located on the substrate and covering the initial fin; a first fin located on the first region and on both sides of the gate structure; a second fin located on the second region and on both sides of the gate structure, the width of the first fin being greater than the width of the second fin; a first sidewall located on the sidewall of the first fin; a second sidewall located on the sidewall of the second fin; a first source-drain doped layer located on the first fin and having a bottom between the first sidewalls; a second source-drain doped layer located on the second fin and having a bottom between the second sidewalls; an isolation layer located on the substrate, the top surface of the first fin being lower than the top surface of the isolation layer, and the top surface of the second fin being higher than the top surface of the isolation layer.

[0008] Optionally, the top surface of the first fin is 10-30 nm lower than the top surface of the isolation layer.

[0009] Optionally, the gate structure is a dummy gate structure or a metal gate structure.

[0010] Optionally, the height of the first sidewall is less than the height of the second sidewall.

[0011] Correspondingly, the application also provides a method for forming the semiconductor structure, comprising: providing a substrate comprising a first region and a second region; forming an initial fin on the substrate; forming a gate structure on the substrate, the gate structure covering part of the sidewall and part of the top of the initial fin; etching part of the initial fin on the first region on both sides of the gate structure to form a first fin; etching part of the initial fin on the second region on both sides of the gate structure to form a second fin, the width of the first fin being greater than the width of the second fin; forming a first source-drain doped layer on the first fin; and forming a second source-drain doped layer on the second fin.

[0012] Optionally, before forming the gate structure, the method further comprises: forming an isolation layer on the substrate, the isolation layer covering part of the sidewall of the initial fin.

[0013] Optionally, the step of forming the first fin and the second fin comprises: thinning the initial fin on both sides of the gate structure to form a thinned fin; forming a sidewall on the bottom sidewall of the thinned fin; etching part of the thinned fin until the top surface of the thinned fin is flush with the top surface of the sidewall; etching the thinned fin and the sidewall of the first region to form the first fin and a first sidewall; and etching the thinned fin and the sidewall of the second region to form the second fin and a second sidewall.

[0014] Optionally, the top surface of the first fin is lower than the top surface of the isolation layer, and the top surface of the second fin is higher than the top surface of the isolation layer.

[0015] Optionally, the top surface of the first fin is 10-30 nm lower than the top surface of the isolation layer.

[0016] Optionally, the height of the first sidewall is smaller than the height of the second sidewall.

[0017] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0018] In the technical scheme of the present application, since the width of the first fin is greater than the width of the second fin, the volume of the first source / drain doping layer can be ensured to be greater than the volume of the second source / drain doping layer in the process of forming the first source / drain doping layer on the first fin and the second source / drain doping layer on the second fin, so that two source / drain doping layers with different volumes can be formed on the same substrate, the demand of different device regions for source / drain doping layers with different volumes is met, the quality of the semiconductor device formed finally is ensured, and the cost is saved, which is helpful to form a semiconductor device with higher integration and expand the use range of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a structural schematic diagram of a semiconductor structure;

[0020] Figures 2 to 12 is a structural schematic diagram of each step of the forming method of the semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0021] As described in the background, the semiconductor structure formed by the prior method has poor performance. The following will be specifically described with reference to the drawings.

[0022] Please refer to Figure 1 , a substrate 100, including a first region I and a second region II; a first fin 101 located on the substrate of the first region I; a second fin 102 located on the substrate of the second region II; a first source / drain doping layer 103 located on the first fin 101; and a second source / drain doping layer 104 located on the second fin 102.

[0023] In the above embodiments, the first region is used to form a logic device region, and the second region is used to form a static random access memory region. The first source-drain doped layer 103 in the first region requires a large epitaxial volume to achieve greater stress and thus ensure the device performance of the logic device region. The second source-drain doped layer 104 in the second region requires a smaller epitaxial volume to ensure that the static random access memory region does not experience bridging problems during operation. However, during the formation of the first source-drain doped layer 103 and the second source-drain doped layer 104, the epitaxial volumes of the first source-drain doped layer 103 and the second source-drain doped layer 104 are close, which cannot simultaneously meet the requirements of the first region and the second region for the source-drain doped layer, thereby affecting the performance of the semiconductor device and limiting its use.

[0024] Based on this, the present invention provides a semiconductor structure and a method for forming the same, wherein a first fin is formed on a first region and a second fin is formed on a second region. By utilizing the fact that the width of the first fin is greater than the width of the second fin, it is possible to ensure that the volume of the first source / drain doped layer is greater than the volume of the second source / drain doped layer during the formation of the first source / drain doped layer on the first fin and the formation of the second source / drain doped layer on the second fin. In this way, two source / drain doped layers of different sizes can be formed on the same substrate, meeting the requirements of different device regions for source / drain doped layers of different sizes. This ensures the quality of the final semiconductor device while saving costs and facilitating the formation of semiconductor devices with higher integration, thus expanding the application range of semiconductor devices.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figures 2 to 12 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0027] Please refer to the following first. Figure 2 A substrate 200 is provided, the substrate 200 including a first region I and a second region II, and an initial fin 201 is formed on the substrate 200.

[0028] The method for forming the substrate 200 and the initial fin 201 includes: providing an initial substrate (not shown) having a mask layer (not shown) on the initial substrate, the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the initial fin 201 located on the substrate 200.

[0029] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0030] In this embodiment, the initial fin 201 is made of silicon; in other embodiments, the initial fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0031] The first region I and the second region II are distributed adjacent to each other.

[0032] In this embodiment, the first area I is used to form logic devices and is named the logic device area, and the second area II is used to form static random access memory (SRAM) and is named the static random access memory area.

[0033] In other embodiments, the first region I can be used to form a static random access memory (SRAM), and the second region II can also be used to form a logic device.

[0034] Please continue to refer to this. Figure 2 An isolation layer 202 is formed on the substrate 200, and the isolation layer 202 covers part of the sidewall of the initial fin 201.

[0035] In this embodiment, the top surface of the isolation layer 202 is lower than the top surface of the initial fin 201.

[0036] In this embodiment, the isolation layer 202 adopts a shallow trench isolation structure (STI).

[0037] The insulating layer 202 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0038] The method of forming the isolation layer 202 includes: forming an isolation structure film (not shown) covering the initial fin 201 on the body substrate 200; and etching back the isolation structure film to form the isolation layer 202.

[0039] The process for forming the isolation structure membrane is a deposition process, such as fluid chemical vapor deposition (CVD). Using CVD to form the isolation structure membrane results in better filling performance.

[0040] The steps of the fluid chemical vapor deposition process used to form the isolation structure film include: forming an isolation fluid layer on the substrate 200; and performing water vapor annealing to form the isolation fluid layer into an isolation structure film.

[0041] The parameters for the vapor annealing include: the gases used include oxygen, ozone and gaseous water, and the annealing temperature is 350 degrees Celsius to 750 degrees Celsius.

[0042] For the process of forming a gate structure covering part of the sidewalls and part of the top of the initial fin on the substrate, please refer to [reference needed]. Figures 3 to 6 .

[0043] In this embodiment, the gate structure is a pseudo-gate structure.

[0044] In other embodiments, the gate structure may also be a metal gate structure.

[0045] Please refer to the following first. Figure 3 A pseudo-gate dielectric layer 203 is formed on the top surface and sidewall of the initial fin 201.

[0046] In this embodiment, the dummy gate dielectric layer 203 provides a material layer for the subsequent formation of the dummy gate structure.

[0047] The material of the pseudo-gate dielectric layer 203 is silicon oxide.

[0048] In this embodiment, the pseudo-gate dielectric layer 203 is formed using an in-situ steam generation (ISSG) process. The pseudo-gate dielectric layer 203 formed by the in-situ steam generation process has good step coverage capability, enabling the formed pseudo-gate dielectric layer 203 to tightly cover the sidewall surface of the initial fin 201, and the thickness of the formed pseudo-gate dielectric layer 203 is uniform.

[0049] In another embodiment, the pseudo-gate dielectric layer 203 is formed by a chemical oxidation process; the method of the chemical oxidation process includes: oxidizing the exposed sidewalls and top surface of the initial fin 201 with an aqueous solution of ozone to form the pseudo-gate dielectric layer 203.

[0050] Please refer to Figure 4 A pseudo-gate layer 204 is formed on the pseudo-gate dielectric layer 203, covering part of the sidewalls and top of the initial fin 201. A protective layer 205 is formed on the pseudo-gate layer 204. The pseudo-gate layer 204 and the protective layer 205 between the first region I and the second region II are etched away to form an opening 206, the bottom of which exposes the surface of the substrate.

[0051] The method of forming the dummy gate layer 205 includes: forming a dummy gate film (not shown) covering the initial fin 201 on a semiconductor substrate 200 and the initial fin 201; etching the dummy gate film to expose the dummy gate dielectric layer 203 on the initial fin 201; and forming a dummy gate layer 204 on the initial fin 201.

[0052] The dummy gate structure includes a dummy gate dielectric layer 203 spanning the initial fin 201 and a dummy gate layer 204 located on the dummy gate dielectric layer 203.

[0053] In this embodiment, the material of the pseudo-gate layer 205 is polycrystalline silicon.

[0054] The dummy gate structure also includes a protective layer 205 located on the surface of the dummy gate layer 204. The protective layer 205 protects the dummy gate layer 204 when the source and drain doped layers are subsequently formed, and also serves as a stop layer for the subsequent planarization dielectric layer.

[0055] The material of the protective layer 205 includes silicon oxide or silicon nitride.

[0056] In this embodiment, the dummy gate layer 204 and the protective layer 205 between the first region I and the second region II are etched away to form an opening 206, the bottom of which exposes the surface of the substrate.

[0057] The etching process employs a dry etching process; in other embodiments, a wet etching process may also be used to etch and remove the dummy gate layer 204 and the protective layer 205 between the first region I and the second region II, forming an opening 206.

[0058] In this embodiment, the purpose of forming the opening 206 is to enable the final gate structure to be disconnected between the first region I and the second region II, allowing for different gate controls.

[0059] Please refer to Figures 5 to 6 Protective sidewalls 207 are formed on the sidewalls of the dummy gate layer 204, the sidewalls of the protective layer 205, and the sidewalls of the opening 206.

[0060] Figure 6 yes Figure 5 Top view, Figure 5 yes Figure 6 Cross-sectional view along section AA.

[0061] In this embodiment, the material of the protective sidewall 207 is silicon oxide; in other embodiments, the material of the protective sidewall 207 may also be silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or silicon carbonitride.

[0062] In this embodiment, the protective sidewall 207 defines the distance between the subsequently formed gate structure and the source / drain doped layers.

[0063] In this embodiment, the protective sidewall 207 is formed by one or more combinations of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0064] The dummy gate structure includes the dummy gate dielectric layer 203, the dummy gate layer 204 located on the dummy gate dielectric layer 203, the protective layer 205 located on the dummy gate layer 204, and the protective sidewall 207 located on the sidewall of the dummy gate layer 204 and the sidewall of the protective layer 205.

[0065] The process of etching a portion of the initial fin on both sides of the dummy gate structure to form a first fin and etching a portion of the initial fin on both sides of the dummy gate structure to form a second fin is described in the following reference. Figures 7 to 11 .

[0066] Please refer to Figure 7 The initial fins 201 on both sides of the pseudo-gate structure are thinned to form thinned fins 208.

[0067] Figure 7 yes Figure 6 Cross-sectional view at BB.

[0068] In this embodiment, the thinned initial fin 201 is located in the source / drain doped region, preparing for the subsequent formation of the source / drain doped layer.

[0069] In this embodiment, the purpose of thinning the initial fin 201 to form the thinned fin 208 is to form a fin with a smaller width on the second region. This allows for the formation of a source / drain doped layer on the thinner fin, resulting in a smaller epitaxial volume of the source / drain doped layer. This prevents bridging between the source / drain doped layers on the second region and avoids affecting the performance of the formed semiconductor device.

[0070] In this embodiment, the thinned fin 208 is formed by a dry etching process; in other embodiments, the thinned fin 208 may also be formed by a wet etching process.

[0071] Please refer to Figure 8 A sidewall 209 is formed on the bottom sidewall of the thinned fin 208.

[0072] Figure 8 View direction and Figure 7 The view orientation is consistent.

[0073] In this embodiment, the sidewall 209 is made of silicon nitride; in other embodiments, the sidewall 209 may also be made of silicon oxide, silicon carbide, or silicon oxynitride.

[0074] In this embodiment, the purpose of forming the sidewall 209 is to protect the thinned fins 208 between the sidewalls 209 during the subsequent etching process of removing part of the thinned fins 208, thereby ensuring that the bottom of the source / drain doped layer has high-quality fins when the source / drain doped layer is formed, and ensuring the quality of the final semiconductor device.

[0075] In this embodiment, the process for forming the sidewall 209 is atomic layer deposition.

[0076] In other embodiments, the process for forming the sidewall 209 may also be a chemical vapor deposition process or a physical vapor deposition process.

[0077] Please refer to Figure 9 The thinned fin 208 is partially etched away until the top surface of the thinned fin 208 is flush with the top surface of the sidewall 209.

[0078] In this embodiment, the etching process for removing part of the thinned fin 208 is a dry etching process; in other embodiments, a wet etching process may also be used to remove part of the thinned fin 208.

[0079] In this embodiment, the purpose of removing part of the thinned fin 208 is to provide space for the subsequent formation of source and drain doped layers.

[0080] Please refer to Figure 10 The thinned fin portion 208 and the sidewall 209 of the first region I are etched to form the first fin portion 210 and the first sidewall 211.

[0081] In this embodiment, the top surface of the first fin 210 is lower than the top surface of the isolation layer 202, and the top surface of the first fin 210 is 10 nanometers to 30 nanometers lower than the top surface of the isolation layer 202.

[0082] In this embodiment, since the first fin 210 is covered by the isolation layer 202, the width of the first fin 210 is the same as the width of the initial fin 201. Thus, the first fin 210 has a large width, which provides conditions for the subsequent formation of a large source / drain doped layer.

[0083] In this embodiment, the top surface of the first fin 210 is lower than the top surface of the isolation layer 202 by 10 to 30 nanometers. When the height by which the top surface of the first fin 210 is lower than the top surface of the isolation layer 202 is less than 10 nanometers, the channel stress of the device decreases and the device performance deteriorates. When the height by which the top surface of the first fin 210 is lower than the top surface of the isolation layer 202 is greater than 30 nanometers, it will affect the control of the short-channel effect and increase the leakage current at the source and drain terminals of the device.

[0084] In this embodiment, when forming the first fin 210 and the first sidewall 211, photoresist (not shown in the figure) is pre-formed on the thinned fin 208 and the sidewall 209 in the second region II. This ensures that the thinned fin 208 and the sidewall 209 in the second region II will not be affected during the formation of the first fin 210 and the first sidewall 211.

[0085] Please refer to Figure 11 The thinned fin portion 208 and the sidewall 209 of the second region II are etched to form the second fin portion 212 and the second sidewall 213.

[0086] In this embodiment, the top surface of the second fin 212 is higher than the top surface of the isolation layer 202, in order to ensure that the second fin 212 has a smaller width.

[0087] In the figure, D represents the width of the first fin 210, and d represents the width of the second fin 212.

[0088] In this embodiment, the width of the first fin 210 is greater than the width of the second fin 212. This allows for the formation of a first source / drain doped layer on the first fin 210 and a second source / drain doped layer on the second fin 212, resulting in both a larger first source / drain doped layer and a smaller second source / drain doped layer. This satisfies the requirements of the first region I and the second region II for source / drain doped layers of different sizes, thereby improving the quality and integration density of the formed semiconductor device.

[0089] In this embodiment, the height of the first sidewall 211 is less than the height of the second sidewall 213. This is because during the formation of the first fin 210, part of the sidewall 209 is also etched away, resulting in a first sidewall 211 with a smaller height. During the formation of the second fin 212, the sidewall 209 is etched very little, and the height of the first sidewall 211 is less than that of the second sidewall 213.

[0090] Please refer to Figure 12A first source / drain doped layer 214 is formed on the first fin 210, and a second source / drain doped layer 215 is formed on the second fin 212.

[0091] In this embodiment, the volume of the first source / drain doped layer 214 is larger than the volume of the second source / drain doped layer 215.

[0092] In this embodiment, since the volume of the first source / drain doped layer 214 is larger than the volume of the second source / drain doped layer 215, two source / drain doped layers of different sizes can be formed on the same substrate. This satisfies the requirement that the first source / drain doped layer 214 in the first region I requires a large epitaxial volume to achieve greater stress and thus ensure the device performance of the logic device region. In the second region II, the second source / drain doped layer 215 requires a smaller epitaxial volume to ensure that the static random access memory region does not experience bridging problems during operation. This ensures the quality of the final semiconductor device while saving costs and helping to form semiconductor devices with higher integration, thus expanding the application range of semiconductor devices.

[0093] In this embodiment, the formation process of the first source / drain doped layer 214 and the second source / drain doped layer 215 includes an epitaxial growth process; the process of doping source / drain ions in the first source / drain doped layer 214 and the second source / drain doped layer 215 is an in-situ doping process.

[0094] When the semiconductor device is a P-type device, the materials of the first source / drain doped layer 214 and the second source / drain doped layer 215 include silicon, germanium, or silicon-germanium; the source / drain ions are P-type ions, including boron ions, BF2- ions, or indium ions. When the semiconductor device is an N-type device, the materials of the first source / drain doped layer 214 and the second source / drain doped layer 215 include silicon, gallium arsenide, or indium gallium arsenide; the source / drain ions are N-type ions, including phosphorus ions or arsenic ions.

[0095] Accordingly, the present invention also provides a semiconductor structure including a substrate 200, including a first region I and a second region II; an initial fin 201 located on the substrate 200; a dummy gate structure located on the substrate and covering the initial fin 201; a first fin 210 located on the first region I and located on both sides of the dummy gate structure; a second fin 212 located on the second region II and located on both sides of the dummy gate structure, wherein the width of the first fin 210 is greater than the width of the second fin 212; a first source / drain doped layer 214 located on the first fin 210; and a second source / drain doped layer 215 located on the second fin 212.

[0096] In this embodiment, since the width of the first fin 210 is greater than the width of the second fin 212, when the first source / drain doped layer 214 is formed on the first fin 210 and the second source / drain doped layer 215 is formed on the second fin 212, the volume of the first source / drain doped layer 214 is greater than the volume of the second source / drain doped layer 215. In this way, two source / drain doped layers of different sizes can be formed on the same substrate. This satisfies the requirement that the first source / drain doped layer 214 in the first region I requires a large epitaxial volume to achieve greater stress and thus ensure the device performance of the logic device region. The second source / drain doped layer 215 in the second region II requires a smaller epitaxial volume to ensure that the static random access memory region does not experience bridging problems during operation. This ensures the quality of the final semiconductor device while saving costs and helping to form semiconductor devices with higher integration, thus expanding the application range of semiconductor devices.

[0097] In this embodiment, a first sidewall 211 is also included, located on the sidewall of the first fin 210.

[0098] In this embodiment, a second sidewall 213 is also included, located on the sidewall of the second fin 212, and the height of the first sidewall 211 is less than the height of the second sidewall 213.

[0099] In this embodiment, the height of the first sidewall 211 is less than the height of the second sidewall 213. This is because during the formation of the first fin 210, part of the sidewall 209 is also etched away, resulting in a first sidewall 211 with a smaller height. During the formation of the second fin 212, the sidewall 209 is etched very little, and the height of the first sidewall 211 is less than that of the second sidewall 213.

[0100] In this embodiment, an isolation layer 202 is also included, located on the substrate, wherein the top surface of the first fin is lower than the top surface of the isolation layer, and the top surface of the second fin is higher than the top surface of the isolation layer.

[0101] In this embodiment, the top surface of the first fin 210 is lower than the top surface of the isolation layer 202 by 10 to 30 nanometers. When the height by which the top surface of the first fin 210 is lower than the top surface of the isolation layer 202 is less than 10 nanometers, the channel stress of the device decreases, and the device performance deteriorates. When the height by which the top surface of the first fin 210 is lower than the top surface of the isolation layer 202 is greater than 30 nanometers, it will affect the control of the short-channel effect and increase the leakage current at the source and drain terminals of the device.

[0102] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first region and a second region; The initial fin is located on the substrate; A gate structure is located on the substrate and covers the initial fin; A first fin is located on the first region and on both sides of the gate structure, and the width of the first fin is the same as the width of the initial fin. The second fin is located on the second region and on both sides of the gate structure, and the width of the first fin is greater than the width of the second fin. The first sidewall is located on the sidewall of the first fin. The second sidewall is located on the sidewall of the second fin. The first source / drain doped layer is located on the first fin, and its bottom is located between the first sidewalls; The second source / drain doped layer is located on the second fin and its bottom is located between the second sidewalls. The volume of the first source / drain doped layer is larger than the volume of the second source / drain doped layer. An isolation layer is located on the substrate, wherein the top surface of the first fin is lower than the top surface of the isolation layer, and the top surface of the second fin is higher than the top surface of the isolation layer.

2. The semiconductor structure as described in claim 1, characterized in that, The top surface of the first fin is 10 to 30 nanometers lower than the top surface of the isolation layer.

3. The semiconductor structure as described in claim 1, characterized in that, The gate structure is either a pseudo-gate structure or a metal gate structure.

4. The semiconductor structure as described in claim 1, characterized in that, The height of the first sidewall is less than the height of the second sidewall.

5. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; Initial fins are formed on the substrate; A gate structure is formed on the substrate, covering part of the sidewalls and part of the top of the initial fin; The initial fin is etched on a portion of the first region on both sides of the gate structure to form a first fin, the width of the first fin being the same as the width of the initial fin; The initial fin is etched on a portion of the second region on both sides of the gate structure to form a second fin, wherein the width of the first fin is greater than the width of the second fin; A first source / drain doped layer is formed on the first fin; A second source / drain doped layer is formed on the second fin, wherein the steps of forming the first fin and the second fin include: Thinning the initial fins on both sides of the gate structure to form thinned fins; A sidewall is formed on the bottom sidewall of the thinned fin; The thinned fin portion is etched away until the top surface of the thinned fin is flush with the top surface of the sidewall; The thinned fin and the sidewall in the first region are etched to form the first fin and the first sidewall; The thinned fin and the sidewall of the second region are etched to form the second fin and the second sidewall, wherein the volume of the first source / drain doped layer is larger than the volume of the second source / drain doped layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Prior to forming the gate structure, the method further includes forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewall of the initial fin.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The top surface of the first fin is lower than the top surface of the isolation layer, and the top surface of the second fin is higher than the top surface of the isolation layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The top surface of the first fin is 10 to 30 nanometers lower than the top surface of the isolation layer.

9. The method for forming a semiconductor structure as described in claim 5, characterized in that, The height of the first sidewall is less than the height of the second sidewall.

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