Cascade type hybrid dc and upfc integrated coordination control method, device and medium

Abstract

This invention relates to the field of flexible AC power transmission technology, and particularly to a coordinated control method, equipment, and medium for cascaded hybrid DC and UPFC, comprising the following steps: setting the reactive power control mode of the MMC3 converter station of the cascaded hybrid DC transmission rectifier station at the receiving end to a constant AC system voltage, and the active power control mode to a constant DC voltage; setting a dynamic limiting reactive power support link in the MMC3 converter station; setting the UPFC in series to a constant active power mode; adding a frequency control link to the UPFC active power control loop; and unlocking the UPFC and the hybrid cascaded DC and increasing the power to the rated value. In this invention, based on the frequency support strategy of the UPFC and the voltage support strategy based on dynamic limiting, during system faults, a coordinated active and reactive power control strategy is proposed by combining the relevant control methods of the cascaded hybrid DC and the relevant control methods of the UPFC, which to a certain extent suppresses the backflow of hybrid DC power and provides reactive power support, preventing large fluctuations in AC system frequency and voltage.

Description

Technical Field

[0001] This invention relates to the field of flexible AC power transmission technology, and in particular to a coordinated control method, device and medium between a cascaded hybrid DC and UPFC. Background Technology

[0002] Flexible Alternating Current Transmission Systems (FACTS) are a new technology that integrates power electronics, microprocessor and microelectronics, communication, and control technologies to flexibly and rapidly control AC power transmission. It enhances the stability of AC power grids and reduces the cost of power transmission. This technology improves transmission quality and efficiency by providing induced or reactive power to the grid.

[0003] The Unified Power Flow Controller (UPFC), as one of the third-generation FACTS components, is also the most powerful and comprehensive thyristor control device. By adjusting power and line parameters through control laws, the UPFC can individually or simultaneously perform various functions such as series compensation, parallel compensation, and phase shifting, improving line transmission capacity, stability, and damping oscillations. It possesses unique characteristics for real-time control of transmission line power flow. Compared with other FACTS controllers, the UPFC has a larger control range and more flexible control methods, enabling accurate and flexible control of power flow in transmission lines, thereby balancing power flow in transmission channels and improving the transmission efficiency of scarce corridor resources.

[0004] Hybrid DC transmission, combining the advantages of both conventional DC transmission (Line-commuted Converter based High Voltage Direct Current, LCC-HVDC) and flexible DC transmission (Voltage Source Converter based High Voltage Direct Current, VSC-HVDC), has become an important development direction for DC transmission technology in recent years. While enhancing the resilience against commutation failures at the receiving end of conventional DC systems, the hybrid DC system's landing point structure also facilitates phased construction of projects, reducing the impact on the receiving end's power grid.

[0005] In the existing technology, there is no relevant research to analyze the coordination problem between UPFC and hybrid cascaded DC. For multi-type converter feed-in systems such as the Jiangsu power grid, which contain both cascaded hybrid DC and UPFC, it is urgent to formulate mutual coordination between active and reactive power between the two and utilize their respective control capabilities to improve the system's stable operation.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the general background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] This invention provides a method, device, and medium for coordinated control between a cascaded hybrid DC and UPFC, thereby effectively solving the problems in the background art.

[0008] To achieve the above objectives, the technical solution adopted by this invention is: a coordinated control method between a cascaded hybrid DC and UPFC, comprising the following steps:

[0009] Set the reactive power control mode of the MMC3 converter station of the receiving-end cascaded hybrid DC transmission rectifier station to constant AC system voltage and the active power control mode to constant DC voltage.

[0010] A dynamic limiting reactive power support element is installed in the MMC3 converter station;

[0011] Set the UPFC series connection to constant active power mode;

[0012] Add a frequency control loop to the UPFC active power control loop;

[0013] Unlock UPFC and hybrid cascaded DC and boost power to rated value.

[0014] Furthermore, the dynamic limiting reactive power support component includes:

[0015]

[0016] in, i dlim This is the active current limiting value. i Dlim This is the minimum active current limit that needs to be guaranteed. i q The actual active current being measured. i d The actual reactive current being measured. i lim This is the total limit value for active and reactive current.

[0017] Furthermore, in the MMC3 converter station, the DC side voltage U dc DC side voltage reference value U dcref After passing through the first proportional gain controller, and then through the dynamic active current limiting, the active current reference value is obtained.

[0018] AC side voltage Uac AC side voltage reference value U acref After passing through the second proportional gain controller and the total current limiting value, the reactive current reference value is obtained.

[0019] Furthermore, the actual reactive current i d From reactive power measurement value Q s The result was obtained after reactive power limiting.

[0020] Furthermore, the additional frequency control element includes:

[0021] Active power measurement value P L Active power reference value P ref and additional frequency output P add After proportional-integral circuit and active current limiting value i dlim After limiting, the output is the active current output. i dref .

[0022] Furthermore, the additional frequency element outputs... P add Due to frequency deviation Δ f The result is obtained after passing through a first-order filtering stage, a proportional-integral stage, and a limiting stage.

[0023] The present invention also includes a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the method described above.

[0024] The present invention also includes a storage medium storing a computer program that, when executed by a processor, implements the method described above.

[0025] The beneficial effects of this invention are as follows: Based on the frequency support strategy of UPFC and the voltage support strategy based on dynamic limiting, this invention proposes an active and reactive power coordination control strategy by combining the cascaded hybrid DC related control method and the UPFC related control method during system faults. This strategy can suppress the backflow of hybrid DC power to a certain extent and provide reactive power support, thereby preventing large fluctuations in AC system frequency and voltage. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a topology diagram of a DC-AC system containing UPFC and hybrid cascaded DC-AC systems;

[0028] Figure 2 This is a flowchart of the method of the present invention;

[0029] Figure 3 This is a diagram of the dynamic amplitude limiting control strategy;

[0030] Figure 4 This is a strategy diagram for the additional active frequency control in the UPFC of this invention;

[0031] Figure 5 A comparison chart of the power outputs of the three MMC converter stations;

[0032] Figure 6 This is a comparison chart of AC system frequencies with and without coordinated control in the verification scheme of this invention;

[0033] Figure 7 This is a comparison chart of AC voltage frequencies when there is no coordinated control in the verification scheme of this invention;

[0034] Figure 8 This is a schematic diagram of the structure of the computer device of the present invention. Detailed Implementation

[0035] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0036] like Figure 1 As shown, Figure 1This diagram illustrates the topology of a hybrid DC / AC transmission receiving end and a UPFC (Uplink Power Supply). The rectifier station consists of two sets of 12-pulse LCCs connected in series, while the inverter station consists of one set of 12-pulse commutated LCCs and a parallel series group of voltage source converters (VSCs). The low-end VSCs are extended to multiple VSCs connected in parallel and distributed across different regional power grids. The MMC (Modular Multilevel Converter) in the diagram is a type of VSC. The UPFC is installed after MMC3. UPFC converter 2 is connected in parallel to the system. Besides providing active power to converter 1, it can also absorb or inject reactive power into the system through a transformer, acting as a controllable parallel static var compensator. Converter 1 is connected in series to the system, injecting a series voltage with adjustable amplitude and phase angle into the line.

[0037] like Figure 2 As shown: A coordinated control method between a cascaded hybrid DC and UPFC includes the following steps:

[0038] Set the reactive power control mode of the MMC3 converter station of the receiving-end cascaded hybrid DC transmission rectifier station to constant AC system voltage and the active power control mode to constant DC voltage.

[0039] A dynamic limiting reactive power support element is installed in the MMC3 converter station;

[0040] Set the UPFC series connection to constant active power mode;

[0041] Add a frequency control loop to the UPFC active power control loop;

[0042] Unlock UPFC and hybrid cascaded DC and boost power to rated value.

[0043] Based on the frequency support strategy of UPFC and the voltage support strategy based on dynamic limiting, during system faults, a coordinated active and reactive power control strategy is proposed by combining the cascaded hybrid DC related control method and the UPFC related control method. This strategy can suppress the backflow of hybrid DC power to a certain extent and provide reactive power support, thereby preventing large fluctuations in AC system frequency and voltage.

[0044] like Figure 3 As shown, i* dlim This is the dynamic limit value for active current. i dlim This is the active current limiting value. i lim This is the total current limit value. U dc , U dcref These are the measured and reference values ​​of the DC side voltage of the inverter station; U ac , U acrefThese are the measured and reference values ​​of the AC side voltage of the inverter station; Q s , Q sq These are the reactive power measurement values ​​and limiting values. PI1 and PI2 are proportional gain controllers 1 and 2. i sq and i* qref These are all calculated reference values ​​for reactive current. i* dref This is the calculated reference value for active current.

[0045] In this embodiment, the dynamic limiting reactive power support component includes:

[0046]

[0047] in, i dlim This is the active current limiting value. i Dlim This is the minimum active current limit that needs to be guaranteed. i q The actual active current being measured. i d The actual reactive current being measured. i lim This is the total limit value for active and reactive current.

[0048] In the MMC3 converter station, the DC side voltage U dc DC side voltage reference value U dcref After passing through the first proportional gain controller, and then through the dynamic active current limiting, the active current reference value is obtained.

[0049] AC side voltage U ac AC side voltage reference value U acref After passing through the second proportional gain controller and the total current limiting value, the reactive current reference value is obtained. Actual reactive current... i d From reactive power measurement value Q s The result was obtained after reactive power limiting.

[0050] Compared to the traditional limiting circuit where the active and reactive currents have fixed limiting values, this embodiment changes the active limiting parameter and increases the reactive limiting parameter. That is, by squeezing out a portion of the active power, more reactive power is released. In the event of a fault in the receiving-end system, the potential of flexible DC to support the reactive power of the AC system can be released, thereby increasing the voltage stability of the AC system.

[0051] like Figure 4 As shown, in this embodiment, the additional frequency control circuit includes:

[0052] Active power measurement value P L Active power reference value P ref and additional frequency output P add After proportional-integral circuit and active current limiting value i dlim After limiting, the output is the active current output. i dref .

[0053] Among them, the output of the additional frequency stage P add Due to frequency deviation Δ f The result is obtained after passing through a first-order filtering stage, a proportional-integral stage, and a limiting stage.

[0054] In the diagram, Δ f To address frequency deviation, the controller output signal is added to the original control circuit via a first-order filter, a proportional-integral (PI) circuit, and a limiting circuit, respectively, thus achieving additional frequency control. P ref This is a reference value for active power. P L This is the measured value of active power. P add For the output of the additional frequency stage, i dlim This is the active current limiting value. i dref For active current output, T It is a time constant. K pa , K ia , K p , K i All of these are proportional-integral parameters of the controller.

[0055] by Figure 1Taking the system as an example for verification, dynamic limiting is designed in the outer loop control of the hybrid DC MMC3 converter station, and additional frequency control is designed in the UPFC series converter. In the initial state of the system, the inverter-side LCC current command value is 1 pu, which is 5kA. It is set to change the DC current command value of LCC to 0.5 pu and increase the reactive load at 2s. Simulations are carried out under two conditions: no coordinated control strategy and coordinated control strategy.

[0056] At this time, the AC system frequency fluctuates significantly, dropping to 49.87 Hz, such as Figures 5 to 6 As shown, after adopting the frequency support coordinated control strategy proposed in this paper, the UPFC quickly responds to changes in the system's active power, adjusts the power command value, suppresses power backfeeding, and the frequency quickly recovers to a stable operating state, providing stable frequency support for the system. Simultaneously, a reactive power deficit occurs on the AC side of the system, such as... Figure 7 As shown, the AC voltage dropped from 500KV to around 350KV, exhibiting significant fluctuations. When the AC voltage decreased to 440KV, compared to before the control strategy was implemented, the AC voltage fluctuation was reduced by approximately 100KV, effectively achieving voltage support for the AC system.

[0057] Please see Figure 8 The diagram shows a structural schematic of a computer device provided in an embodiment of this application. An embodiment of this application provides a computer device 400, including a processor 410 and a memory 420. The memory 420 stores a computer program executable by the processor 410. When the computer program is executed by the processor 410, it performs the method described above.

[0058] This application embodiment also provides a storage medium 430, on which a computer program is stored, and the computer program is executed by a processor 410 to perform the above method.

[0059] The storage medium 430 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0060] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0061] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0063] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0064] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0065] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0066] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0067] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for coordinating control between a cascade type hybrid DC and UPFC, characterized in that, The method comprises the following steps: Setting the reactive power control mode of the MMC3 converter station of the receiving end cascaded hybrid DC power transmission rectifier station to fixed AC system voltage and the active power control mode to fixed DC voltage; Setting a dynamic limiting reactive power support link in the MMC3 converter station; Setting the UPFC in series to fixed active power mode; Adding a frequency control link to the UPFC active power control loop; Unlocking the UPFC and increasing the power to the rated value; The dynamic limiting reactive power support link comprises: ； wherein, i dlim is the active current limit value, i Dlim is the minimum active current limit value to be guaranteed, i q is the measured actual active current, i d is the measured actual reactive current, i lim is the total active and reactive current limit value; In the MMC3 converter station, the DC side voltage U dc The DC side voltage reference value U dcref After passing through the first proportional gain controller, and then passing through the dynamic active current limiting, the active current reference value is obtained; AC side voltage U ac with the AC side voltage reference value U acref After passing through the second proportional gain controller, passing through the total current limiting value, the reactive current reference value is obtained; The additional frequency control link comprises: measured value of active power P L reference value of active power P ref and an additional frequency element output P add through a proportional-integral element and an active current limit value i dlim after limiting, the output results in an active current output i dref .

2. The method of claim 1, wherein the method is characterized by: The actual reactive current i d The reactive power measurement value Q s After the reactive power is limited, the calculation is obtained.

3. The method of claim 1, wherein the method is characterized by: the additional frequency loop output P add from the frequency deviation Δ f is obtained after sequentially passing through a first-order filter loop, a proportional-integral loop, and a limiting loop.

4. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method in any one of claims 1-3.

5. A storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the method in any one of claims 1-3.

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