Isolated switching converter and controller and control method thereof

Abstract

This invention discloses an isolated switching converter, its controller, and a control method. The switching converter includes a transformer, a primary switching transistor, and an isolation circuit. The control method includes: providing a gradually increasing current threshold voltage during startup; generating a first compensation signal based on the difference between an output feedback signal representing the switching converter's output signal and a reference voltage; generating first and second control signals based on the first compensation signal; sending the first control signal into a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal into a second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; ending the startup process when the secondary side is activated, providing a current threshold voltage based on the first synchronization signal; and turning off the primary switching transistor based on a current detection signal and the current threshold voltage.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to a quasi-resonant controlled isolated switching converter, its controller, and control method. Background Technology

[0002] Isolated switching converters typically include a transformer with primary and secondary windings to provide isolation. A primary switch is coupled to the primary winding, controlling the transfer of energy stored in the primary winding to the secondary winding. A secondary switch is coupled to the secondary winding, providing the output voltage to loads coupled to the secondary side output. In peak current controlled isolated switching power supplies, the primary switch is turned off when the current flowing through it reaches a turn-off threshold, thereby controlling the energy transferred to the load.

[0003] Isolated switching converters typically have a startup process. At the very beginning of startup, the secondary-side output voltage has not yet established itself; for example, it is typically the potential of the secondary reference ground. There is a significant difference between the output voltage and the desired output voltage. In this situation, using feedback may be useless and unstable, resulting in poor transient response of the system. Furthermore, during startup, the current demand of the isolated switching converter is low, and the output voltage of an isolated converter using constant peak current control can rise very quickly, even causing output voltage overshoot. Simultaneously, the power devices in the circuit must withstand these stresses and pressures during startup, further impacting the cost and efficiency of the isolated switching converter. Summary of the Invention

[0004] In view of one or more problems existing in the prior art, the purpose of the present invention is to provide a method that can control an isolated switching converter to safely and smoothly complete its startup process throughout the startup process, without incurring additional costs and increasing complexity.

[0005] According to an embodiment of the present invention, a controller for an isolated switching converter includes a transformer and a primary switching transistor. The controller includes: an error amplifier circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives an output feedback signal related to the output signal of the switching converter, the second input terminal receives a reference voltage, and the error amplifier circuit generates a first compensation signal at the output terminal based on the difference between the output feedback signal and the reference voltage; a control signal generation circuit generating a first control signal and a second control signal at the output terminal based on the first compensation signal; and an isolation circuit having a first channel for transmitting the first control signal and a second channel for transmitting the second control signal, and providing a first synchronization signal electrically isolated from the first control signal at the first output terminal. The circuit provides a second synchronization signal electrically isolated from the second control signal at the second output terminal; a reset signal generation circuit has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a current detection signal representing the current flowing through the primary switch, the second input terminal receives a current threshold voltage, the reset signal generation circuit compares the current detection signal with the current threshold voltage, and generates a reset signal at the output terminal to control the turn-off of the primary switch; a threshold generation circuit provides the current threshold voltage at the output terminal, the threshold generation circuit including: a startup threshold generation circuit that provides a gradually increasing current threshold voltage during startup; and a normal threshold generation circuit that ends the startup process when the secondary side is activated, and provides the current threshold voltage based on the first synchronization signal.

[0006] An isolated switching converter according to an embodiment of the present invention includes the controller as described above.

[0007] According to an embodiment of the present invention, a control method for an isolated switching converter includes a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, a secondary switching transistor coupled to the secondary winding, and an isolation circuit. The control method includes: providing a gradually increasing current threshold voltage during startup; generating an output feedback signal based on an output signal of the switching converter; generating a first compensation signal based on the difference between the output feedback signal and a reference voltage; generating a first control signal and a second control signal based on the first compensation signal; sending the first control signal into a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal into a second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; detecting whether the secondary side is activated; ending the startup process when the secondary side is activated, and providing the current threshold voltage based on the first synchronization signal; and comparing a current detection signal representing the current flowing through the primary switching transistor with the current threshold voltage to generate a reset signal to turn off the primary switching transistor.

[0008] According to an embodiment of the present invention, during startup, soft-start control is introduced on the primary side of the isolated switching converter to soft-start the current threshold voltage to control the energy supplied to the secondary side. Upon activation on the secondary side and the end of the startup process, a first synchronization signal controlling the current threshold voltage is received through an isolation circuit. Based on this first synchronization signal, the current threshold voltage is controlled to achieve control of the isolated converter operating in steady state. Furthermore, soft-start control is also introduced on the secondary side of the switching converter to soft-start the reference voltage during startup to prevent output voltage overshoot. This allows the isolated switching converter to safely and smoothly complete its startup process. Additionally, according to an embodiment of the present invention, during startup, the isolated switching converter is restricted to operating in the first valley conduction mode, further reducing the operating stress on the power converter and saving system costs. Attached Figure Description

[0009] Figure 1 This is a block diagram of an isolated switching converter 100 according to an embodiment of the present invention;

[0010] Figure 2 This is a block diagram of an isolated switching converter 100A according to an embodiment of the present invention;

[0011] Figure 3 This is a circuit schematic diagram of an error amplifier circuit 101 and a control signal generation circuit 102 according to an embodiment of the present invention.

[0012] Figure 4 This is a circuit schematic diagram of a threshold generation circuit 104 according to an embodiment of the present invention;

[0013] Figure 5 A waveform diagram of the current threshold voltage during startup according to an embodiment of the present invention;

[0014] Figure 6 This is a waveform diagram of the current threshold voltage after startup according to an embodiment of the present invention;

[0015] Figure 7 This is a circuit schematic diagram of the primary-side control circuit according to an embodiment of the present invention;

[0016] Figure 8 This is a block diagram of an isolating switch converter 100B according to an embodiment of the present invention;

[0017] Figure 9 This is a waveform diagram of the working process of an isolating switch converter during startup according to an embodiment of the present invention;

[0018] Figure 10 This is a circuit diagram of a portion of the secondary-side control circuit according to an embodiment of the present invention;

[0019] Figure 11This is a flowchart of a control method 700 for an isolated switching converter according to an embodiment of the present invention. Detailed Implementation

[0020] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0021] Throughout this specification, references to “an embodiment,” “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0022] This invention can be applied to any isolated converter. In the following detailed description, for the sake of brevity, only a flyback converter will be used as an example to explain the specific working principle of this invention.

[0023] Figure 1 This is a block diagram of an isolated switching converter 100 according to an embodiment of the present invention. Figure 1As shown, the isolated switching converter 100 includes a transformer T, a primary switch 10, a secondary switch 20, and a controller 30. The transformer T has a primary winding and a secondary winding, both having a first terminal and a second terminal. The first terminal of the primary winding receives an input voltage Vin, and the first terminal of the secondary winding provides a DC output voltage Vo. The second terminal is coupled to a secondary reference ground. The primary switch 10 is coupled between the second terminal of the primary winding and the primary reference ground. The secondary switch 20 is coupled between the second terminal of the secondary winding and the load. However, those skilled in the art will understand that the secondary switch 20 can also be coupled between the first terminal of the secondary winding and the load.

[0024] exist Figure 1 In the illustrated embodiment, the controller 30 of the isolated switching converter 100 incorporates quasi-resonant control. In quasi-resonant control, the switching converter operates in a non-current continuous mode. When the current flowing through the energy storage element (transformer T) drops to zero, the parasitic capacitance of the energy storage element and the primary switching transistor 10 begins to resonate, generating a resonant voltage waveform. When the resonant voltage across the primary switching transistor 10 reaches its minimum value, the primary switching transistor 10 is turned on (commonly referred to as valley conduction), thereby reducing the switching losses and electromagnetic interference of the switching converter 100.

[0025] like Figure 1 As shown, the controller 30 includes an error amplifier circuit 101, a control signal generation circuit 102, an isolation circuit 103, a threshold generation circuit 104, a reset signal generation circuit 106, and a primary logic circuit 107. In some embodiments, the controller 30 and the secondary switch 20 are integrated on the same chip. In another embodiment, the controller 30 also includes a driving circuit for the secondary switch 20.

[0026] exist Figure 1 In the disconnect switch converter 100 shown, the controller 30 has multiple pins, including the output feedback pin FB, the compensation pin COMP, the secondary reference ground pin SGND, the primary current detection pin CS, the primary control pin PDrv, and the primary reference ground pin PGND.

[0027] like Figure 1 As shown, the error amplifier circuit 101 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output feedback pin FB to receive the output feedback signal VFB related to the output signal of the switching converter 100. The second input terminal receives the reference voltage VREF, and the output terminal is coupled to the compensation pin COMP. Figure 1In the illustrated embodiment, a resistor divider consisting of resistors RH and RL is coupled between the output voltage Vo and the output feedback pin FB of the controller to sample the output voltage of the switching converter and provide an output feedback signal VFB. An error amplifier circuit 101 is coupled between the output feedback pin FB and the compensation pin COMP, and generates a first compensation signal Vcomp at the output terminal based on the difference between the output feedback signal VFB and the reference voltage VREF.

[0028] A control signal generation circuit 102 is coupled to the compensation pin COMP to receive a first compensation signal Vcomp. Based on the first compensation signal Vcomp, the control signal generation circuit 102 generates a first control signal PL1 and a second control signal PL2 at its output terminal to control the first threshold voltage VTH and switching frequency of the primary switching transistor 10, respectively. An isolation circuit 103 has a first channel for transmitting the first control signal PL1 and a second channel for transmitting the second control signal PL2. It has a first input terminal for receiving the first control signal PL1, and provides a first synchronization signal SYNC1 electrically isolated from the first control signal PL1 at its first output terminal. It also has a second input terminal for receiving the second control signal PL2, and provides a second synchronization signal SYNC2 electrically isolated from the second control signal PL2 at its second output terminal. In one embodiment, the isolation circuit 103 may include an optocoupler, a transformer, a capacitive isolation device, or any other suitable electrical isolation device. In other embodiments, the isolation circuit 103 may be located external to the controller integrated circuit.

[0029] like Figure 1 As shown, the reset signal generation circuit 106 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the primary current detection pin CS to receive the current detection signal VCS representing the current flowing through the primary switch transistor. The second input terminal is coupled to the output terminal of the threshold generation circuit 104 to receive the current threshold voltage VTH. The reset signal generation circuit 106 compares the current detection signal VCS with the current threshold voltage VTH and provides a turn-off control signal RST at the output terminal to control the turn-off of the primary switch transistor 10. The primary logic circuit 107 generates a primary control signal CTRLP at the output terminal based on the second synchronization signal SYNC2 and the turn-off control signal RST. This CTRLP is coupled to the control terminal of the primary switch transistor 10 via the primary control pin PDrv to control the turn-on and turn-off of the primary switch transistor 10.

[0030] The threshold generation circuit 104 provides a current threshold voltage VTH at its output. The threshold generation circuit 104 includes a startup threshold generation circuit 141, a normal threshold generation circuit 142, and a selection circuit 143. During the startup process of the isolated switching converter 100, the threshold generation circuit 141 is selected to provide a gradually increasing current threshold voltage VTH. When the secondary side is activated and the startup process ends, the normal threshold generation circuit 142 is selected to provide the current threshold voltage VTH. The normal threshold generation circuit 142 is further coupled to the first output of the isolation circuit 103 to receive a first synchronization signal SYNC1, and provides the current threshold voltage VTH based on the first synchronization signal SYNC1.

[0031] exist Figure 1 In the illustrated embodiment, the controller 30 further includes a startup control unit 105. The startup control unit 105 is coupled to a second output of the isolation circuit 103 to receive a second synchronization signal SYNC2, wherein the startup control unit 105 detects whether the secondary side is activated based on the second synchronization signal SYNC2 and provides an activation signal S_ON at its output representing that the secondary side is activated. In one embodiment, the secondary side is activated when the first pulse signal of the second synchronization signal SYNC2 is transmitted to the primary side via the second channel of the isolation circuit 103.

[0032] Figure 2 This is a block diagram of an isolated switching converter 100A according to an embodiment of the present invention. Figure 1 Compared to controller 30, Figure 2 The controller 30A shown further includes a zero-crossing comparator circuit 108 and a set signal generation circuit 109.

[0033] The zero-crossing comparator circuit 108 is used to detect whether the resonant voltage across the primary switch 10 has reached its minimum value, i.e., at the trough. Figure 2 In the illustrated embodiment, the isolated switching converter 100A further includes an auxiliary winding located on the primary side, which is coupled to the zero-crossing detection pin ZCD of the controller 30 via a resistor divider circuit. A zero-crossing comparator circuit 108 is coupled to the zero-crossing detection pin ZCD to receive the zero-crossing detection signal VZCD, compares the zero-crossing detection signal VZCD with the zero-crossing threshold voltage VZCD_TH, and provides a zero-crossing signal SET0 at the output.

[0034] The set signal generation circuit 109 generates a set signal SET at its output terminal, based on the second synchronization signal SYNC2 and the zero-crossing signal SET0, to control the operating frequency of the primary switching transistor 10. Figure 2In the illustrated embodiment, the set signal generation circuit 109 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the second output terminal of the isolation circuit 103 to receive the second synchronization signal SYNC2, and the second input terminal is coupled to the zero-crossing comparator circuit 108 to receive the zero-crossing signal SET0. Based on the zero-crossing signal SET0 and the second synchronization signal SYNC2, the set signal generation circuit 109 provides a set signal SET at its output terminal to control the conduction of the primary switch 10, thereby controlling the operating frequency of the primary switch 10. In one embodiment, during startup, when the resonant voltage of the primary switch 10 first reaches its minimum value, i.e., the primary switch 10 turns on at the first valley. This reduces the operating stress on the power converter and saves system costs. In another embodiment, after the startup process ends, when the second synchronization signal SYNC2 arrives and the resonant voltage of the primary switch 10 reaches its minimum value, the primary switch 10 is turned on.

[0035] Figure 3 This is a circuit schematic diagram of an error amplifier circuit 101 and a control signal generation circuit 102 according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, the error amplifier circuit 101 includes an error amplifier EA. The error amplifier EA has a non-inverting input, an inverting input, and an output, wherein the inverting input receives an output feedback signal VFB, the non-inverting input receives a reference voltage VREF, and the output provides a first compensation signal Vcomp.

[0036] exist Figure 3 In the illustrated embodiment, the control signal generation circuit 102 includes a first control signal generation circuit 120 and a second control signal generation circuit 121. For example... Figure 3 As shown, the first control signal generation circuit 120 includes a hysteresis compensation circuit 1201, a first comparison circuit 1202, and a first pulse circuit 1203. The hysteresis compensation circuit 1201 is coupled to the output of the error amplifier circuit 101 to receive a first compensation signal Vcomp, and provides a second compensation signal Vcomp1 at the output based on the first compensation signal Vcomp. In one embodiment, the hysteresis compensation circuit 1201 is a superposition of the first compensation signal Vcomp and a hysteresis signal. In another embodiment, the second compensation signal Vcomp1 is proportional to the first compensation signal Vcomp, with a proportionality coefficient of K1. In one embodiment, K1 is a number greater than 1.

[0037] A first comparator circuit 1202 is coupled to the output of a hysteresis compensation circuit 1201 to receive a second compensation signal Vcomp1, and is coupled to the output of a modulation signal generation circuit 1210 to receive a modulation signal VCT. The first comparator circuit 1202 compares the second compensation signal Vcomp1 with the modulation signal VCT, and provides a first comparison signal CMP1 at its output. The first comparator circuit 1202A includes a comparator COM1. The non-inverting input of the comparator COM1 receives the second compensation signal Vcomp1, and the inverting input is coupled to the first terminal of the capacitor CT to receive the modulation signal VCT. The first comparison signal CMP1 is provided at its output. A first pulse circuit 1203 receives the first comparison signal CMP1 and provides a pulse-form first control signal PL1 at its output, which is transmitted to the primary side through the first channel of the isolation circuit 103 to control the current threshold voltage VTH.

[0038] exist Figure 3 In the illustrated embodiment, the modulation signal generation circuit 1210 includes a voltage source VPK, a switching transistor ST, a capacitor CT, and a resistor RT. For example... Figure 3 As shown, the voltage source VPK has a positive terminal and a negative terminal, with the negative terminal coupled to the secondary reference ground. The switching transistor ST has a first terminal, a second terminal, and a control terminal; the first terminal is coupled to the positive terminal of the voltage source VPK, and the control terminal is connected to the second control signal PL2. The capacitor CT has a first terminal and a second terminal, with the first terminal coupled to the second terminal of the switching transistor ST, and the second terminal connected to the secondary reference ground. The resistor RT has a first terminal and a second terminal, with the first terminal coupled to the first terminal of the capacitor CT, and the second terminal connected to the secondary reference ground. The modulation signal VCT is generated at the first terminal of the capacitor CT. When the second control signal PL2 is active, the modulation signal VCT is pulled high to its peak voltage, and then begins to decrease until the second control signal PL2 becomes active again.

[0039] exist Figure 3 In the illustrated embodiment, the second control signal generation circuit 121 includes a second comparison circuit 1211, a valley detection circuit 1212, a valley locking circuit 1213, and a second pulse circuit 1214. The second comparison circuit 1211 is coupled to the output of the error amplifier circuit 101 to receive the first compensation signal Vcomp, and coupled to the modulation signal generation circuit 1210 to receive the modulation signal VCT. It compares the modulation signal VCT with the first compensation signal Vcomp and generates a second comparison signal CMP2 at its output. The second comparison circuit 1211A includes a comparator COM2. The non-inverting input of the comparator COM2 receives the first compensation signal Vcomp, and the inverting input is coupled to the first terminal of the capacitor CT to receive the modulation signal VCT. It provides the second comparison signal CMP2 at its output.

[0040] The trough detection circuit 1212 is used to detect the waveform of the secondary-side resonant voltage. In one embodiment, the trough detection circuit 1212 is coupled to the secondary switch 20 to detect the waveform of the resonant voltage and outputs a trough pulse signal VP representing one or more troughs of the resonant voltage. In one embodiment, the trough detection circuit 1212 detects whether the switching voltage across the secondary switch 20 is lower than a trough reference signal during the turn-off period of the secondary switch 20 and outputs the trough pulse signal VP.

[0041] The valley locking circuit 1213 receives a first comparison signal CMP1, a second comparison signal CMP2, and a valley pulse signal VP. At its output, it provides a target valley value for controlling the conduction of the primary switch 10 and generates a frequency control signal FS corresponding to this target valley value. In one embodiment, the valley locking circuit 1213 compares the valley value when the modulation signal VCT reaches the second compensation signal Vcomp1 with the current locked valley value, and determines whether to increase the target valley value based on the comparison result. It also compares the valley value when the modulation signal VCT reaches the first compensation signal Vcomp with the current locked valley value, and determines whether to decrease the target valley value based on the comparison result.

[0042] The second pulse circuit 1214 provides a pulse-form second control signal PL2 at the output terminal based on the frequency control signal FS, which is transmitted to the primary side through the second channel of the isolation circuit 103 to control the valley conduction and switching frequency of the primary switch 10.

[0043] Figure 4 This is a circuit schematic diagram of a threshold generation circuit 104 according to an embodiment of the present invention. Figure 4 In the embodiment shown, the threshold generation circuit 104 includes an activation threshold generation circuit 141, a normal threshold generation circuit 142, and a selection circuit 143.

[0044] The startup threshold generation circuit 141 is used to provide a current threshold voltage VTH that gradually increases from a low threshold voltage V1 to a high threshold voltage V2 during startup. Figure 5 This is a waveform diagram of the current threshold voltage during startup according to an embodiment of the present invention. Figure 5 As shown, during startup, the current threshold voltage VTH gradually increases from the low threshold voltage V1 to the high threshold voltage V2 after a preset number of times (e.g., 8 times). Furthermore, when the switching converter first starts up, it operates at a lower frequency, and the current threshold voltage VTH is equal to the low threshold voltage. As the operating frequency of the primary switch 10 gradually increases, the current threshold voltage VTH gradually increases.

[0045] Figure 6 This is a waveform diagram of the current threshold voltage after startup according to an embodiment of the present invention. The normal threshold generation circuit 142 includes a first capacitor C1. Figure 6 As shown, when the rising edge of the second synchronization signal SNYC2 arrives, the voltage across the first capacitor C1 is set high to the upper threshold voltage Vs2. Then, the voltage across the first capacitor C1 begins to decrease with a certain time constant, and the voltage across the first capacitor C1 is sampled and held when the first synchronization signal SYNC1 arrives to provide the first threshold voltage VTH.

[0046] Continue as Figure 4 As shown, the normal threshold generation circuit 142 further includes a timing circuit 1041, a trigger FF1, voltage sources Vs1 and Vs2, switching transistors S1 and S2, a resistor R2, and a sample-and-hold circuit 1042. The timing circuit 1041 has an input terminal and an output terminal, wherein the input terminal is coupled to the second output terminal of the isolation circuit 103 to receive the second synchronization signal SYNC2. The timing circuit 1041 performs timing based on the second synchronization signal SYNC2 and generates a timing signal DLY at its output terminal. The trigger FF1 has a set terminal, a reset terminal, and an output terminal, wherein the set terminal receives the second synchronization signal SYNC2, and the reset terminal is coupled to the output terminal of the timing circuit 1041 to receive the timing signal DLY. The voltage source Vs1 has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground. The voltage source Vs2 has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground. Switch S1 has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the positive terminal of the voltage source Vs2, and the control terminal is coupled to the output terminal of the flip-flop FF1. Switch S2 has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the positive terminal of the voltage source Vs1 via resistor R2, and the control terminal is coupled to the inverting output terminal of the flip-flop FF1. Sample-and-hold circuit 1042 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first output terminal of isolation circuit 103 to receive the first synchronization signal SYNC1, and the second input terminal is coupled to the first terminal of the first capacitor C1 to receive the voltage across the first capacitor C1. Sample-and-hold circuit 1042 samples and holds the voltage across the first capacitor C1 based on the first synchronization signal SYNC1, and generates a first threshold voltage VTH at the output terminal.

[0047] The selection circuit 143 has a first input terminal, a second input terminal, and a control terminal. The first input terminal is coupled to the output terminal of the start-up threshold generation circuit 141, and the second input terminal is coupled to the output terminal of the normal threshold generation circuit 142. The selection circuit 143 provides a suitable current threshold voltage VTH at the output terminal based on the activation signal S_ON.

[0048] Figure 7 This is a circuit schematic diagram of the primary-side control circuit according to an embodiment of the present invention. Figure 7In the illustrated embodiment, with Figure 2 Compared to the switching converter 100A shown, the transformer T further includes an auxiliary winding having a first terminal and a second terminal, wherein the second terminal of the auxiliary winding is coupled to the primary reference ground. The switching converter also includes a power supply diode Ds, a power supply capacitor Cs, and a power supply current source Iss. The power supply capacitor Cs has a first terminal and a second terminal, wherein the first terminal provides the primary supply voltage Vcc to the control circuit on the primary side, and the second terminal is coupled to the primary reference ground. The power supply diode Ds has an anode and a cathode, wherein the anode is coupled to the first terminal of the auxiliary winding, and the cathode is coupled to the first terminal of the power supply capacitor Cs.

[0049] exist Figure 7 In the illustrated embodiment, the startup control circuit 105 includes an undervoltage latch circuit 151 and a startup circuit 152. The undervoltage latch circuit 151 is coupled to a first terminal of the supply capacitor Cs to receive the supply voltage Vcc and compares it with a first threshold voltage VTH_H and a second threshold voltage VTH_L to generate an undervoltage latch signal UVLO. The supply current source Iss has an input terminal, an output terminal, and a control terminal. The input terminal is coupled to a first terminal of the primary winding to receive an input voltage Vin or a high-voltage input power supply terminal (e.g., HV), the output terminal is coupled to a first terminal of the supply capacitor Cs, and the control terminal is coupled to the undervoltage latch circuit 151 to receive the undervoltage latch signal UVLO. When the supply voltage Vcc is higher than the first threshold voltage VTH_H, the supply current source Iss is turned off. When the supply voltage Vcc is lower than the second threshold voltage VTH_L, the supply current source Iss is turned on, thereby charging the supply capacitor Cs. In some embodiments, when the supply voltage Vcc is lower than the second threshold voltage VTH_L, the primary-side control circuit powered by the supply voltage Vcc mostly stops working to avoid malfunction.

[0050] The startup circuit 152 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the undervoltage latch circuit 151 to receive the undervoltage latch signal UVLO, and the second input terminal is coupled to the second output terminal of the isolation circuit 103 to receive the second synchronization signal SYNC2. Based on the undervoltage latch signal UVLO and the second synchronization signal SYNC2, the startup circuit 152 generates a startup signal STAUP indicating the start of the startup process and an activation signal S_ON indicating the end of the startup process at its output terminal. Figure 7In the illustrated embodiment, the undervoltage latch circuit 151 includes a hysteresis comparator COM0. The startup circuit 152 includes a single trigger circuit 1521 and a flip-flop FF2. The single trigger circuit 1521 has an input and an output, wherein the input is coupled to the undervoltage latch circuit 151 to receive the undervoltage latch signal UVLO. The flip-flop FF2 has a set, a reset, and an output, wherein the set is coupled to the output of the single trigger circuit 1521, the reset is coupled to the output of the isolation circuit 103 to receive the second synchronization signal SYNC2, the output provides a startup signal STAUP, and the inverted output provides an activation signal S_ON. The flip-flop FF2 has reset priority.

[0051] The zero-crossing comparator circuit 108 includes a comparator COM3. The non-inverting input of the comparator COM3 receives the zero-crossing threshold voltage VZCD_TH, and the inverting input is coupled to the zero-crossing detection pin ZCD to receive the zero-crossing detection signal VZCD. The output provides the zero-crossing signal SET0.

[0052] The set signal generation circuit 109A includes an AND gate AND1 and a selection circuit 1091. The AND gate AND1 has a first input, a second input, and an output. The first input receives a second synchronization signal SYNC2, and the second input is coupled to the output of the zero-crossing comparator circuit 108 to receive a zero-crossing signal SET0. The selection circuit 1091 is coupled to the start control circuit 105 and receives a start signal STAUP and an activation signal S_ON. When the start signal STAUP is valid, the selection circuit 1091 selects the zero-crossing signal SET0 as the set signal SET and provides it to the primary logic circuit 107. When the activation signal S_ON goes high, the selection circuit 1091 selects the output of the AND gate AND1 as the set signal SET and provides it to the primary logic circuit. Figure 7 In the embodiment shown, the selection circuit 1091 includes switches Q1 and Q2.

[0053] The reset signal generation circuit 106 includes a comparator COM4. The non-inverting input of comparator COM4 is coupled to the current detection pin CS to receive the current detection signal VCS, and the inverting input is coupled to the output of the threshold generation circuit 104 to receive the threshold voltage VTH. According to an embodiment of the present invention, during startup, i.e., when the startup signal STAUP is valid, the startup threshold generation circuit 141 provides a gradually increasing current threshold voltage VTH. When the activation signal S_ON is valid, the startup process ends, and the normal threshold generation circuit 142 generates the current threshold voltage VTH based on the first synchronization signal SYNC2.

[0054] The primary logic circuit 107 includes a flip-flop FF3. The flip-flop FF3 has a set terminal, a reset terminal, and an output terminal. The set terminal is coupled to the output terminal of the set signal generation circuit 109A to receive the set signal SET. The reset terminal is coupled to the output terminal of the reset signal generation circuit 106 to receive the reset signal RST. The output terminal provides a primary control signal CTRLP to control the on and off of the primary switch 10.

[0055] Figure 8 This is a block diagram of a disconnecting switch converter 100B according to an embodiment of the present invention. Figure 8 The controller 30B shown is Figure 2 Compared to the controller 30A shown, it further includes a secondary start-up control circuit 110 and a reference voltage generation circuit 111 located on the secondary side.

[0056] exist Figure 8 In the illustrated embodiment, controller 30B further includes a secondary power supply pin VDD, coupled to the output voltage Vo, to provide a power supply voltage for the secondary-side control circuit of controller 30B. Secondary startup control circuit 110 is coupled to the secondary power supply pin VD to receive the secondary power supply voltage VDD, and compares the secondary-side power supply voltage VDD with a third threshold voltage Vo. DD_ON In comparison, based on the comparison result, a second activation signal S_ON1 representing the activation of the secondary side is provided at the output terminal. The reference voltage generation circuit 111 is coupled to the secondary startup control circuit 110 to receive the second activation signal S_ON1, and controls the reference voltage VREF based on the second activation signal. Specifically, during startup, the reference voltage VREF gradually increases following the output feedback signal VFB. When the secondary side is activated, and the startup process ends, the reference voltage VREF remains unchanged at the first reference voltage Vref1.

[0057] Figure 9 This is a waveform diagram showing the operation of a disconnector converter during startup according to an embodiment of the present invention. Figure 9 As shown, at time t1, the primary supply voltage Vcc increases to a level greater than the first threshold voltage VTH_H, and the undervoltage lockout signal UVLO goes high. Afterwards, the switching converter starts up, the primary switch 10 begins operating, providing energy to the secondary side, the output voltage Vo begins to increase, and the secondary supply voltage VDD also increases accordingly.

[0058] During startup, the current threshold voltage VTH gradually increases, and the conduction time of the primary switch 10 also gradually increases. The conduction of the primary switch 10 is determined by the zero-crossing signal SET0 generated by the zero-crossing detection signal VZCD and the zero-crossing threshold voltage VZCD_TH.

[0059] At time t2, the secondary supply voltage VDD increases to a level greater than the third threshold voltage V. DD_ONThe second activation signal S_ON1 is active. At time t3, when the first pulse of the second synchronization signal SYNC2 arrives, the activation signal S_ON is set high, and the primary side detects the end of the startup process. Afterwards, the second synchronization signal SYNC2, together with the zero-crossing detection signal VZCD, determines the conduction of the primary switch.

[0060] Figure 10 This is a circuit diagram of a portion of the secondary-side control circuit according to an embodiment of the present invention. Figure 10 In the illustrated embodiment, the secondary startup control circuit 110 includes a comparator COM5. The non-inverting input of comparator COM5 is coupled to the secondary power supply pin VD to receive the secondary power supply voltage VDD, and the non-inverting input receives a third threshold voltage V. DD_ON A second activation signal S_ON1 is provided at the output terminal.

[0061] The reference voltage generation circuit 111 includes a reference capacitor C3, a reference voltage source Vref1, a reference resistor R3, and switches M1 and M2. The reference capacitor C3 has a first terminal and a second terminal, wherein the first terminal is coupled to the second input terminal of the error amplifier circuit 101A, and the second terminal is coupled to the secondary reference ground. The reference voltage source Vref1 has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the secondary reference ground. Switches M1 and M2 constitute a selection switch circuit, coupled to the secondary startup control circuit 110 to receive a second activation signal S_ON1. Based on the second activation signal S_ON1, the selection switch circuit selects whether to couple the first terminal of the reference capacitor C3 to the first input terminal of the error amplifier circuit 101A or to the positive terminal of the reference voltage source Vref1 via the reference resistor R3. In one embodiment, when the second activation signal S_ON1 is low, the reference voltage REF follows the output feedback signal VFB and gradually increases during startup. When the second activation signal S_ON1 is high, the reference voltage REF is disconnected from the output feedback pin FB and gradually increases to the first reference voltage Vref1 with a preset time constant.

[0062] Figure 11 This is a flowchart of a control method 700 for an isolated switching converter according to an embodiment of the present invention. The switching converter includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, a secondary switch coupled to the secondary winding, and a dual-channel isolation circuit. The control method includes steps 701 to 708.

[0063] In step 701, during startup, a gradually increasing current threshold voltage is provided. In one embodiment, the current threshold voltage gradually increases from a low threshold voltage to a high threshold voltage over a preset number of times during startup.

[0064] In step 702, an output feedback signal is generated based on the output signal of the switching converter.

[0065] In step 703, a first compensation signal is generated based on the difference between the output feedback signal and the reference voltage.

[0066] In step 704, a first control signal and a second control signal are generated based on the first compensation signal. In one embodiment, the method for generating the first control signal includes: generating a second compensation signal based on the first compensation signal; comparing the second compensation signal with a modulation signal to provide a first comparison signal; and providing the first control signal based on the first comparison signal. In a further embodiment, the method for generating the second control signal includes: comparing the first compensation signal with the modulation signal to generate a second comparison signal; and generating a target valley value for primary switch conduction based on the first comparison signal, the second comparison signal, and a valley pulse signal characterizing the valley of the voltage across the secondary switch, and providing a second control signal corresponding to the target valley value.

[0067] In step 705, the first and second control signals are respectively sent to the first and second channels of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal and a second synchronization signal electrically isolated from the second control signal.

[0068] In step 706, it is detected whether the secondary side is activated. In one embodiment, the secondary side is activated when the first pulse signal of the second synchronization signal is transmitted to the primary side via the isolation circuit. In another embodiment, the secondary side is activated when the secondary side supply voltage increases to a third threshold voltage.

[0069] In step 707, the startup process ends when the secondary side is activated, and a current threshold voltage is provided based on the first synchronization signal. In one embodiment, when the rising edge of the second synchronization signal arrives, the voltage across the first capacitor is set high to the upper limit threshold voltage. Afterward, the voltage across the first capacitor begins to decrease, and the voltage across the first capacitor is sampled and held when the first synchronization signal arrives to provide the current threshold voltage.

[0070] In step 708, the current detection signal representing the current flowing through the primary switch is compared with the current threshold voltage to generate a reset signal to turn off the primary switch.

[0071] In one embodiment, the control method 700 further includes: comparing a zero-crossing detection signal with a zero-crossing threshold voltage and outputting a zero-crossing signal at the output terminal; providing a set signal based on the zero-crossing signal to control the conduction of the primary switch during startup; and providing the set signal based on a second synchronization signal and the zero-crossing signal after startup. In another embodiment, after startup, when the second synchronization signal arrives and the resonant voltage across the primary switch reaches its minimum value, the primary switch is controlled to conduct.

[0072] In another embodiment, the control method 700 further includes: during startup, the reference voltage gradually increases following the output feedback signal; when the secondary side is activated, the startup process ends, and the reference voltage gradually increases to a first reference voltage.

[0073] In the specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such order, unless specifically specified in the language of the claims. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0074] The above description and embodiments are merely exemplary and are not intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit and scope of protection of this invention.

Claims

1. A controller for an isolated switching converter, the switching converter including a transformer, a primary switching transistor, and a secondary switching transistor, the controller comprising: An error amplifier circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives an output feedback signal related to the output signal of the switching converter, and the second input terminal receives a reference voltage. Based on the difference between the output feedback signal and the reference voltage, the error amplifier circuit generates a first compensation signal at the output terminal. The control signal generation circuit generates a first control signal and a second control signal at its output terminal based on the first compensation signal. The secondary startup control circuit compares the secondary-side power supply voltage with the threshold voltage, and provides a second activation signal at the output terminal based on the comparison result, which characterizes whether the secondary side is activated. The reference voltage generation circuit includes: A reference capacitor has a first terminal and a second terminal, wherein the first terminal is coupled to the second input terminal of an error amplifier circuit, and the second terminal is coupled to a secondary reference ground; A reference voltage source has a positive terminal and a negative terminal, wherein the negative terminal is coupled to a secondary reference ground; and The selection switch circuit is coupled to the secondary startup control circuit to receive the second activation signal. Based on the second activation signal, the selection switch circuit selects whether to couple the first end of the reference capacitor to the first input terminal of the error amplifier circuit or to the positive terminal of the reference voltage source via the reference resistor. An isolation circuit has a first channel for transmitting a first control signal and a second channel for transmitting a second control signal, provides a first synchronization signal electrically isolated from the first control signal at a first output terminal, and provides a second synchronization signal electrically isolated from the second control signal at a second output terminal; The reset signal generation circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a current detection signal representing the current flowing through the primary switch transistor, and the second input terminal receives a current threshold voltage. The reset signal generation circuit compares the current detection signal with the current threshold voltage and generates a reset signal at the output terminal to control the turn-off of the primary switch transistor. A threshold generation circuit provides the current threshold voltage at its output terminal. The threshold generation circuit includes: A startup threshold generation circuit provides a gradually increasing current threshold voltage during startup; and The normal threshold generation circuit ends the startup process when the secondary side is activated, and provides the current threshold voltage based on the first synchronization signal.

2. The controller of claim 1, further comprising: The start control unit is coupled to the second output of the isolation circuit to receive the second synchronization signal, wherein the start control unit detects whether the secondary side is activated based on the second synchronization signal and provides an activation signal at the output.

3. The controller of claim 2, wherein the start-up control unit comprises: The undervoltage latch circuit is coupled to the power supply capacitor to receive the primary power supply voltage. The undervoltage latch circuit compares the primary power supply voltage with the first power supply threshold voltage and the second power supply threshold voltage to generate an undervoltage latch signal. as well as The startup circuit has a first input terminal, a second input terminal, an output terminal, and an inverting output terminal. The first input terminal is coupled to an undervoltage latch circuit to receive an undervoltage latch signal, and the second input terminal is coupled to the output terminal of an isolation circuit to receive a second synchronization signal. Based on the undervoltage latch signal and the second synchronization signal, the startup circuit provides a startup signal at the output terminal indicating the start of the startup process and an activation signal at the inverting output terminal indicating the end of the startup process.

4. The controller of claim 1, further comprising: The zero-crossing comparator circuit compares the zero-crossing detection signal with the zero-crossing threshold voltage and provides a zero-crossing signal at the output. The set signal generation circuit provides a set signal at the output terminal, wherein the set signal is generated based on the zero-crossing signal during the startup process, and the set signal is generated based on the second synchronization signal and the zero-crossing signal after the startup process ends; as well as The primary logic circuit generates primary control signals for the primary switching transistor based on the set and reset signals to control the primary switching transistor.

5. The controller as claimed in claim 1, wherein during startup, the current threshold voltage gradually increases from a low threshold voltage to a high threshold voltage after a preset number of times.

6. The controller of claim 1, wherein the normal threshold generation circuit comprises: The timing circuit has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the isolation circuit to receive a second synchronization signal, the timing circuit performs timing based on the second synchronization signal, and generates a timing signal at the output terminal; The first flip-flop has a first input terminal, a second input terminal, an output terminal, and an inverting output terminal, wherein the first input terminal is coupled to the second output terminal of the isolation circuit to receive a second synchronization signal, and the second input terminal is coupled to the output terminal of the timing circuit to receive a timing signal; A first capacitor has a first terminal and a second terminal, wherein the second terminal is coupled to a primary reference ground; A first voltage source has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; The second voltage source has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; The first switching transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor, the second terminal is coupled to the positive terminal of the first voltage source, and the control terminal is coupled to the output terminal of the first flip-flop. The second switching transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor, the second terminal is coupled to the positive terminal of the second voltage source via a first resistor, and the control terminal is coupled to the inverting output terminal of the first flip-flop. as well as The sample-and-hold circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first output terminal of the isolation circuit to receive a first synchronization signal, and the second input terminal is coupled to the first terminal of the first capacitor to receive the voltage across the first capacitor. The sample-and-hold circuit samples and holds the voltage across the first capacitor based on the first synchronization signal and generates a current threshold voltage at the output terminal.

7. The controller as claimed in claim 1, wherein the reference voltage gradually increases following the output feedback signal during startup, and after the startup process ends, the reference voltage gradually increases to a first reference voltage.

8. An isolated switching converter, comprising: A transformer has a primary winding and a secondary winding; The primary switching transistor is coupled to the primary winding. The secondary switch is coupled to the secondary winding; as well as The controller as described in any one of claims 1 to 7.

9. A control method for an isolated switching converter, wherein the switching converter... The converter includes a transformer, a primary switching transistor, and an isolation circuit. The control method includes: During startup, a gradually increasing current threshold voltage is provided; An output feedback signal is generated based on the output signal of the switching converter; A first compensation signal is generated based on the difference between the output feedback signal and the reference voltage; Based on the first compensation signal, a first control signal and a second control signal are generated respectively; The first control signal is sent into the first channel of the isolation circuit to generate a first synchronization signal that is electrically isolated from the first control signal. The second control signal is sent into the second channel of the isolation circuit to generate a second synchronization signal that is electrically isolated from the second control signal. The secondary side is activated when the supply voltage to the secondary side increases to the third threshold voltage. Before the secondary side is activated, the reference voltage gradually increases following the output feedback signal. After the secondary side is activated, the reference voltage gradually increases to the first reference voltage. The startup process ends when the secondary side is activated, and the current threshold voltage is provided based on the first synchronization signal; as well as The current detection signal, representing the current flowing through the primary switch, is compared with the current threshold voltage to generate a reset signal to turn off the primary switch.

10. The control method of claim 9, wherein during the startup process, the current threshold voltage gradually increases from a low threshold voltage to a high threshold voltage after a preset number of times.

11. The control method of claim 9, wherein the method of providing a current threshold voltage when the startup process ends includes: When the second synchronization signal arrives, the voltage across the first capacitor is charged to the upper threshold voltage. Discharge the first capacitor; as well as When the first synchronization signal arrives, the voltage across the first capacitor is sampled and held to provide the current threshold voltage.

12. The control method as described in claim 9, further comprising: The zero-crossing detection signal is compared with the zero-crossing threshold voltage, and the zero-crossing signal is output at the output terminal. During startup, a set signal is provided based on the zero-crossing signal to control the conduction of the primary switching transistor; as well as The set signal is provided based on the second synchronization signal and the zero-crossing signal after the startup process is completed.

13. The control method of claim 9, wherein the secondary side is activated when the first pulse signal of the second synchronization signal is transmitted to the primary side via the isolation circuit.

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