Resonant clock system and chip

Abstract

This application provides a resonant clock system and chip, including: a pulse generation module and a clock tree transmission module connected together; the pulse generation module includes a resonant circuit, and is used to generate a pulse signal based on the resonant circuit according to an acquired initial clock signal, the width of the pulse signal being related to the resonant frequency of the resonant circuit; the clock tree transmission module includes multiple cascaded signal transmission units, each signal transmission unit including a connected inverter and a first inductor; the clock tree transmission module is used to transmit the pulse signal; wherein, the resonant frequency of the clock tree transmission module is the same as the resonant frequency of the resonant circuit. The resonant clock system of this application generates a pulse signal with a width related to the resonant frequency of the resonant circuit based on an initial clock signal through the resonant circuit in the pulse generation module, and transmits the pulse signal through the clock tree transmission module.

Description

Technical Field

[0001] This application relates to circuit technology, and more particularly to a resonant clock system and chip. Background Technology

[0002] Resonant clock circuits can effectively reduce the power consumption of the global clock, and this has been widely proven in existing designs.

[0003] In traditional resonant clock circuits, the resonant frequency is related to the clock frequency, and power consumption and performance optimization can only be achieved at a specific resonant frequency point. However, when a chip is working, its operating frequency may dynamically adjust within a preset frequency range depending on the operating state, and it may not necessarily operate continuously at a specific resonant frequency. The reason for this change in the chip's operating frequency may be due to user-controlled frequency variations or frequency variations caused by clock frequency offsets.

[0004] If the clock frequency deviates significantly, the resonant frequency of the resonant circuit will conflict with the clock frequency, thereby reducing system performance. Summary of the Invention

[0005] This application provides a resonant clock system and chip that can reduce power consumption during clock signal generation and transmission.

[0006] This application provides a resonant clock system, including: a pulse generation module and a clock tree transmission module connected together;

[0007] The pulse generation module includes a resonant circuit. The pulse generation module is used to generate a pulse signal based on the resonant circuit according to the acquired initial clock signal. The width of the pulse signal is related to the resonant frequency of the resonant circuit.

[0008] The clock tree transmission module includes multiple cascaded signal transmission units, each of which includes a connected inverter and a first inductor; the clock tree transmission module is used to transmit the pulse signal.

[0009] The resonant frequency of the clock tree transmission module is the same as the resonant frequency of the resonant circuit.

[0010] Optionally, the system may also include a power supply terminal;

[0011] The pulse generation module is specifically used for:

[0012] After the initial clock signal received at the total input terminal of the pulse generation module has a rising edge, the resonant circuit is controlled to oscillate and discharge, so that the voltage at the total output terminal of the pulse generation module oscillates and changes.

[0013] After the voltage at the total output terminal increases from low to high and reaches a preset voltage value, the oscillation discharge of the resonant circuit is cut off, and the capacitor in the resonant circuit is charged by the power supply terminal to increase the voltage at the total output terminal.

[0014] Optionally, the pulse generation module further includes: a switch control circuit, a logic control circuit, and a first master control terminal;

[0015] The logic control circuit is configured to, after the rising edge of the initial clock signal received at the total input terminal occurs, control the signal at the first total control terminal to become high after a first preset time delay, so as to control the resonant circuit to oscillate and discharge; and

[0016] After the voltage at the total output terminal changes from low to high and reaches a preset voltage value, the signal at the first total control terminal is controlled to become low, cutting off the oscillation discharge of the resonant circuit, and the capacitor in the resonant circuit is charged by the power supply terminal.

[0017] The switch control circuit is used to control the resonant circuit to oscillate and discharge according to the signal change of the first general control terminal, or to control the power supply terminal to charge the capacitor in the resonant circuit.

[0018] Optionally, the logic control circuit includes: AND gates, NAND gates, multiple delay units, and an even number of inverters;

[0019] The total input terminal is connected to the first input terminal of the NAND gate through multiple delay units; the total output terminal is connected to the second input terminal of the NAND gate through an even number of inverters; the output terminal of the NAND gate is connected to the first input terminal of the AND gate, the total input terminal is connected to the second input terminal of the AND gate; and the output terminal of the AND gate is connected to the first total control terminal.

[0020] Optionally, the switch control circuit includes: a first transistor, a second transistor, a pull-up switch, and a pull-down switch;

[0021] The first terminal of the first transistor is connected to the power supply terminal, and the second terminal is connected to both the first terminal of the second transistor and the total output terminal. The control terminal of the first transistor is connected to the total input terminal. The second terminal of the second transistor is connected to one end of the second inductor in the resonant circuit, and the control terminal of the second transistor is connected to the total input terminal. The first terminal of the pull-down switch is connected to the other end of the second inductor, and the control terminal of the pull-down switch is connected to the first total control terminal. The first terminal of the pull-up switch is connected to the power supply terminal, and the second terminal is connected to the total output terminal. The control terminal of the pull-up switch is connected to the first total control terminal.

[0022] Optionally, the switch control circuit further includes: a third transistor;

[0023] The first terminal of the third transistor is connected to the total output terminal, the second terminal of the third transistor is connected to the second terminal of the second transistor, and the control terminal of the third transistor is used to receive the reverse signal of the first total control terminal.

[0024] Optionally, the system may also include a power supply terminal;

[0025] The pulse generation module is specifically used for:

[0026] After the initial clock signal received at the total input terminal of the pulse generation module has a falling edge, the resonant circuit is controlled to oscillate and discharge, so that the voltage at the total output terminal of the pulse generation module oscillates and changes.

[0027] After the voltage at the total output terminal increases from low to high and reaches a preset voltage value, the oscillation discharge of the resonant circuit is cut off, and the capacitor in the resonant circuit is charged by the power supply terminal to increase the voltage at the total output terminal.

[0028] Optionally, the pulse generation module includes: a control circuit, a drive circuit, a feedback circuit, and a second main control terminal;

[0029] The control circuit and drive circuit are configured to control the resonant circuit to oscillate and discharge after a falling edge appears in the initial clock signal received at the total input terminal; and

[0030] The feedback circuit is used to control the signal at the second total control terminal to become high level after the voltage at the total output terminal changes from low to high and reaches a preset voltage value.

[0031] The control circuit and drive circuit are also used to receive a high-level signal from the second general control terminal, cut off the oscillation discharge of the resonant circuit, and charge the capacitor in the resonant circuit by the power supply terminal.

[0032] Optionally, the control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

[0033] Wherein, the first terminal of the eighth transistor is connected to the power supply terminal, and the second terminal is connected to the first terminal of the ninth transistor; the control terminal of the eighth transistor is connected to the total input terminal and the control terminal of the tenth transistor; the second terminal of the ninth transistor is connected to the first terminal of the tenth transistor, the first terminal of the eleventh transistor, and the output terminal of the control circuit; the control terminal of the ninth transistor is connected to the second total control terminal; the second terminal of the tenth transistor is grounded; the second terminal of the eleventh transistor is grounded; and the control terminal of the eleventh transistor is connected to the second total control terminal.

[0034] Optionally, the driving circuit includes: a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;

[0035] The first terminal of the twelfth transistor is connected to the power supply terminal, and the second terminal is connected to the first terminal of the thirteenth transistor, the first terminal of the fourteenth transistor, and the total output terminal of the pulse generation module. The control terminal of the twelfth transistor is connected to the output terminal of the control circuit and the control terminal of the thirteenth transistor. The second terminal of the thirteenth transistor is connected to one end of the third inductor in the resonant circuit and the second terminal of the fourteenth transistor. The control terminal of the fourteenth transistor is connected to the output terminal of the control circuit.

[0036] Optionally, the feedback circuit includes: a first inverter, a NOR gate, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

[0037] The input terminal of the first inverter is connected to the output terminal of the driving circuit, and the output terminal of the first inverter is connected to the control terminal of the sixteenth transistor and the first input terminal of the NOR gate; the first terminal of the sixteenth transistor is connected to the first terminal of the fifteenth transistor, the first terminal of the seventeenth transistor, the control terminal of the seventeenth transistor, and the second input terminal of the NOR gate; the control terminal of the fifteenth transistor is connected to the total input terminal; and the output terminal of the NOR gate is connected to the second total control terminal.

[0038] Optionally, the signal transmission unit includes two-stage inverters and a first inductor;

[0039] In this configuration, the first terminal of the first-stage inverter is connected to the power supply terminal, the second terminal of the first-stage inverter is connected to ground, and the control terminal of the first-stage inverter is connected to the total output terminal of the previous signal transmission unit or the pulse generation module; the first terminal of the second-stage inverter is connected to the power supply terminal, the second terminal of the second-stage inverter is connected to ground through the first inductor, and the control terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter; the output terminal of the second-stage inverter is connected to the input terminal of the next signal transmission unit or the load.

[0040] Optionally, the first-stage inverter includes a fourth transistor and a fifth transistor;

[0041] The first terminal of the fourth transistor is connected to the power supply terminal, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the control terminal of the second-stage inverter, and the control terminal of the fourth transistor is connected to the total output terminal of the previous signal transmission unit or the pulse generation module; the second terminal of the fifth transistor is connected to ground, and the control terminal of the fifth transistor is connected to the total output terminal of the previous signal transmission unit or the pulse generation module.

[0042] The second-stage inverter includes a sixth transistor and a seventh transistor;

[0043] The first terminal of the sixth transistor is connected to the power supply terminal, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor and the input terminal of the next signal transmission unit or load, and the control terminal of the sixth transistor is connected to the output terminal of the first-stage inverter; the second terminal of the seventh transistor is connected to ground through the first inductor, and the control terminal of the seventh transistor is connected to the output terminal of the first-stage inverter.

[0044] Optionally, the resonant clock system further includes:

[0045] A clock raw output module, connected to the pulse generation module, is used to generate an initial clock signal and send it to the pulse generation module;

[0046] And / or,

[0047] The load module, connected to the clock tree transmission module, is used to process data based on the signal output by the clock tree transmission module.

[0048] Optionally, the resonant clock system further includes: a signal shaping circuit;

[0049] The load module and the clock tree transmission module are connected via the signal shaping circuit;

[0050] The signal shaping circuit is used to shape the signal output by the clock tree transmission module into a square wave signal with a preset duty cycle and send it to the load module.

[0051] This application also provides a chip, including: a resonant clock system as described above.

[0052] This application provides a resonant clock system, including: a pulse generation module and a clock tree transmission module connected together; the pulse generation module includes a resonant circuit, and is used to generate a pulse signal based on the resonant circuit according to an acquired initial clock signal, the width of the pulse signal being related to the resonant frequency of the resonant circuit; the clock tree transmission module includes multiple cascaded signal transmission units, each signal transmission unit including a connected inverter and a first inductor; the clock tree transmission module is used to transmit the pulse signal; wherein, the resonant frequency of the clock tree transmission module is the same as the resonant frequency of the resonant circuit. The resonant clock system of this application generates a pulse signal based on the initial clock signal through the resonant circuit in the pulse generation module, the frequency of which is related to the frequency of the initial clock signal, and the width of which is related to the resonant frequency of the resonant circuit, and transmits the pulse signal through the clock tree transmission module; that is, regardless of how the frequency of the initial clock signal changes, the pulse signal generated by the pulse generation module after the initial clock signal passes through is a signal of fixed width, the pulse width being related to the resonant frequency of the resonant circuit; by combining this fixed-width pulse signal, the resonant frequency of the clock tree transmission module can be matched with the width of this pulse signal to achieve normal operation of the chip, without needing to consider the actual frequency of the current initial clock signal. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A schematic diagram illustrating one application scenario provided in this application;

[0055] Figure 2 A schematic diagram of a resonant clock system provided in one embodiment of this application;

[0056] Figure 3 A circuit diagram of a pulse generation module provided in one embodiment of this application;

[0057] Figure 4 An embodiment of this application provides a Figure 3 The timing diagram of the corresponding circuit;

[0058] Figure 5 A timing waveform diagram of each node in a logic control circuit provided in an embodiment of this application;

[0059] Figure 6 A circuit diagram of a clock tree transmission module provided in one embodiment of this application;

[0060] Figure 7 An embodiment of this application provides a Figure 6 The timing diagram of the corresponding circuit;

[0061] Figure 8 A circuit diagram of another pulse generation module provided in one embodiment of this application;

[0062] Figure 9 An embodiment of this application provides a Figure 8 The timing diagram of the corresponding circuit;

[0063] Figure 10 This is a schematic diagram of another resonant clock system provided in an embodiment of this application. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] The operating frequency of a chip is not fixed and will dynamically adjust within a preset frequency range depending on the operating state. However, due to the limitations of its principle, the resonant clock circuit can only optimize power consumption and performance at specific resonant frequency points. At other frequency points, it will increase the chip's power consumption and damage the signal quality.

[0066] Meanwhile, for traditional resonant circuits composed of inductors and capacitors, the optimal resonant operating point calculated during the design phase may experience unknown fluctuations due to phenomena such as silicon manufacturing offsets and on-chip signal interference, making it difficult for the chip to achieve the optimal operating state in the design during use.

[0067] In some solutions, a multi-inductor parallel circuit structure is used in the chip to expand the resonant frequency point of the resonant circuit. During operation, the resonant frequency point is dynamically adjusted by selecting the number of inductor branches or the size of the inductors to adapt to the chip's current operating state. The specific number and type of branches can be freely switched according to the chip's circuit mode. However, designing a high-quality inductor on a chip often consumes significant design resources, commonly involving high-level wiring resources, which can lead to resource competition with the power and ground designs in digital chips. The aforementioned parallel inductor method undoubtedly introduces more inductors, meaning that more inductor resources are needed during implementation, increasing the overall chip manufacturing cost and convergence difficulty. The number of inductors that can be connected in parallel on a chip is limited, and the resonant frequency point of the resonant circuit is a set of several fixed values ​​under various connection conditions. When the chip operates at frequencies outside this set, it still cannot achieve optimal power consumption optimization, only operating in a relatively optimal state, and cannot fully utilize the inductor's capabilities.

[0068] Therefore, this application proposes a resonant clock circuit that can adapt to frequency and voltage changes and has a certain anti-interference capability.

[0069] Figure 1 This is a schematic diagram illustrating one application scenario provided by this application. For example... Figure 1 As shown, the clock source generates an initial clock signal, which can be converted into a pulse signal and transmitted to each load through the resonant clock system provided in this application.

[0070] The specific structure and function of the resonant clock system can be found in the following embodiments.

[0071] Figure 2 This is a schematic diagram of the structure of a resonant clock system provided in an embodiment of this application, as shown below. Figure 2 As shown, the resonant clock system provided in this embodiment includes a pulse generation module 201 and a clock tree transmission module 202 connected to each other. The pulse generation module 201 includes a resonant circuit 203, which generates a pulse signal based on the acquired initial clock signal. The width of the pulse signal is related to the resonant frequency of the resonant circuit 203. The clock tree transmission module 202 includes multiple cascaded signal transmission units 204, each including a connected inverter 205 and a first inductor 206. The clock tree transmission module 202 transmits the pulse signal generated by the pulse generation module 201. The resonant frequency of the clock tree transmission module 202 is the same as the resonant frequency of the resonant circuit 203.

[0072] The resonant clock system in this embodiment generates a pulse signal with a width related to the resonant frequency of the resonant circuit based on the initial clock signal through the resonant circuit in the pulse generation module, and then transmits the pulse signal through the clock tree transmission module. That is, regardless of how the frequency of the initial clock signal changes, the signal generated by the pulse generation module after passing through the initial clock signal is always a pulse of fixed width. As long as the resonant frequency of the clock tree transmission module matches the width of this pulse signal, the chip can operate normally without considering the actual frequency of the initial clock signal. Furthermore, the inverter and the first inductor in the clock tree transmission module are connected; the inductor assists the clock tree transmission module in charging and discharging, optimizing the power consumption of the clock tree transmission module and further reducing power loss during pulse signal transmission.

[0073] Since the pulse generation module 201 essentially generates a pulse signal at the edge (rising or falling edge) of the initial clock signal, the frequency of this pulse signal must be the same as the frequency of the initial clock signal. And since the pulse signal is generated based on the resonant circuit 203, the width of the pulse signal must be related to the resonant frequency of the resonant circuit 203. Therefore, changes in the frequency of the initial clock signal will only affect the frequency of the pulse signal, not its width. To transmit the pulse signal to the various loads in the chip, it is only necessary to ensure that the resonant frequency of the clock tree transmission module 202 is the same as the resonant frequency of the resonant circuit 203; that is, the resonant frequency of the clock tree transmission module 202 is related to the width of the pulse signal, thus minimizing transmission losses.

[0074] However, it is important to note that the width of the designed pulse signal must be less than the minimum possible operating cycle of the chip, that is, enough time to generate a pulse signal in half a clock cycle.

[0075] The width of the pulse signal is related to the resonant frequency of the resonant circuit 203. The resonant frequency of the clock tree transmission module 202 is the same as the resonant frequency of the resonant circuit 203. These two conditions can be achieved based on a specific circuit structure. For specific implementation methods, please refer to the following embodiments.

[0076] In some embodiments, the resonant clock system includes a power supply terminal. Specifically, the pulse generation module 201 can be used to: control the resonant circuit 203 to oscillate and discharge after the rising edge of the initial clock signal received at the total input terminal of the pulse generation module 201 occurs, so that the voltage at the total output terminal of the pulse generation module 201 oscillates and changes; after the voltage at the total output terminal of the pulse generation module 201 changes from low to high and reaches a preset voltage value, cut off the oscillation and discharge of the resonant circuit 203, and charge the capacitor in the resonant circuit 203 from the power supply terminal of the resonant clock system to increase the voltage at the total output terminal. The preset voltage value can be set according to actual needs.

[0077] The power supply terminal of the resonant clock system provides a stable voltage for the entire system, enabling all components in the resonant clock system to operate normally.

[0078] Since the process of the resonant circuit 203 discharging and generating a pulse signal is triggered at the rising edge of the initial clock signal, the occurrence time of the pulse signal can characterize the occurrence time of the rising edge of the initial clock signal. This is equivalent to retaining the rising edge information of the initial clock signal and propagating it to each load in the resonant clock system in the form of a pulse signal.

[0079] According to the characteristics of the resonant circuit 203, due to the presence of parasitic resistance in the circuit, the maximum rebound voltage that the oscillation signal can reach in the first oscillation cycle will definitely not reach the voltage value of the resonant clock system. At this time, the oscillation process is cut off, and a full-swing signal waveform cannot be obtained. Therefore, by charging the power supply terminal, the voltage of the total output terminal is pulled to the high level required by the resonant clock system, and a complete full-swing pulse signal can be obtained.

[0080] refer to Figure 3 To achieve the function of the resonant circuit 203 oscillating and discharging at the rising edge in the above embodiment, the structure of the pulse generation module 201 may further include: a switch control circuit 301, a logic control circuit 302, and a first general control terminal 303. The switch control circuit 301 is connected to the logic control circuit 302 and the first general control terminal 303, respectively.

[0081] Specifically, the initial clock signal CLK is input to the switch control circuit 301 through the first input terminal (i.e., the total input terminal of the pulse generation module 201) and the logic control circuit 302 through the first input terminal. The output signal out of the switch control circuit 301 (i.e., the total output terminal of the pulse generation module 201) is input to the logic control circuit 302 through the second input terminal. The output terminal of the logic control circuit 302 is the first total control terminal 303. The output control signal CH is input to the switch control circuit 301 through the second input terminal.

[0082] The logic control circuit 302 is used to control the signal CH of the first general control terminal 303 to become high after a first preset time following the rising edge of the initial clock signal CLK input to its first input terminal. This high level is then input to the switch control circuit 301 to control the resonant circuit 203 to oscillate and discharge through the output terminal of the switch control circuit 301. After the voltage of the output signal out changes from low to high and reaches a preset voltage value, the signal CH of the first general control terminal 303 is controlled to become low, cutting off the oscillation and discharge of the resonant circuit 203, and the capacitor in the resonant circuit 203 is charged by the power supply terminal. The switch control circuit 301 is used to control the oscillation and discharge of the resonant circuit 203, or to control the power supply terminal to charge the capacitor in the resonant circuit 203.

[0083] Optionally, after the initial clock signal CLK is input to the logic control circuit 302, under the action of the logic devices in the logic control circuit 302, CH is finally output at the output terminal of the logic control circuit 302. The aforementioned logic devices will cause a signal delay of a first preset time. The first preset time of delay is determined by the specific circuit structure and device selection, and the actual duration is relatively small.

[0084] The main function of the entire resonant circuit 203 is to generate a low-level pulse signal at the rising edge of the initial clock signal, which is determined by the resonant frequency of the resonant circuit composed of the series inductor and the load capacitor.

[0085] Still referencing Figure 3 In the pulse generation module 201, the logic control circuit 302 includes: an AND gate, a NAND gate, multiple delay units, and an even number of inverters. The delay units are labeled D, and the inverters are labeled E. Specifically, the total input terminal 401 of the pulse generation module 201 is connected to the first input terminal of the NAND gate through multiple delay units D; the total output terminal 402 of the pulse generation module 201 is connected to the second input terminal of the NAND gate through an even number of inverters E; the output terminal of the NAND gate is connected to the first input terminal of the AND gate, and the total input terminal 401 of the pulse generation module 201 is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the first total control terminal 303.

[0086] The switch control circuit 301 includes: a first transistor Q1, a second transistor Q2, a pull-up switch Q3, and a pull-down switch Q4; the first terminal of the first transistor Q1 is connected to the power supply terminal Vdd, the second terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2 and the total output terminal 402, and the control terminal of the first transistor Q1 is connected to the total input terminal 401; the second terminal of the second transistor Q2 is connected to one end of the second inductor L in the resonant circuit 203, and the control terminal of the second transistor Q2 is connected to the total input terminal 401; the first terminal of the pull-down switch Q4 is connected to the other end of the second inductor L, the control terminal of the pull-down switch Q4 is connected to the first total control terminal 303, and the second terminal of the pull-down switch Q4 is grounded; the first terminal of the pull-up switch Q3 is connected to the power supply terminal Vdd, the second terminal of the pull-up switch Q3 is connected to the total output terminal 402, and the control terminal of the pull-up switch Q3 is connected to the first total control terminal 303, receiving the reverse signal of the control signal from the first total control terminal 303. The equivalent capacitance C of the circuit is also shown in the figure. One end of the equivalent capacitance C is connected to the total output terminal 402, and the other end is grounded.

[0087] In this configuration, the first transistor Q1 can be a P-type field-effect transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate; the second transistor Q2 can be an N-type field-effect transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate; the pull-up switch Q3 can be a P-type field-effect transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate; and the pull-down switch Q4 can be an N-type field-effect transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate.

[0088] In this embodiment of the invention, the input signal (i.e., the initial clock signal) CLK of the total input terminal 401 of the pulse generation module 201 and the output signal out of the total output terminal 402 are equivalent to the input of the logic control circuit 302, and the output signal of the logic control circuit 302 is the control signal CH of the first total control terminal 303.

[0089] Figure 4 Provided for this application Figure 3 The timing waveform diagram of the corresponding circuit. (Reference) Figure 4 When the input signal CLK is low, the first transistor Q1 is turned on, and the output signal out is precharged to a high level. When the input signal CLK becomes high, the first transistor Q1 is turned off, and the second transistor Q2 is turned on. At this time, the control signal CH at the first master control terminal is high, the pull-down switch is turned on, and the load capacitor C and the second inductor L form a resonant circuit. If the system parameters can satisfy the following formula at this time, an oscillating electrical signal will be generated at the output terminal.

[0090]

[0091] Where R is the equivalent resistance in the pulse generation module 201 at this time, including the on-resistance of the second transistor Q2, parasitic resistances such as line resistance, and the on-resistance of the pull-down switch Q4; l is the effective inductance value of the inductor L; c is the equivalent capacitance of the system, including the parasitic capacitance of the second transistor Q2, the parasitic capacitance of the pull-down switch Q4, line capacitance, and load capacitance.

[0092] Assuming the control signal CH of the first master control terminal 303 is always high, ensuring that the pull-down switch Q4 is always on, the resonant clock system will be in an oscillating discharge state. If the second terminal of the pull-down switch Q4 is grounded, the output signal can be expressed by the following formula:

[0093]

[0094]

[0095] Among them, u out The output signal voltage at the total output terminal; V dd ω is the power supply terminal voltage; ω0 is the resonant angular frequency; ω is the natural oscillation angular frequency; β is the resonant phase angle; δ is the attenuation coefficient. That is, the circuit in... Under the envelope, oscillating discharge at angular frequency ω, the waveform of the output signal out at the total output terminal will be as follows: Figure 4 As shown by line ① in the diagram.

[0096] refer to Figure 4 The waveform corresponding to CH, the actual output waveform of out, and line ② Figure 5The waveforms of each node in the corresponding logic control circuit 302, and the actual working process of the control signal CH, are explained as follows: When the input signal CLK is low, CH is low. At this time, the pull-up switch Q3 is open, which can provide auxiliary charging function and optimize signal quality. When the input signal CLK becomes high, since the signal at node inD (the node where the input signal CLK is connected to the NAND gate) is obtained after a certain delay based on CLK, the signal at node inD is still low for a short time. At this time, node C0 (the output node of the NAND gate) is high. Since the input terminals of the last stage AND gate are all 1 at this time, CH is pulled up to a high level, and the pull-down switch Q4 is opened, cooperating with the second crystal. The output terminal of transistor Q2 forms a resonant path with the second inductor L. When the high level of the input signal CLK reaches node inD after a certain delay, the output terminal has already discharged and becomes low, while node C0 remains high, and the circuit path remains unchanged. When the level of the output signal out gradually rises under the action of resonance and exceeds the sampling level of the first inverter connected to the output signal out, node outD (the node where the output signal out is connected to the NAND gate) obtains a high level, node C0 becomes low, and the control signal CH becomes low under the action of the AND gate. At this time, the pull-down switch Q4 is turned off, the resonant path is broken, and the pull-up switch Q3 is turned on, continuing to charge capacitor C.

[0097] The function of the control signal CH is to cut off the oscillation discharge of the resonant circuit when the level of the total output terminal rises to a certain level, while simultaneously helping the total output terminal to continuously charge to the system voltage of the resonant clock system. A low-level pulse signal, determined by the resonant frequency of the resonant circuit composed of the series inductor and load capacitor, is generated at the rising edge of the initial clock signal.

[0098] Based on the above process, it can be seen that in order to ensure that when the high level of the input signal CLK is transmitted to inD, the output signal out of the total output terminal 402 has already completed a partial discharge. The level of the out signal is lower than the threshold voltage of the first inverter into which the out signal is input, and the out signal has not bounced above the threshold voltage of the first inverter. Therefore, the delay chain time between the signal at the inD node and the input signal CLK needs to fall within the threshold voltage of the first inverter. Figure 5 Within the shaded area.

[0099] It is also known that, due to the presence of resistors (device on-resistance, line parasitic resistance, and parasitic resistance of inductor devices) in resonant circuit 203, the first-stage rebound voltage value of the resonance process (the voltage at the total output terminal reaches its peak value for the first time from low to high during the oscillation process, which is the first-stage rebound voltage of the oscillation discharge process) cannot reach the system voltage of the resonant clock system. Therefore, in order to ensure that the first inverter can successfully capture the rising oscillation signal, a low-threshold device can be used as a sampling device.

[0100] To ensure that the highest bounce level of the oscillation waveform output from the total output terminal is high enough, a bias voltage U can be connected to the second terminal of the pull-down switch Q4. s When the bias voltage U s When valid, the voltage of the output signal out can be expressed by the following formula:

[0101]

[0102]

[0103] The meaning of each parameter can be found in the description in the above embodiments.

[0104] In summary, after the above process, the total output terminal generates a low-level pulse signal at the rising edge of the initial clock signal, and the width of the low-level pulse signal is determined by the resonant frequency of the resonant circuit.

[0105] However, due to the "strong 0, strong 1" limitation of CMOS devices, the charging level at the total output terminal via the second transistor Q2 can only reach a maximum of V. dd -V T-MN (V T-MN (This refers to the threshold voltage of the second transistor Q2). To solve the above problem, the switch control circuit 301 may further include: a third transistor Q5; the first terminal of the third transistor Q5 is connected to the total output terminal, the second terminal of the third transistor Q5 is connected to the second terminal of the second transistor Q2, and the control terminal of the third transistor Q5 is used to receive the inverted signal from the first total control terminal. Specifically, Q5 can be a P-type field-effect transistor.

[0106] See Figure 3 As shown, since the inductor is connected to the ground terminal of transistor Q2, transistor Q2 is turned on when the input signal CLK is high. At this time, the circuit resistance is the on-resistance R of transistor Q2. on Line parasitic resistance R wire Parasitic resistance R of inductive devices ind The sum, i.e., R = R on +R wire +R ind ;

[0107] A complementary PMOS transistor Q5, controlled by an inverting clock signal, is connected in parallel with transistor Q2. When the input signal CLK is high, both transistors Q2 and Q5 are turned on simultaneously. At this time, R... on The resistance value is the result of connecting the on-resistances of transistors Q2 and Q5 in parallel. Compared to the method of connecting transistor Q5 in parallel with only transistor Q2, this reduces the on-resistance of the circuit, and the total output voltage is closer to the bias voltage U. sTherefore, by adding a complementary transistor, namely the third transistor Q5, the total output can benefit more effectively from the bias voltage U. s .

[0108] In the above embodiments, the pulse generation module enables the pulse signal width to be related to the resonant frequency of the resonant circuit; the correlation between the pulse signal width and the resonant frequency means that there is a certain functional relationship between the pulse signal width and the resonant frequency of the resonant circuit, as shown in the formula above. The clock tree transmission module can control its own resonant frequency to be the same as the resonant frequency of the resonant circuit.

[0109] In other embodiments, the pulse generation module 201 can be specifically used to: control the resonant circuit 203 to oscillate and discharge after the initial clock signal received at the total input terminal of the pulse generation module 201 has a falling edge, so that the voltage at the total output terminal of the pulse generation module 201 oscillates and changes; after the voltage at the total output terminal changes from low to high and reaches a preset voltage value, cut off the oscillation and discharge of the resonant circuit 203, and charge the capacitor in the resonant circuit 203 from the power supply terminal to increase the voltage at the total output terminal.

[0110] Similar to the principle of the pulse generation module 201 in the above embodiments, the difference is that the pulse generation module 201 in this embodiment causes the resonant circuit 203 to oscillate and discharge at the falling edge of the initial clock signal. This allows the falling edge information of the initial clock signal to be retained and propagated to each load in the resonant clock system. In the specific circuit implementation, one of the following can be selected to implement the pulse generation module 201.

[0111] refer to Figure 8 To achieve the aforementioned function of oscillating and discharging at the falling edge of the initial clock signal, the pulse generation module 201 may include a control circuit 801, a drive circuit 802, a feedback circuit 803, and a second total control terminal 804. The control circuit 801 and drive circuit 802 are used to control the resonant circuit 203 to oscillate and discharge after the falling edge of the initial clock signal at the total input terminal appears. Specifically, the control circuit 801 controls the drive circuit 802 to operate, so that the drive circuit 802 drives the resonant circuit 203 to oscillate and discharge. The feedback circuit 803 controls the signal at the second total control terminal 804 to become high-level after the voltage at the total output terminal changes from low to high and reaches a preset voltage value; the control circuit 801 and drive circuit 802 are also used to receive the high-level signal from the second total control terminal 804, cut off the oscillation and discharge of the resonant circuit 203, and charge the capacitor in the resonant circuit 203 from the power supply terminal.

[0112] The preset voltage value can be set according to actual needs. According to the characteristics of the resonant circuit 203, when the voltage at the total output terminal reaches its peak value for the first time from low to high, the total output terminal voltage is the first rebound voltage of the oscillation discharge process. This voltage value will definitely not reach the system voltage value of the resonant clock system, so the preset voltage value will definitely be less than the system voltage Vdd.

[0113] In this embodiment, the main function of the pulse generation module 201 is to cause the resonant circuit 203 to oscillate and discharge at the falling edge of the initial clock signal, that is, to generate a low-level pulse signal at the falling edge of the initial clock signal, which is determined by the resonant frequency of the resonant circuit 203 composed of a series inductor and a load capacitor.

[0114] Still referencing Figure 8 The control circuit 801 includes: an eighth transistor Q10, a ninth transistor Q11, a tenth transistor Q12, and an eleventh transistor Q13; wherein, the first terminal of the eighth transistor Q10 is connected to the power supply terminal Vdd, and the second terminal is connected to the first terminal of the ninth transistor Q11; the control terminal of the eighth transistor Q10 is connected to the total input terminal CLK and the control terminal of the tenth transistor Q12; the second terminal of the ninth transistor Q11 is connected to the first terminal of the tenth transistor Q12, the first terminal of the eleventh transistor Q13, and the output terminal of the control circuit 801; the control terminal of the ninth transistor Q11 is connected to the second total control terminal 804; the second terminal of the tenth transistor Q12 is grounded; the second terminal of the eleventh transistor Q13 is grounded; and the control terminal of the eleventh transistor Q13 is connected to the second total control terminal 804.

[0115] The driving circuit 802 includes: a twelfth transistor Q14, a thirteenth transistor Q15, and a fourteenth transistor Q16; the first terminal of the twelfth transistor Q14 is connected to the power supply terminal Vdd, and the second terminal is connected to the first terminal of the thirteenth transistor Q15, the first terminal of the fourteenth transistor Q16, and the total output terminal of the pulse generation module 201; the control terminal of the twelfth transistor Q14 is connected to the output terminal of the control circuit 801 and the control terminal of the thirteenth transistor Q15; the second terminal of the thirteenth transistor Q15 is connected to one end of the third inductor L7 in the resonant circuit 203 and the second terminal of the fourteenth transistor Q16; the control terminal of the fourteenth transistor Q16 is connected to the output terminal of the control circuit 801.

[0116] The feedback circuit 803 includes: a first inverter INV, a NOR gate D1, a fifteenth transistor Q17, a sixteenth transistor Q18, and a seventeenth transistor Q19; the input terminal of the first inverter is connected to the output terminal of the drive circuit 802, and the output terminal of the first inverter is connected to the control terminal of the sixteenth transistor Q18 and the first input terminal of the NOR gate D1; the first terminal of the sixteenth transistor Q18 is connected to the first terminal of the fifteenth transistor Q17, the first terminal of the seventeenth transistor Q19, the control terminal of the seventeenth transistor Q19, and the second input terminal of the NOR gate D1; the control terminal of the fifteenth transistor Q17 is connected to the total input terminal; and the output terminal of the NOR gate D1 is connected to the second total control terminal 804.

[0117] Among them, Q10, Q11, Q14, Q16, and Q19 can be P-type field-effect transistors, and Q12, Q13, Q15, Q17, and Q18 can be N-type field-effect transistors.

[0118] Figure 9 Provided for this application Figure 8 The timing waveform diagram of the corresponding circuit. (Reference) Figure 8 and Figure 9 When the initial clock signal CLK is in state p1, the initial clock signal CLK is high, and the output signal out_Pulse at the total output terminal is always high. At this time, the control signal CON at the second total control terminal is pre-charged to low level through the feedback circuit.

[0119] When the initial clock signal CLK is in state p2, it goes low. The output signal con_Pulse of the control circuit 801 is charged to a high level after passing through the pre-charged ninth transistor Q11 and the newly turned-on eighth transistor Q10. At this time, the thirteenth transistor Q15 of the drive circuit 802 turns on, and the third inductor L7 is connected to the circuit, entering the resonant mode. The above process takes time Dn3.

[0120] After half a resonant cycle π / ω, the output signal out_Pulse at the total output terminal drops to the lowest point of the resonant circuit voltage. This voltage is sufficient to invert the first inverter INV to a high level. This means that the sixteenth transistor Q18 in the feedback circuit 803 turns on, and the high level of the pre-charge at node c1 in the previous operating state is released. Thereafter, the voltage at node c1 is maintained at a low level through the seventeenth transistor Q19.

[0121] After this, after half a resonant period π / ω, theoretically after a specified delay (D) (res_Vth)After that, the voltage of the output signal out_Pulse at the total output terminal rises to the highest point of the resonant circuit voltage. However, before the voltage of the output signal out_Pulse rises to the highest point, it first reaches the threshold voltage V_th of the first inverter INV. Inverter INV then inverts again, and the signal inv_Pulse output by this inverter INV becomes low. At this time, both input terminals of D1 in the feedback circuit 803 are low, and its output control signal con becomes high (this step is delayed by D_feedback). The feedback process ends, and a pulse signal out_Pulse related to the oscillation frequency is successfully obtained.

[0122] When the initial clock signal CLK is in the p3 state: the control circuit 801 receives a high level con, the pull-up path of con_Pulse (the path formed by Q10 and Q11) is closed, and the pull-down path (the path formed by Q12 and Q13) is opened. Then the twelfth transistor Q14 of the drive circuit 802 is turned on, exiting the resonant mode. The voltage of the output signal out_Pulse is further pulled up from the highest value of the resonant circuit voltage to the level of the resonant clock system.

[0123] In summary, through the above process, the pulse generation module generates a low-level pulse signal at the falling edge of the initial clock signal, and the signal width is determined by the resonant frequency of the resonant circuit. The pulse generation module generates a specified pulse width through the resonant circuit, reusing the energy stored at the output terminal from the previous moment. Only a small amount of energy loss due to parasitic resistance needs to be compensated, thus effectively saving circuit power consumption. Simultaneously, compared to traditional circuits, the delay chain length is reduced, thereby reducing the energy loss of each delay stage.

[0124] Figure 6 A circuit diagram of a clock tree transmission module provided in one embodiment of this application is shown below. Figure 6 As shown, the signal transmission unit 204 includes two inverters 601 and 602 and a first inductor 206. The first terminal of the first inverter 601 is connected to the power supply terminal Vdd, the second terminal of the first inverter 601 is connected to ground, and the control terminal of the first inverter 601 is connected to the total output terminal of the previous signal transmission unit or pulse generation module. The first terminal of the second inverter 602 is connected to the power supply terminal, the second terminal of the second inverter 602 is connected to ground through the first inductor 206, the control terminal of the second inverter 602 is connected to the output terminal of the first inverter 601, and the output terminal of the second inverter 602 is connected to the input terminal of the next signal transmission unit or load.

[0125] For specific details, please refer to Figure 6The first-stage inverter 601 includes a fourth transistor Q6 and a fifth transistor Q7. The first terminal of the fourth transistor Q6 is connected to the power supply terminal, and the second terminal of the fourth transistor Q6 is connected to the first terminal of the fifth transistor Q7 and the control terminal of the second-stage inverter 602. The control terminal of the fourth transistor Q6 is connected to the total output terminal of the previous signal transmission unit or pulse generation module. The second terminal of the fifth transistor Q7 is connected to ground, and the control terminal of the fifth transistor Q7 is connected to the total output terminal of the previous signal transmission unit or pulse generation module. The second-stage inverter 602 includes a sixth transistor Q8 and a seventh transistor Q9. The first terminal of the sixth transistor Q8 is connected to the power supply terminal, and the second terminal of the sixth transistor Q8 is connected to the first terminal of the seventh transistor Q9 and the input terminal of the next signal transmission unit or load. The control terminal of the sixth transistor Q8 is connected to the output terminal of the first-stage inverter 601. The second terminal of the seventh transistor Q9 is connected to ground through the first inductor 206, and the control terminal of the seventh transistor Q9 is connected to the output terminal of the first-stage inverter 601.

[0126] The signal transmission unit 204 consists of an inverter with a small input capacitor and a resonant inverter with a large driving capability. The first-stage inverter 601 is constructed from small-sized components, ensuring a small input capacitor for the system. It also inverts and shapes the waveform of the pulse signal input from the pulse generation module, making the pulse width closer to the resonant width of the second-stage inverter 602. The second-stage inverter 602 has a first inductor 206 connected in series with the ground terminal. When the pull-down path formed by the seventh transistor Q9 and the first inductor 206 is opened, part of the electric field energy obtained at the output terminal of the second-stage inverter 602 in the previous moment is converted into the magnetic field energy of the first inductor 206. This magnetic field energy then feeds back to the output capacitor, causing the output voltage to first decrease and then increase. Due to unavoidable energy loss during this process, the inductor 206 can only help raise the output voltage by a portion. The subsequent charging process is carried out by the pull-up path opened under the control of node O. Figure 7 Provided for an embodiment of this application Figure 6 The timing diagram of the corresponding circuit.

[0127] By cascading the signal transmission units 204, the inductor 206 can assist the circuit in charging and discharging when driving a large load, optimizing circuit power consumption. In this way, each stage of the overall clock tree can achieve energy optimization. Since the entire clock tree propagates pulse signals, it is naturally suitable for circuits composed of latches.

[0128] Figure 10 This is a schematic diagram of another resonant clock system provided in an embodiment of this application. The resonant clock system provided in this embodiment may further include: a clock raw output module 101 and / or a load module 102.

[0129] The original clock output module 101 is connected to the pulse generation module 201 and is used to generate an initial clock signal and send it to the pulse generation module 201.

[0130] The load module 102 is connected to the clock tree transmission module 202 and is used to process data according to the signal output by the clock tree transmission module 202.

[0131] Referring to the above embodiments, when the pulse generation module 201 adopts... Figure 3 In the corresponding circuit structure, the out signal output from the total output terminal 402 is input to the clock tree transmission module 202; when the pulse generation module 201 adopts... Figure 8 In the corresponding circuit structure, the out_Pulse signal output from the total output terminal of the drive circuit 802 is input to the clock tree transmission module 202.

[0132] When the load is a trigger or a timing device or other device that has strict requirements for the clock duty cycle (commonly 50%), the resonant clock system also includes: a signal shaping circuit 103; the load module 102 and the clock tree transmission module 202 are connected through the signal shaping circuit 103; the signal shaping circuit 103 is used to shape the signal output by the clock tree transmission module 202 into a square wave signal with a preset duty cycle and send it to the load module 102.

[0133] The technical solution of this application can optimize the power consumption of the pulse generation circuit. Specifically, the pulse generation module generates a specified pulse width through a resonant circuit, reusing the energy stored at the output terminal from the previous moment. Only a small amount of energy loss due to parasitic resistance needs to be compensated, thus effectively saving circuit power consumption. Simultaneously, compared to traditional circuits, the resonant clock system provided in this embodiment reduces the delay chain length, thereby reducing the energy loss at each delay stage. Furthermore, each stage in the clock tree transmission module can achieve power consumption optimization, with an optimization capability exceeding 30%. Therefore, with the combined effect of the above two units, the power consumption of the global clock tree can be significantly optimized globally.

[0134] The technical solution of this application can be adapted to any frequency. Since the pulse signal for the clock tree operation is determined by the pulse generation module, as long as the circuit's operating period is greater than the minimum pulse width that the pulse generation module can generate, the circuit can operate normally without changing the system inductance value and achieve maximum power consumption optimization.

[0135] The technical solution presented in this application can effectively reduce the inductance value required by the system. Since the pulse width is less than half a cycle, based on the resonant frequency... It can be seen that when the resistance R is small, the resonant period can be approximated as... With a fixed load C, the larger the period T required for resonance, the larger the additional inductance L needed in the design. In this application, the period required for resonance is much smaller than the system clock frequency, which means that the required inductance value L can be effectively reduced, thereby reducing the area required to construct the inductor and the design cost.

[0136] The technical solution of this application can adapt to on-chip variations. Since the pulse generation module and the subsequent transmission module have the same fundamental resonance principle, they can obtain the same trend of change under the influence of on-chip variations (OCV), and make proportional parameter offsets to achieve pulse width adaptation. This allows the subsequent buffer circuit to operate more accurately within the optimal range of the initially designed power consumption optimization.

[0137] This application also provides a chip, including: the resonant clock system as described in the above embodiments.

[0138] In some specific implementations, this chip may also include on-chip global clock distribution network, local clock distribution network, digital circuits using pulsed-latch systems, circuits that require pulse generation, and circuits that require long-distance signal transmission, among other circuit structures.

[0139] The specific circuit structure and working principle of the resonant clock system can be referred to the description in the above embodiments. Since the chip in this application adopts the resonant clock system of the above embodiments, it can achieve the same technical effect, which will not be repeated here.

[0140] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A resonant clock system, characterized in that, include: The connected pulse generation module, clock tree transmission module, and power supply are connected. The pulse generation module includes a resonant circuit, a switch control circuit, a logic control circuit, and a first master control terminal. The pulse generation module is used to generate a pulse signal based on the resonant circuit according to the acquired initial clock signal. The width of the pulse signal is the duration from the start of oscillation and discharge of the resonant circuit to the cut-off of the oscillation and discharge, and the duration is determined based on the resonant frequency of the resonant circuit. The logic control circuit is used to, after the rising edge of the initial clock signal received at the total input terminal of the pulse generation module occurs, control the signal of the first total control terminal to become high after a first preset time delay, thereby controlling the resonant circuit to oscillate and discharge; and after the voltage at the total output terminal of the pulse generation module changes from low to high and reaches a preset voltage value, control the signal of the first total control terminal to become low, cutting off the oscillation and discharge of the resonant circuit, and charging the capacitor in the resonant circuit from the power supply terminal. The switch control circuit is used to control the oscillation and discharge of the resonant circuit according to the signal change of the first total control terminal, or to control the power supply terminal to charge the capacitor in the resonant circuit. The clock tree transmission module includes multiple cascaded signal transmission units. Each signal transmission unit includes two-stage inverters and a first inductor. The second terminal of the second-stage inverter is connected to ground through the first inductor, and the output terminal of the second-stage inverter is connected to the input terminal of the next signal transmission unit or the load. The control terminal of the first-stage inverter is connected to the total output terminal of the previous signal transmission unit or the pulse generation module. The clock tree transmission module is used to transmit the pulse signal. The resonant frequency of the clock tree transmission module is the same as the resonant frequency of the resonant circuit.

2. The system according to claim 1, characterized in that, When the resonant circuit oscillates and discharges, it is used to cause the voltage at the total output terminal of the pulse generation module to oscillate and change. When the power supply terminal charges the capacitor in the resonant circuit, it is used to increase the voltage of the total output terminal.

3. The system according to claim 1, characterized in that, The logic control circuit includes: AND gates, NAND gates, multiple delay units, and an even number of inverters; The total input terminal is connected to the first input terminal of the NAND gate through multiple delay units; the total output terminal is connected to the second input terminal of the NAND gate through an even number of inverters; the output terminal of the NAND gate is connected to the first input terminal of the AND gate, the total input terminal is connected to the second input terminal of the AND gate; and the output terminal of the AND gate is connected to the first total control terminal.

4. The system according to claim 1 or 3, characterized in that, The switch control circuit includes: a first transistor, a second transistor, a pull-up switch, and a pull-down switch; the first transistor is a P-type transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate; the second transistor is an N-type transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate. The second terminal of the first transistor is connected to the power supply terminal, and the first terminal is connected to the first terminal of the second transistor and the total output terminal. The control terminal of the first transistor is connected to the total input terminal. The second terminal of the second transistor is connected to one end of the second inductor in the resonant circuit, and the control terminal of the second transistor is connected to the total input terminal. The first terminal of the pull-down switch is connected to the other end of the second inductor, and the control terminal of the pull-down switch is connected to the first total control terminal. The second terminal of the pull-up switch is connected to the power supply terminal, the first terminal is connected to the total output terminal, and the control terminal of the pull-up switch is connected to the first total control terminal.

5. The system according to claim 4, characterized in that, The switch control circuit further includes: a third transistor, which is a P-type transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate; The second terminal of the third transistor is connected to the total output terminal, the first terminal of the third transistor is connected to the second terminal of the second transistor, and the control terminal of the third transistor is used to receive the reverse signal of the first total control terminal.

6. The system according to claim 1, characterized in that, The system also includes a power supply terminal; The pulse generation module is specifically used for: After the initial clock signal received at the total input terminal of the pulse generation module has a falling edge, the resonant circuit is controlled to oscillate and discharge, so that the voltage at the total output terminal of the pulse generation module oscillates and changes. After the voltage at the total output terminal increases from low to high and reaches a preset voltage value, the oscillation discharge of the resonant circuit is cut off, and the capacitor in the resonant circuit is charged by the power supply terminal to increase the voltage at the total output terminal.

7. The system according to claim 6, characterized in that, The pulse generation module includes: a control circuit, a drive circuit, a feedback circuit, and a second main control terminal; The control circuit and drive circuit are configured to control the resonant circuit to oscillate and discharge after a falling edge appears in the initial clock signal received at the total input terminal; and The feedback circuit is used to control the signal at the second total control terminal to become high level after the voltage at the total output terminal changes from low to high and reaches a preset voltage value. The control circuit and drive circuit are also used to receive a high-level signal from the second general control terminal, cut off the oscillation discharge of the resonant circuit, and charge the capacitor in the resonant circuit by the power supply terminal.

8. The system according to claim 7, characterized in that, The control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the eighth transistor and the ninth transistor are P-type transistors, and the tenth transistor and the eleventh transistor are N-type transistors; the first terminal of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are all drains, the second terminal of the tenth transistor, and the control terminal of the eleventh transistor are all sources, and the control terminal of the eleventh transistor is the gate. Wherein, the second terminal of the eighth transistor is connected to the power supply terminal, and the first terminal is connected to the second terminal of the ninth transistor; the control terminal of the eighth transistor is connected to the total input terminal and the control terminal of the tenth transistor; the first terminal of the ninth transistor is connected to the first terminal of the tenth transistor, the first terminal of the eleventh transistor, and the output terminal of the control circuit; the control terminal of the ninth transistor is connected to the second total control terminal; the second terminal of the tenth transistor is grounded; the second terminal of the eleventh transistor is grounded; and the control terminal of the eleventh transistor is connected to the second total control terminal.

9. The system according to claim 7 or 8, characterized in that, The driving circuit includes: a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; the twelfth transistor and the fourteenth transistor are P-type transistors, and the thirteenth transistor is an N-type transistor; the first terminal of the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all sources, the second terminal is all drains, and the control terminal is all gates; The second terminal of the twelfth transistor is connected to the power supply terminal, and the first terminal is connected to the first terminal of the thirteenth transistor, the second terminal of the fourteenth transistor, and the total output terminal of the pulse generation module. The control terminal of the twelfth transistor is connected to the output terminal of the control circuit and the control terminal of the thirteenth transistor. The second terminal of the thirteenth transistor is connected to one end of the third inductor in the resonant circuit and the second terminal of the fourteenth transistor. The control terminal of the fourteenth transistor is connected to the output terminal of the control circuit.

10. The system according to claim 7 or 8, characterized in that, The feedback circuit includes: a first inverter, a NOR gate, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; the fifteenth and sixteenth transistors are P-type transistors, and the seventeenth transistor is an N-type transistor; the first terminal of the fifteenth, sixteenth, and seventeenth transistors is the source, the second terminal is the drain, and the control terminal is the gate. The input terminal of the first inverter is connected to the output terminal of the driving circuit, and the output terminal of the first inverter is connected to the control terminal of the sixteenth transistor and the first input terminal of the NOR gate; the second terminal of the sixteenth transistor is connected to the second terminal of the fifteenth transistor, the first terminal of the seventeenth transistor, the control terminal of the seventeenth transistor, and the second input terminal of the NOR gate; the control terminal of the fifteenth transistor is connected to the total input terminal; and the output terminal of the NOR gate is connected to the second total control terminal.

11. The system according to claim 1 or 6, characterized in that, in, The first terminal of the first-stage inverter is connected to the power supply terminal, and the second terminal of the first-stage inverter is connected to ground; the first terminal of the second-stage inverter is connected to the power supply terminal, and the control terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter.

12. The system according to claim 11, characterized in that, The first-stage inverter includes: a fourth transistor and a fifth transistor; The first terminal of the fourth transistor is connected to the power supply terminal, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the control terminal of the second-stage inverter, and the control terminal of the fourth transistor is connected to the total output terminal of the previous signal transmission unit or the pulse generation module; the second terminal of the fifth transistor is connected to ground, and the control terminal of the fifth transistor is connected to the total output terminal of the previous signal transmission unit or the pulse generation module. The second-stage inverter includes a sixth transistor and a seventh transistor; The first terminal of the sixth transistor is connected to the power supply terminal, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor and the input terminal of the next signal transmission unit or load, and the control terminal of the sixth transistor is connected to the output terminal of the first-stage inverter; the second terminal of the seventh transistor is connected to ground through the first inductor, and the control terminal of the seventh transistor is connected to the output terminal of the first-stage inverter.

13. The system according to claim 1, characterized in that, The system also includes: A clock raw output module, connected to the pulse generation module, is used to generate an initial clock signal and send it to the pulse generation module; and / or, The load module, connected to the clock tree transmission module, is used to process data based on the signal output by the clock tree transmission module.

14. The system according to claim 13, characterized in that, The system also includes: a signal shaping circuit; The load module and the clock tree transmission module are connected via the signal shaping circuit; The signal shaping circuit is used to shape the signal output by the clock tree transmission module into a square wave signal with a preset duty cycle and send it to the load module.

15. A chip, characterized in that, include: The resonant clock system as described in any one of claims 1-14.

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