A DDS circuit with synchronization function

Abstract

The present invention discloses a DDS circuit with synchronization function, which belongs to the field of integrated circuits and includes a synchronous receiving circuit, a synchronous transmitting circuit, a clock frequency division and controller, a phase accumulator, a phase-amplitude converter, a data synthesizer and a digital-to-analog converter. After an external synchronous signal is input, a digital core will automatically synchronize with the rising edge of the synchronous input signal. The present invention performs edge detection through the input synchronous signal and realizes the synchronization of the core clock, thereby generating a digital sinusoidal waveform with consistent initial phases, realizing output synchronization of multiple DDS circuits, solving the problem of inconsistent initial phases when multiple DDS circuits are used, and does not require external configuration of clocks or synchronization mechanism circuits, thereby simplifying the circuit configuration and use difficulty when DDS is applied, and can be widely used in DDS or related high-speed digital-to-analog converter circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a DDS circuit with a synchronization function. Background Art

[0002] DDS (Direct Digital Synthesizer) is a signal generator circuit synthesized in a fully digital way. It can generate a flexibly modulated sinusoidal analog waveform through a built-in digital-to-analog conversion circuit. It has the characteristics of fast configuration, precise frequency modulation and high-precision modulation, and is widely used in radar, testing and communication. In multi-channel applications, this type of device is difficult to ensure the phase consistency of the output signal in actual use due to the influence of peripheral circuits, power-on configuration and clock terminals. The traditional method configures the peripheral clock circuit and performs synchronous power-on configuration, or performs phase shift processing on the output signal, which consumes a lot of hardware and is complex to configure. Summary of the invention

[0003] The object of the present invention is to provide a DDS circuit with synchronization function to solve the problem of inconsistent initial phases when multiple DDS circuits are used.

[0004] In order to solve the above technical problems, the present invention provides a DDS circuit with synchronization function, comprising:

[0005] A phase accumulator receives an input Config signal and generates continuous phase signals Phase(1) to Phase(m);

[0006] A phase-to-amplitude converter converts the continuous phase signal into a continuous amplitude signal Amp(1) to Amp(m);

[0007] A data synthesizer converts the continuous amplitude signal into interleaved digital sinusoidal signals data(1) to data(n);

[0008] An analog receiver and synthesizer receives interleaved digital sinusoidal signals and synthesizes them into analog differential signals Adata(p) and Adata(q);

[0009] A digital-to-analog converter converts the analog differential signal into an analog sinusoidal output;

[0010] The synchronous receiving circuit receives the external synchronous input signal Sync_in and generates the internal synchronous clock f clk / 2;

[0011] Synchronous transmission circuit, the internal synchronous clock f clk / 2 is converted into a synchronous output signal Sync_out for external output;

[0012] Clock frequency division and controller, the internal synchronous clock fclk / 2 is processed as synchronized module clock f clk / m、f clk / m、f clk / n、f clk / 2. f clk , and are provided to the phase accumulator, phase-to-amplitude converter, data synthesizer, analog reception and synthesizer and digital-to-analog converter respectively.

[0013] In one implementation, the synchronous receiving circuit includes a delay circuit, a buffer 2, a buffer 4, a buffer 6, a buffer 8, a buffer 10, a buffer 13, a D flip-flop 3, a D flip-flop 5, a D flip-flop 7, a D flip-flop 9, a D flip-flop 11, a D flip-flop 15, a NAND gate 12, and a NAND gate 14;

[0014] The input end of the delay circuit is connected to the external synchronization input signal Sync_in and the delay parameter Input_delay <n:0>, the output end is connected to the D end of D flip-flop 3 through buffer 2; the Q end of D flip-flop 3 is connected to the D end of D flip-flop 5 through buffer 4, the Q end of D flip-flop 5 is connected to the D end of D flip-flop 7 through buffer 6, and the Q end of D flip-flop 7 is connected to the D end of D flip-flop 9 through buffer 8;

[0015] The Q end of the D flip-flop 9 is connected to the input end of the buffer 10 and the D end of the D flip-flop 11 at the same time, and the output end of the buffer 10 and the Q end of the D flip-flop 11 are connected to the input end of the NAND gate 12 at the same time; the output end of the NAND gate 12 is connected to an input end of the NAND gate 14 through the buffer 13, the output end of the NAND gate 14 is connected to the D end of the D flip-flop 15, and the Q end of the D flip-flop 15 is connected to the other input end of the NAND gate 14;

[0016] The clock signal terminals of the D flip-flop 3, D flip-flop 5, D flip-flop 7, D flip-flop 9, D flip-flop 11 and D flip-flop 15 are all connected to the system clock f clk .

[0017] In one implementation, the synchronous transmission circuit includes a D flip-flop twenty-one, a D flip-flop twenty-three, a D flip-flop twenty-five, a D flip-flop twenty-seven, a D flip-flop thirty, an inverter twenty, an inverter twenty-two, an inverter twenty-four, an inverter twenty-six, an inverter twenty-eight and an AND gate twenty-nine;

[0018] The clock input terminal of the D flip-flop twenty-one is connected to f clk / 2, the D terminal is connected to the output terminal of the inverter twenty, and the Q terminal is connected to the input terminal of the inverter twenty;

[0019] The clock input terminal of the D flip-flop 23 is connected to the Q terminal of the D flip-flop 21, the D terminal is connected to the output terminal of the inverter 22, and the Q terminal is connected to the input terminal of the inverter 22;

[0020] The clock input terminal of the D flip-flop 25 is connected to the Q terminal of the D flip-flop 23, the D terminal is connected to the output terminal of the inverter 24, and the Q terminal is connected to the input terminal of the inverter 24;

[0021] The clock input end of the D flip-flop 27 is connected to the Q end of the D flip-flop 25 and the input end of the inverter 28 at the same time, the D end is connected to the output end of the inverter 26, and the Q end is connected to the input end of the inverter 26;

[0022] The input end of the AND gate 29 is respectively connected to the Q end of the D flip-flop 27 and the output end of the inverter 28, and the output end is connected to the D end of the D flip-flop 30; the clock input end of the D flip-flop 30 is connected to the internal synchronous clock f clk / 2, the Q end is connected to the synchronous output signal Sync_out.

[0023] In one implementation, the Config signal is used to configure the phase, frequency, and amplitude parameters of the DDS circuit.

[0024] In one implementation, the number of bits m of the continuous phase signals Phase(1) to Phase(m) is determined by actual needs and is 4, 8, 16, etc. Correspondingly, its clock is f clk / m.

[0025] In one implementation, the number of bits m of the continuous amplitude signals Amp(1) to Amp(m) is consistent with the continuous phase signal, and the corresponding clock is f clk / m.

[0026] In one implementation, the interleaved digital sinusoidal signals data(1) to data(n) are determined by actual requirements and are 2 or 4. Correspondingly, the clock is f clk / n.

[0027] In one implementation, the clock frequency division and controller inputs a synchronization enable signal Sync_en for enabling a circuit synchronization function.

[0028] In one implementation, the frequency of the synchronization output signal Sync_out is f clk / 16, the duty cycle is 25%.

[0029] The present invention provides a DDS circuit with synchronization function, which realizes the phase consistency of the output signal when multiple DDS circuits are used simultaneously. The present invention performs edge detection and realizes the synchronization of the core clock through the input synchronization signal, thereby generating a digital sine waveform with consistent initial phase, and realizing the output synchronization of multiple DDS circuits. The DDS circuit proposed by the present invention includes a synchronous receiving circuit, a synchronous transmitting circuit, a clock frequency division and controller, a phase accumulator, a phase-amplitude converter, a data synthesizer and a digital-to-analog converter. After the external synchronization signal is input, the digital core will automatically synchronize with the rising edge of the synchronous input signal. The present invention can solve the problem of inconsistent initial phases when multiple DDS circuits are used, without the need for externally configured clocks or synchronization mechanism circuits, simplifying the circuit configuration and use difficulty when DDS is applied, and can be widely used in DDS or related high-speed digital-to-analog converter circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of a DDS circuit structure with synchronization function provided by the present invention;

[0031] Figure 2 It is a structural schematic diagram of a synchronous receiving circuit in the present invention;

[0032] Figure 3 is a signal timing diagram of a synchronous receiving circuit in the present invention;

[0033] Figure 4 It is a structural schematic diagram of a synchronous transmission circuit in the present invention;

[0034] Figure 5 It is a signal timing diagram of the synchronous transmission circuit in the present invention. DETAILED DESCRIPTION

[0035] The following is a further detailed description of a DDS circuit with synchronization function proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] Figure 1 The invention provides a DDS circuit with synchronization function. The circuit is a typical direct digital frequency synthesizer architecture. The difference is that a synchronization mechanism is added. The synchronization function module consists of a synchronization signal (SYNC) receiving and a synchronization signal (SYNC) sending.

[0037] Please continue reading Figure 1 The DDS circuit with synchronization function is composed of a phase accumulator, a phase-to-amplitude converter, a MUX (i.e., a data synthesizer), an analog receiver and synthesizer, a DAC (i.e., a digital-to-analog converter), a clock frequency divider and controller, a synchronous receiver circuit, and a synchronous transmitter circuit. The phase accumulator receives the input Config signal and generates continuous phase signals Phase(1) to Phase(m); the phase-to-amplitude converter converts the continuous phase signal into continuous amplitude signals Amp(1) to Amp(m); the data synthesizer converts the continuous amplitude signal into interleaved digital sinusoidal signals data(1) to data(n); the analog receiver and synthesizer receives the interleaved digital sinusoidal signals and synthesizes them into analog differential signals Adata(p) and Adata(q); the digital-to-analog converter converts the analog differential signals into analog sinusoidal outputs; the synchronous receiver circuit receives the external synchronous input signal Sync_in and generates an internal synchronous clock f clk / 2; The synchronous transmission circuit sends the internal synchronous clock f clk / 2 is converted into a synchronous output signal Sync_out for external output; the clock frequency division and controller converts the internal synchronous clock f clk / 2 is processed as synchronized module clock f clk / m、f clk / m、f clk / n、f clk / 2. f clk , and are provided to the phase accumulator, phase-to-amplitude converter, data synthesizer, analog reception and synthesizer and digital-to-analog converter respectively.

[0038] The Config signal is used to configure the phase, frequency, amplitude and other parameters of the DDS circuit. The number of bits m of the continuous phase signals Phase(1) to Phase(m) is determined by actual needs and can be 4, 8, 16, etc. Correspondingly, its clock is f clk / m; the number of bits m of the continuous amplitude signal Amp(1)~Amp(m) is consistent with the continuous phase signal, and the corresponding clock is f clk / m. The interleaved digital sinusoidal signals data(1) to data(n) are determined by actual needs, and are generally 2 or 4, or there is also a single channel without interleaving; correspondingly, its clock is f clk The clock frequency division and controller input has a synchronization enable signal Sync_en for enabling the circuit synchronization function.

[0039] In the embodiment of the present invention, the phase accumulator and the phase-to-amplitude converter are both 16-bit structures, i.e., m=16; they are converted into 4-bit interleaved digital sinusoidal signals data (1:4) by MUX, i.e., n=4. The SYNC receiving circuit (i.e., the synchronous receiving circuit) captures the rising edge of the external synchronous input signal Sync_in and generates a two-frequency divided clock f with the same phase. clk / 2. The SYNC transmission circuit (synchronous transmission circuit) divides the internal two-frequency clock f clk / 2 is processed into a 16-frequency divided signal Sync_out with the same phase and a duty cycle of 25%, and is provided to the external slave device that needs to be synchronized as its synchronization signal input.

[0040] Figure 2 1 is a schematic diagram of the structure of the synchronous receiving circuit of the present invention, including a delay circuit 1, a buffer 2, a buffer 4, a buffer 6, a buffer 8, a buffer 10, a buffer 13, a D flip-flop 3, a D flip-flop 5, a D flip-flop 7, a D flip-flop 9, a D flip-flop 11, a D flip-flop 15, a NAND gate 12, and a NAND gate 14. The input end of the delay circuit is connected to an external synchronous input signal Sync_in and a delay parameter Input_delay. <n:0>, the output end is connected to the D end of D flip-flop 3 through buffer 2; the Q end of D flip-flop 3 is connected to the D end of D flip-flop 5 through buffer 4, the Q end of D flip-flop 5 is connected to the D end of D flip-flop 7 through buffer 6, and the Q end of D flip-flop 7 is connected to the D end of D flip-flop 9 through buffer 8; the Q end of D flip-flop 9 is simultaneously connected to the input end of buffer 10 and the D end of D flip-flop 11, and the output end of buffer 10 and the Q end of D flip-flop 11 are simultaneously connected to the input end of NAND gate 12; the output end of NAND gate 12 is connected to one input end of NAND gate 14 through buffer 13, the output end of NAND gate 14 is connected to the D end of D flip-flop 15, and the Q end of D flip-flop 15 is connected to the other input end of NAND gate 14; the clock signal ends of D flip-flop 3, D flip-flop 5, D flip-flop 7, D flip-flop 9, D flip-flop 11, and D flip-flop 15 are all connected to the system clock f clk .

[0041] The delay circuit is used to fine-tune the phase of the synchronous clock, which can be adjusted by the T value of N+1; after the synchronous input signal Sync_in is sampled by four clock delays, a synchronous pulse with a pulse width of the system clock (sysclk) is generated through a NAND gate 12, and finally a synchronized divided-by-two clock f is generated through a divide-by-two circuit composed of a NAND gate 14 and a D flip-flop 15. clk / 2.

[0042] Figure 3 It is the working timing of the synchronous receiving circuit. Since the system clock sysclk of the master device and the slave device is the same clock, the synchronization signal Sync_in and the system clock sysclk are coherent clocks. After being processed by the synchronous receiving circuit, a two-frequency clock f with a phase difference of 4 system clocks from the synchronization signal Sync_in can be generated. clk / 2.

[0043] Figure 4 2 is a schematic diagram of the structure of the synchronous transmission circuit in the present invention, including D flip-flop 21, D flip-flop 23, D flip-flop 25, D flip-flop 27, D flip-flop 30, inverter 20, inverter 22, inverter 24, inverter 26, inverter 28, and AND gate 29. The clock input terminal of the D flip-flop 21 is connected to f clk / 2, the D end is connected to the output end of inverter 20, and the Q end is connected to the input end of inverter 20; the clock input end of the D flip-flop 23 is connected to the Q end of the D flip-flop 21, the D end is connected to the output end of inverter 22, and the Q end is connected to the input end of inverter 22; the clock input end of the D flip-flop 25 is connected to the Q end of the D flip-flop 23, the D end is connected to the output end of inverter 24, and the Q end is connected to the input end of inverter 24; the clock input end of the D flip-flop 27 is simultaneously connected to the Q end of the D flip-flop 25 and the input end of inverter 28, the D end is connected to the output end of inverter 26, and the Q end is connected to the input end of inverter 26; the input end of the AND gate 29 is respectively connected to the Q end of the D flip-flop 27 and the output end of inverter 28, and the output end is connected to the D end of the D flip-flop 30; the clock input end of the D flip-flop 30 is connected to the internal synchronous clock f clk / 2, the Q end is connected to the synchronous output signal Sync_out.

[0044] In the synchronous transmission circuit, the synchronized divided-by-two clock f clk / 2 is divided by two four times to generate a synchronized 16-frequency clock f clk / 16; the duty cycle is adjusted through inverter 28 and AND gate 29 to generate a 16-frequency clock signal with a duty cycle of 25%'f clk / 16, and finally generates a two-frequency clock f through thirty D flip-flops clk / 2 aligned synchronization signal output, see the specific signal timing diagram Figure 5 .

[0045] It is particularly noted that the clock frequency division and controller are not described in the present invention. When synchronization is enabled, the clock frequency division and controller will generate a two-frequency clock f clk / 2 delay fixed frequency division clock, including f clk / 16, f clk / 4 and f clk / 2,f clk There are no special requirements, and the DLL method can be selected for automatic alignment in the design.

[0046] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DDS circuit with synchronization function, characterized in that: include: A phase accumulator receives an input Config signal and generates continuous phase signals Phase(1) to Phase(m); A phase-to-amplitude converter converts the continuous phase signal into a continuous amplitude signal Amp(1) to Amp(m); A data synthesizer converts the continuous amplitude signal into interleaved digital sinusoidal signals data(1) to data(n); An analog receiver and synthesizer receives interleaved digital sinusoidal signals and synthesizes them into analog differential signals Adata(p) and Adata(q); A digital-to-analog converter converts the analog differential signal into an analog sinusoidal output; The synchronous receiving circuit receives the external synchronous input signal Sync_in and generates the internal synchronous clock f clk / 2; Synchronous transmission circuit, the internal synchronous clock f clk / 2 is converted into a synchronous output signal Sync_out for external output; Clock frequency division and controller, the internal synchronous clock f clk / 2 is processed as synchronized module clock f clk / m、f clk / m、f clk / n、f clk / 2. f clk , and are provided to the phase accumulator, phase-to-amplitude converter, data synthesizer, analog reception and synthesizer and digital-to-analog converter respectively.

2. The DDS circuit with synchronization function as claimed in claim 1, characterized in that: The synchronous receiving circuit includes a delay circuit, a buffer 2, a buffer 4, a buffer 6, a buffer 8, a buffer 10, a buffer 13, a D flip-flop 3, a D flip-flop 5, a D flip-flop 7, a D flip-flop 9, a D flip-flop 11, a D flip-flop 15, a NAND gate 12 and a NAND gate 14; The input end of the delay circuit is connected to the external synchronization input signal Sync_in and the delay parameter Input_delay <n:0> , the output end is connected to the D end of D flip-flop 3 through buffer 2; the Q end of D flip-flop 3 is connected to the D end of D flip-flop 5 through buffer 4, the Q end of D flip-flop 5 is connected to the D end of D flip-flop 7 through buffer 6, and the Q end of D flip-flop 7 is connected to the D end of D flip-flop 9 through buffer 8;< / n:0> The Q end of the D flip-flop 9 is connected to the input end of the buffer 10 and the D end of the D flip-flop 11 at the same time, and the output end of the buffer 10 and the Q end of the D flip-flop 11 are connected to the input end of the NAND gate 12 at the same time; the output end of the NAND gate 12 is connected to an input end of the NAND gate 14 through the buffer 13, the output end of the NAND gate 14 is connected to the D end of the D flip-flop 15, and the Q end of the D flip-flop 15 is connected to the other input end of the NAND gate 14; The clock signal terminals of the D flip-flop 3, D flip-flop 5, D flip-flop 7, D flip-flop 9, D flip-flop 11 and D flip-flop 15 are all connected to the system clock f clk .

3. The DDS circuit with synchronization function as claimed in claim 2, characterized in that: The synchronous transmission circuit includes a D flip-flop 21, a D flip-flop 23, a D flip-flop 25, a D flip-flop 27, a D flip-flop 30, an inverter 20, an inverter 22, an inverter 24, an inverter 26, an inverter 28 and an AND gate 29; The clock input terminal of the D flip-flop twenty-one is connected to f clk / 2, the D terminal is connected to the output terminal of the inverter twenty, and the Q terminal is connected to the input terminal of the inverter twenty; The clock input terminal of the D flip-flop 23 is connected to the Q terminal of the D flip-flop 21, the D terminal is connected to the output terminal of the inverter 22, and the Q terminal is connected to the input terminal of the inverter 22; The clock input terminal of the D flip-flop 25 is connected to the Q terminal of the D flip-flop 23, the D terminal is connected to the output terminal of the inverter 24, and the Q terminal is connected to the input terminal of the inverter 24; The clock input end of the D flip-flop 27 is connected to the Q end of the D flip-flop 25 and the input end of the inverter 28 at the same time, the D end is connected to the output end of the inverter 26, and the Q end is connected to the input end of the inverter 26; The input end of the AND gate 29 is respectively connected to the Q end of the D flip-flop 27 and the output end of the inverter 28, and the output end is connected to the D end of the D flip-flop 30; the clock input end of the D flip-flop 30 is connected to the internal synchronous clock f clk / 2, the Q end is connected to the synchronous output signal Sync_out.

4. The DDS circuit with synchronization function as claimed in claim 1, characterized in that: The Config signal is used to configure the phase, frequency, and amplitude parameters of the DDS circuit.

5. The DDS circuit with synchronization function as claimed in claim 1, characterized in that: The number of bits m of the continuous phase signals Phase(1) to Phase(m) is determined by actual needs and can be 4, 8, 16, etc. Correspondingly, its clock is f clk / m.

6. The DDS circuit with synchronization function as claimed in claim 5, characterized in that: The number of bits m of the continuous amplitude signal Amp(1) to Amp(m) is consistent with the continuous phase signal, and the corresponding clock is f clk / m.

7. The DDS circuit with synchronization function as claimed in claim 1, characterized in that: The interleaved digital sinusoidal signals data(1) to data(n) are determined by actual needs and can be 2 or 4. Correspondingly, the clock is f clk / n.

8. The DDS circuit with synchronization function as claimed in claim 1, characterized in that: The clock frequency division and controller input has a synchronization enable signal Sync_en for enabling the circuit synchronization function.

9. The DDS circuit with synchronization function as claimed in claim 1, characterized in that: The frequency of the synchronous output signal Sync_out is f clk / 16, the duty cycle is 25%.

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