Sampling switch circuit

Abstract

A sampling switching circuit includes: an input node connected to receive an input voltage signal to be sampled; a sampling transistor including a gate terminal, a source terminal, and a drain terminal, the source terminal being connected to the input node; a capacitor; a current source configured to allow a defined current to flow through it; and a switching circuit system configured to alternate between a pre-charge configuration and an output configuration according to a clock signal. In the pre-charge configuration, the switching circuit system connects the capacitor to a current path between the current source and a first voltage reference node to create a potential difference across the capacitor that depends on the defined current. In the output configuration, the switching circuit system connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor such that the voltage level applied at the gate terminal of the sampling transistor depends on the defined current.

Description

Technical Field

[0001] This invention relates to a sampling switch circuit and circuit system, which may be referred to as a sampling circuit system. The sampling switch circuit according to the invention may be referred to as a sample-and-hold circuit or a sample-and-hold switch circuit. Background Technology

[0002] Generally speaking, voltage-mode sampling and current-mode sampling are known, and a sample-and-hold circuit can be considered an example of a voltage-mode sampling circuit.

[0003] In a typical voltage-mode sampler, the sampling transistor, such as a field-effect transistor (FET), acts as a simple switch that is turned on during the sampling (tracking or output) phase and turned off during the hold phase. The on-resistance of the device (sampling transistor) depends on the input voltage (e.g., the gate-source voltage in the case of a FET), which in turn produces harmonic distortion, i.e., input-dependent distortion. Where the voltage-mode sampler is located at the front end of an analog-to-digital converter (ADC), harmonic distortion can limit the ADC's dynamic range.

[0004] Bootstrap circuits initially appeared as passive level shifters that operated in continuous mode to provide a gate voltage proportional to the input. See, for example, M. Kikushi and M. Takeda, “Distortionless FET switching circuit,” US3942039. Later, developments were made to reduce continuous power consumption (as the number of switches implemented increases) and voltage margin (as the supply voltage decreases), leading to widely used bootstrap topologies, such as those discussed in M. Dessouky and A. Kaiser, “Very low-voltage digital audio TR modulator with 88-dB dynamicrange using local switch bootstrapping,” IEEE J. Solid State Circuits, Vol. 36, pp. 349–355, March 2001.

[0005] The function of the bootstrap circuit is to maintain the continuous on-resistance of the switch by maintaining a constant gate-source voltage Vgs. The previously considered bootstrapping method will now be explored in an introductory manner.

[0006] As described above, a bootstrap circuit can be used (during the sampling or tracking phase) to provide or apply a constant voltage across the gate-source of a switch, which is at least theoretically independent of the input signal. This reduces or minimizes the input-dependent on-resistance variation of the sampling switch.

[0007] Figure 1 This is a schematic diagram of sampling switch circuit 1, used to fully understand the bootstrap concept. Input signal V IN Applied to sampling switch M S The source (source terminal), in this case the sampling switch M S These are transistors (especially field-effect transistors). A voltage source V0 (e.g., a battery) is then connected between the source and gate (gate terminal) via a clock-controlled switch, such that during the tracking phase, the voltage V0+V... IN Applied to sampling switch M S The gate voltage, V0, is constant during the tracking phase. The gate is connected to ground (ground supply voltage) separately via another clock-controlled switch. The sampling capacitor C... S Connected to sampling switch M S The drain (drain terminal), sampling switch M S The drain of the circuit acts as the output node of circuit 1, and the output signal V is generated at this output node. OUT Sampling capacitor C S It is connected between the drain and ground.

[0008] Typically, as shown, V0 = V DD , where V DD It is the supply voltage, and this enables the device M... S To obtain the maximum possible gate-source voltage, device M S To generate minimum on-resistance. Figure 1 In this context, CLK represents a frequency of f. s The sampling clock (clock signal).

[0009] Circuit 1 operates as follows. When CLK is high (and -CLK is low), the sampling switch M... S The gate is connected to ground (ground supply voltage). The terms "high" and "low" can refer to voltage levels, such as digital voltage levels, for example, V0 and V1 respectively. DD Voltage level and GND (0V) voltage level. Therefore, transistor M S The circuit is off and the sampling capacitor C is in operation. S The sampled value (voltage) is held during the holding phase (or period). When CLK is low (-CLK is high), V IN +V DD It is applied to the gate of the switch. Therefore, transistor M S The circuit is now turned on and is in tracking mode (tracking phase or period), and the sampling capacitor C is activated. S Voltage tracking input signal V at both ends INTherefore, the gate-source voltage in tracking mode is V. IN +V DD –V IN =V DD That is, with the input signal V IN Irrelevant.

[0010] Figure 2 The previously considered bootstrap circuit 10 is shown as a detailed implementation of circuit 1. In bootstrap circuit 10, the voltage source V0 (in other words, Figure 1 The battery in the middle uses a fairly large capacitor C. B accomplish.

[0011] The operation of circuit 10 is as follows.

[0012] When the sampling clock is high (i.e., CLK = high), transistors M5 and M 5t On, transistors M5 and M 5t The circuit is turned on at node G (i.e., sampling switch M). S The voltage at the gate of the sampling switch M is reduced to ground. S Turn off and start sampling capacitor C S The sampled value is held during the hold phase. During this phase (i.e., the hold phase), transistors M2 and M7 are also turned off. The clock signal "-CLK" (which is the inverted version of the clock signal CLK) is low (i.e., -CLK = low). This turns off transistor M6 and turns on transistor M8. This raises the voltage at node Z to the supply voltage, i.e., V. DD Since node Z is now connected to V DD Therefore, transistor M4 is turned off. Simultaneously, since the voltage at node G is grounded (i.e., it has a ground supply voltage), transistor M3 is turned on. Transistor M1 is also turned on (because CLK = high). In this situation, capacitor C... B It is connected to ground (GND) at its bottom plate and to V at its top plate. DD Therefore, this is also called the pre-charge phase, because when the sample is held in the sampling capacitor C... S When above, capacitor C B Precharged to store voltage V DD .

[0013] When the sampling clock is low (i.e., CLK = low), transistors M5 and M 5t The transistor is switched off, and therefore node G is disconnected from ground. Transistor M8 quickly turns off, and transistor M6 quickly turns on (-CLK = high) and connects node X (whose voltage level was ground at the beginning of this phase) to node Z, which in turn causes the voltage on node Z to change from V0. DDThe voltage drops to ground. This turns on transistor M4 and connects node Y to node G. In this case, the voltage on node G begins to rise (because node Y is charged to V during the precharge / hold phase). DD As the voltage at node G increases, transistors M2 and M7 begin to conduct (in other words, they turn on). This causes the voltages at nodes Z and X to shift towards the input signal V. IN The voltage increases. At this point, the voltage at node Y increases to V. DD +V IN (because V) DD It is capacitor C B The initial voltage (V) on the surface. DD +V IN The signal is transmitted to node G (i.e., sampling switch M). S (the gate of the switch). In this case, the gate-source voltage of the switch is V. DD +V IN -V IN =V DD The gate-source voltage is constant and varies with the input signal V. IN Irrelevant. As mentioned before, this stage is referred to as the sampling, tracking, or output stage, in which the sampling switch M... S The circuit is turned on, and the sampling capacitor C is activated. S Voltage tracking input signal V at both ends IN .

[0014] The inventors also considered the above-mentioned Figure 2 Circuit 10 in the diagram relates to the operation of ultra-high sampling frequencies. One problem the inventors recognized was V... IN The input impedance at that point is relatively low; for example, look at the bootstrap section of the circuit (responsible for feeding the sampling switch M). S The portion that provides the gate voltage, i.e., in Figure 2 The middle part includes transistors M1 to M8 and capacitor C. B (partial), thus causing sampling switch M S The relatively high input load.

[0015] It is desirable to solve one or more of the above problems, and in particular, it is desirable to provide sampling switching circuits with improved performance, for example, at higher operating speeds. It is desirable to provide improved sampling switching circuits that can be used as the front end of a voltage-mode sampler for an ADC, for example, in direct RF applications. Summary of the Invention

[0016] According to a first aspect of the present invention, a sampling switch circuit is provided, comprising: an input node connected to receive an input voltage signal to be sampled; a sampling transistor including a gate terminal, a source terminal, and a drain terminal, the source terminal being connected to the input node; a capacitor; a current source configured to allow a defined current to flow therethrough; and a switching circuit system configured to switch between a pre-charge configuration and an output configuration according to a clock signal. In the pre-charge configuration, the switching circuit system connects the capacitor to a current path between the current source and a first voltage reference node to form a potential difference across the capacitor that depends on the defined current. In the output configuration, the switching circuit system connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor such that the voltage level applied at the gate terminal of the sampling transistor depends on the defined current.

[0017] The pre-charge configuration can be referred to as the hold configuration. The output configuration can be referred to as the sample configuration. An example of switching between the pre-charge configuration and the output configuration could be alternating between the two.

[0018] A first voltage reference node can be configured to provide a first reference voltage signal, and a second voltage reference node can be configured to provide a second reference voltage signal. The first and second reference voltage signals can be DC voltage signals, reference DC voltage signals, constant voltage signals, or constant DC voltage signals. The first and second reference voltage signals can have the same voltage level.

[0019] The current source can be a controllable current source and can be configured such that the defined current depends on the control signal.

[0020] The control signal may include a control voltage signal, and the controllable current source may be configured such that the defined current depends on the voltage level of the control voltage signal. The control signal may also include a control digital signal, and the controllable current source may be configured such that the defined current depends on the digital value of the control digital signal. The control signal may be the output of a DAC (digital-to-analog converter) controlled by the control digital signal.

[0021] The control voltage signal can be the input voltage signal or can depend on the input voltage signal.

[0022] A controllable current source may include at least one transistor connected to control a defined current based on the gate voltage of the at least one transistor. The at least one transistor of the controllable current source may be connected such that its gate voltage depends on a control signal. The controllable current source may include a DAC connected to the gate terminal of the at least one transistor.

[0023] A controllable current source may include multiple transistors connected together to control a defined current based on their respective gate voltages. The multiple transistors of a controllable current source can be connected such that their gate voltages depend on a control signal.

[0024] The defined current, capacitor, clock signal, and voltage levels at the first and second voltage reference nodes can be configured such that the difference between the voltage levels provided at the gate and source terminals of the sampling transistor when the switching circuit system is in the output configuration is greater than or equal to the threshold voltage of the sampling transistor.

[0025] The capacitor may include a first terminal and a second terminal. The switching circuit system may include a first pair of switches and a second pair of switches. The first pair of switches may include a first switch connected between the first terminal of the capacitor and a current source, and a second switch connected between the second terminal of the capacitor and a first voltage reference node. The second pair of switches may include a third switch connected between the first terminal of the capacitor and a second voltage reference node, and a fourth switch connected between the second terminal of the capacitor and the gate terminal of the sampling transistor.

[0026] In the pre-charge configuration, the switching circuit system can be configured such that the first and second switches are on, and the third and fourth switches are off; and in the output configuration, the switching circuit system can be configured such that the first and second switches are off, and the third and fourth switches are on.

[0027] The first switch, the second switch, the third switch, and the fourth switch can be implemented as transistors, or optionally as field-effect transistors.

[0028] The current source may include at least one transistor, and wherein the third and fourth switches may be larger than at least one transistor, and optionally larger than the first and second switches.

[0029] The fourth switch may be a transistor comprising a gate terminal, a source terminal, and a drain terminal. The capacitor may be a first capacitor. The sampling switch circuit may include a second capacitor. In a pre-charge configuration, the switching circuit system may connect the second capacitor to create a given potential difference across the second capacitor. In an output configuration, the switching circuit system may connect the second capacitor between the gate terminal and the source terminal of the fourth switch such that the gate-source voltage of the fourth switch is limited by the given potential difference.

[0030] The switching circuit system can be configured, in a precharge configuration, to connect the gate terminal of the sampling transistor to a third voltage reference node, such that the voltage level applied at the gate terminal of the sampling transistor in the precharge configuration can depend on the voltage level provided at the third voltage reference node.

[0031] The third voltage reference node can be configured to provide a third reference voltage signal, which may optionally be a DC voltage signal and may optionally have a voltage level such that the difference between the voltage levels provided at the gate terminal and source terminal of the sampling transistor when the switching circuit system is in a pre-charge configuration is less than the threshold voltage of the sampling transistor.

[0032] The switching circuitry may include a holding switch connected between the gate terminal of the sampling transistor and a third reference voltage reference node. The switching circuitry may be configured such that the holding switch is on in a pre-charge configuration and off in an output configuration. Optionally, the holding switch may be implemented as a transistor.

[0033] According to a second aspect of the present invention, a multi-channel sampling circuit system is provided, comprising a plurality of sampling switch circuits according to the aforementioned first aspect of the present invention. Each of the sampling switch circuits can be configured to operate based on its own clock signal. The input nodes of the sampling switch circuits can be connected together to form a common input node and can receive the same input voltage signal from each other.

[0034] Multiple channels and / or the switching circuitry of said channels may have a common (i.e., shared) reference voltage or supply voltage. Multiple channels and the switching circuitry of said channels may have their own individual reference voltage or supply voltage.

[0035] According to a third aspect of the present invention, an analog-to-digital converter is provided, which includes a sampling switch circuit according to the aforementioned first aspect of the present invention or a multi-channel sampling circuit system according to the aforementioned second aspect of the present invention.

[0036] According to a fourth aspect of the present invention, an integrated circuit system, such as an IC chip, is provided, the integrated circuit system including a sampling switch circuit according to the aforementioned first aspect of the present invention, or a multi-channel sampling circuit system according to the aforementioned second aspect of the present invention, or an analog-to-digital converter according to the aforementioned third aspect of the present invention. Attached Figure Description

[0037] Now, we will refer to the attached diagram as an example, in which:

[0038] Figure 1 The above is a schematic diagram of the previously considered sampling switch circuit;

[0039] Figure 2 The bootstrap circuit previously considered is shown above. Figure 1 Detailed implementation of the circuit;

[0040] Figure 3 This is a schematic diagram illustrating the sampling switch circuit of the present invention;

[0041] Figure 3A It is in the pre-charge configuration Figure 3 Schematic diagram of the sampling switch circuit;

[0042] Figure 3B It is in the output configuration Figure 3 Schematic diagram of the sampling switch circuit;

[0043] Figure 4 It shows Figure 3 A variant of the current source for the sampling switch circuit;

[0044] Figure 5 It shows Figure 3 Another variation of the current source for the sampling switch circuit;

[0045] Figure 6 It has n-bit digital control. Figure 3 A variant of the current source for the sampling switch circuit;

[0046] Figure 7 This is a schematic diagram illustrating the sampling switch circuit of the present invention;

[0047] Figure 8 This is a schematic diagram illustrating the multi-channel sampling switch circuit of the present invention;

[0048] Figure 9 It is shown during the first operating mode Figure 7 The curve of the voltage signal at the gate terminal of the sampling switch in the sampling switch circuit over time;

[0049] Figure 10 It is shown during the second operating mode Figure 7 The curve of the voltage signal at the gate terminal of the sampling switch in the sampling switch circuit over time;

[0050] Figure 11 This is a schematic diagram illustrating the ADC of the present invention; and

[0051] Figure 12 This is a schematic diagram illustrating the integrated circuit system of the present invention. Detailed Implementation

[0052] The embodiments of the present invention attempt to solve the above problems.

[0053] In particular, through an overview and review Figure 1 and Figure 2 The discussion, in the implementation described herein, reduced the sampling switch M SThe input load is advantageous in voltage-mode sampling applications. The circuit configuration allows it to operate in two different modes. The first mode allows the circuit to act as an input reference and operate like a conventional bootstrap circuit, but with the aforementioned advantages. The second mode alternatively uses a reference voltage (or other control signal) instead of as an input reference (and can be considered as applying a voltage to the sampling transistor M). S The signal voltage level at the gate terminal is shifted (in this case, increased). Two modes will be considered in this paper, both of which provide high impedance input or high input impedance (to the switching circuitry or bootstrap section of the circuit), allowing for use in large arrays.

[0054] Figure 3 This is a simplified schematic diagram illustrating the sampling switch circuit 100 embodying the present invention. The sampling switch circuit 100 may be referred to as, for example, a sampling circuit, a sampler circuit, a sampler front-end circuit, an ADC front-end circuit, a sample-and-hold circuit, or a sample-and-hold switch circuit, and this disclosure will be understood accordingly. Variations of the sampling switch circuit 100 embodying the present invention will be considered later below.

[0055] The sampling switch circuit 100 includes an input node V IN Sampling transistor (sampling switch) M S Capacitor C1, current source 120, switching circuit system and output node V OUT .

[0056] The input node is connected to receive the input voltage signal V to be sampled. IN Sampling transistor M S It includes a gate terminal, a source terminal, and a drain terminal, with the source terminal connected to the input node.

[0057] Current source 120 is configured to make a defined current I D The current flows through it. As shown by the dashed line, the current source 120 can be a controllable current source and is controlled by the input voltage signal V. IN (First mode) control, causing the limited current I... D Depends on the input voltage signal V IN (e.g., with input voltage signal V) IN (Proportional). However, this is not necessary. For example, current source 120 can be an uncontrollable current source (second mode), such that the defined current I... D Effectively fixed and predefined. As another example, current source 120 can be a controllable current source and subject to the input voltage signal V. IN Different (e.g., unrelated) control signals control (second mode).

[0058] Capacitor C1 includes a first terminal and a second terminal labeled a and b, and the switching circuit system includes first switches SW1 through fourth switches SW4 and a fifth switch SW5. The first, second, third, and fourth switches can be implemented as transistors, optionally as field-effect transistors. The fifth switch can also be implemented as a transistor, optionally as a field-effect transistor.

[0059] The first switch SW1 and the second switch SW2 can be considered as the first pair of switches, and the third switch SW3 and the fourth switch SW4 can be considered as the second pair of switches.

[0060] Focusing on the first pair of switches, the first switch SW1 is connected between the first terminal a of capacitor C1 and the current source 120, and the second switch SW2 is connected between the second terminal b of capacitor C1 and the first voltage reference node V. DD1 Between. The current source is connected between the first switch SW1 and another reference voltage node, which can be considered as the ground voltage reference node (GND).

[0061] Switching to the second pair of switches, the third switch SW3 is connected between the first terminal a of capacitor C1 and the second voltage reference node V. DD2 Between, and the fourth switch SW4 is connected between the second terminal b of capacitor C1 and the gate terminal of the sampling transistor marked as node c.

[0062] First voltage reference node V DD1 Configured to provide a first reference voltage signal, and a second voltage reference node V DD2 Configured to provide a second reference voltage signal, which may be a DC voltage signal (DC reference voltage or DC reference voltage signal). The first and second reference voltage signals may have the same voltage level (e.g., the (core) supply voltage V). DD ), or they can be different. For example, V DD2 Voltage levels can be higher than V DD1 Voltage Level. The ground voltage reference node GND is configured to provide a ground reference voltage signal, which can be a DC voltage signal. Nominally, the voltage level at the ground voltage reference node GND can be referred to as 0V. For convenience, node V... DD1 and V DD2 The (supply) voltage level at a point can be referred to as V. DD1 and V DD2 .

[0063] The fifth switch SW5 is connected between the gate terminal of the sampling transistor, i.e., node c, and another reference voltage node. This other reference voltage node can also be the ground voltage reference node (GND) as shown, but in other arrangements, a DC voltage signal with a voltage level different from the voltage level of ground (i.e., 0V) can be provided.

[0064] Sampling capacitor C S Connected to sampling switch M S The drain terminal acts as the output node, and the output signal V is generated at this drain terminal. OUT Sampling capacitor C S Connected between the drain terminal and another reference voltage node, as shown, this other reference voltage node can also be a ground voltage reference node (GND). Although in some arrangements the sampling capacitor C S It is indicated as a discrete component, but it can be a parasitic capacitance.

[0065] The sampling switch circuit 100 is configured to operate in a precharge configuration and an output configuration (switching or alternating between the precharge configuration and the output configuration) according to a clock signal CLK. In the precharge configuration, the switching circuitry of the sampling switch circuit 100 connects capacitor C1 to the current source 120 and the first voltage reference node V. DD1 In the current path between them, a current I is formed across capacitor C1 that depends on a defined current. D The potential difference. In the output configuration, the switching circuitry connects capacitor C1 to the second voltage reference node V. DD2 Between the sampling transistor and its gate terminal, such that the voltage level applied at the gate terminal of the sampling transistor, i.e., node c, depends on a defined current I. D .

[0066] To provide precharge and output configurations, the first switch SW1 and the second switch SW2 are connected to be controlled by the clock signal CLK, and the third switch SW3 and the fourth switch SW4 are connected to be controlled by the clock signal / CLK (which may be referred to as -CLK, clock-bar, or inverted clock, and is an inverted version of the clock signal CLK). The fifth switch SW5 is also connected to be controlled by the clock signal CLK.

[0067] Figure 3 Example timing diagrams or waveforms for clock signals CLK and / CLK are also shown, illustrating that when / CLK is low (marked as 0), CLK is high (marked as V). DD), and when / CLK is high, CLK is low. Both clock signals shown have a 50% duty cycle (i.e., the clock signal is high for the same proportion of time as the clock signal is low), but it is understood that the duty cycle can be any percentage, representing any ratio between the amount of time the clock signal is high and the amount of time the clock signal is low within a given period or cycle.

[0068] Figure 3A The circuit 100 in the pre-charge configuration is shown. When CLK is high (e.g., V...), DD When / CLK is low (e.g., GND), the switching circuitry is configured into a pre-charge configuration. In this configuration, the first switch SW1 and the second switch SW2 are on, and the third switch SW3 and the fourth switch SW4 are off. In this configuration, the fifth switch SW5 is also on.

[0069] In the pre-charge configuration, capacitor C1 is connected to current source 120 and the first voltage reference node V. DD1 In the current path between. As previously mentioned, it depends on the defined current I. D A potential difference is formed across capacitor C1. Once the circuit begins operation, this potential difference may form during a series (or more) initial precharge configuration periods or periods, separated by the initial output configuration period or period. During normal operation, this potential difference may also follow the defined current I. D Any changes within multiple precharge configuration periods or cycles separated by output configuration periods or cycles.

[0070] Specifically, the potential difference across capacitor C1 becomes related to the defined current I. D Proportional. For example, if the current I is limited. D Increase, the voltage V at node a a This will decrease, causing the potential difference V across capacitor C1 to... DD1 -V a This will increase. During the duration of the pre-charge configuration, this will be based on a limited current I. D Control the potential difference across capacitor C1.

[0071] Since SW5 is also turned on, sampling transistor M... S The gate terminal of the sample transistor M is supplied with a ground voltage from the ground voltage reference node. S It is controlled to be off, so that the sample (presents a V based on the previous clock cycle) IN The potential difference (in the form of a sample capacitor C) is maintained at the sampling capacitor C. S superior.

[0072] Figure 3BCircuit 100 in the output configuration is shown. When CLK is low (e.g., GND) and / CLK is high (e.g., V), DD When the switch circuit is activated, it is configured in the output configuration. In this configuration, the first switch SW1 and the second switch SW2 are off, and the third switch SW3 and the fourth switch SW4 are on. In this configuration, the fifth switch SW5 is also off.

[0073] Therefore, in Figure 3B In the arrangement, sampling transistor M S The gate terminal is provided with a potential difference and voltage level V stored across the capacitor C1. DD2 The sum of these voltage levels defines the voltage level. Specifically, the sampling transistor M... S The voltage level at the gate terminal can be expressed as V DD2 +(V DD1 -V a ).

[0074] Therefore, the sampling transistor M in the output configuration S The gate-source voltage can be expressed as V DD2 +(V DD1 -V a )-V IN Typically, the defined current, capacitor, clock signal, and voltage levels at the first and second voltage reference nodes can be configured such that the difference between the voltage levels supplied at the gate and source terminals of the sampling transistor when the switching circuit system is in the output configuration is greater than or equal to the threshold voltage of the sampling transistor. This makes the sampling transistor M... S Switch to conduction and enable sampling capacitor C S Voltage tracking input signal V at both ends IN .

[0075] As mentioned earlier, the current source 120 can be a controllable current source and is controlled by the input voltage signal V. IN Control (first mode) to ensure a limited current I D Depends on the input voltage signal V IN (For example, with the input voltage signal V) IN (Proportional). In this case, the voltage V a Possibly related to V IN Inversely proportional, causing the gate-source voltage (V) of the sampling transistor in the output configuration to be... DD2 +(V DD1 -V a )-V IN ) becomes with V IN Basically irrelevant (i.e., V) GS It is constant). That is to say, although the above V GSThe voltage equation includes V IN But V GS With V IN It's irrelevant because V a With V IN It is inversely proportional. This reduces or minimizes the input-related on-resistance variation of the sampling switch.

[0076] However, as mentioned earlier, current source 120 is not necessarily a controllable current source, or current source 120 is affected by the input voltage signal V. IN Control. A controllable current source can be configured such that a defined current depends on a control signal, wherein the control signal is related to V. IN Irrelevant (Second Mode). For example, in current source 120, which is a controllable current source and is subject to the input voltage signal V. IN Different (e.g., in the second mode, with the input voltage signal V) IN When controlled by an unrelated control signal, the gate-source voltage (V) of the sampling transistor in the output configuration is... DD2 +(V DD1 -V a )-V IN It may retain the input voltage signal V IN Some dependencies (i.e., V) GS With V IN (Change). However, for the input voltage signal V IN This kind of dependency can be acceptable in some arrangements.

[0077] Regardless of whether current source 120 is subject to input voltage signal V IN Controllable current source, and Figure 1 and Figure 2 Compared to the sampling switch circuit, it has the advantages associated with the sampling switch circuit 100.

[0078] In particular, one advantage is that, by using current source 120, considering the high impedance input to current source 120 when it is controlled, even when it is subjected to input voltage signal V IN During control, the sampling transistor (sampling switch) M S The input load is also reduced, which allows for use in large arrays, for example. The current source 120 is supplied by the input voltage signal V. IN Under controlled conditions, since the current source effectively acts as a buffer, the high impedance input to the current source 120 causes the input node of the sampling switch circuit 100 (labeled V) to be blocked. IN The load is reduced.

[0079] Furthermore, when using one or more transistors (as detailed later in this document) to implement the current source 120, due to the sampling transistor M in the pre-charge configuration...S The gate terminal of the transistor is not driven, so such a transistor (and any transistors used to implement switches SW1 and SW2) can be relatively small. Conversely, any transistors used to implement switches SW3 and SW4 can be relatively large to efficiently drive the sampling transistor M without affecting the load at the control input of current source 120 (or the input node of sampling switch circuit 100). S The gate terminal, wherein the current source 120 is subjected to the input voltage signal V IN control.

[0080] For similar reasons, as mentioned earlier, V DD2 Voltage levels can be higher than V DD1 Voltage level, to achieve sampling transistor M S Strong drive of the gate terminal. Due to the pre-charge configuration, the sampling transistor M S The gate terminal is not driven, and because the potential difference stored in capacitor C1 is controlled during the multiple pre-charge cycles as previously mentioned, V DD1 Voltage levels can be lower than V DD2 Voltage level. Furthermore, this enables the control of the voltage level V. DD2 +(V DD1 -V a )-V IN (i.e. V) DD2 ≠V DD1 Another way.

[0081] Figure 4 This shows how to understand Figure 3 A schematic diagram of a possible implementation of the current source 120 is shown. For simplicity, only the current source connected between SW1 and the ground reference node is shown.

[0082] For ease of comparison, Figure 4 This illustrates the situation where the current source is not controllable (second mode). Figure 3 The current source 120 is the same as the current source 120A. Current source 120B, an implementation of current source 120A, is also shown, in this case as a field-effect transistor, with its gate terminal connected to a reference voltage V. REF The reference voltage V REF A limited current I was defined. D V REF It can be a constant DC voltage signal to provide a constant (uncontrollable) current.

[0083] Alternatively, the current source can be controlled. The current of the current source can be controlled using a control signal. The control signal may include a control voltage signal (CVS), and the controllable current source can be configured such that a defined current depends on the voltage level of the control voltage signal.

[0084] Figure 4 This illustrates the case where the current source can be controlled by the control signal CS. Figure 3 The current source 120C is shown as a current source 120C. Current source 120D, an implementation of current source 120C, is also shown. Typically, a controllable current source may include at least one transistor connected to control a defined current based on the gate voltage of the at least one transistor, and the at least one transistor of the controllable current source is connected such that the gate voltage of the at least one transistor depends on a control signal. In this case, 120D includes a field-effect transistor whose gate terminal is connected to a control voltage signal CVS, which defines a defined current I. D .

[0085] The control signal may include a control digital signal (CDS), and the controllable current source can be configured such that the defined current depends on the digital value of the control digital signal. As shown by the dashed line in current source 120D, a control voltage signal CVS can be generated by a digital-to-analog converter (DAC) based on the control digital signal CDS. The control voltage signal CVS (and the control digital signal CDS) may be the input voltage signal V. IN Or it may depend on the input voltage signal V IN (First mode). The control voltage signal CVS (and the control digital signal CDS) can be compared with the input voltage signal V. IN Irrelevant (Second Mode).

[0086] Figure 4 The diagram shows a current source 120E representing a current source 120C, where the control signal CS is (or depends on) the input voltage signal V. IN (First mode). An implementation of current source 120F, i.e., current source 120E, is also shown, in this case as a field-effect transistor with its gate terminal connected to the input voltage signal V. IN The input voltage signal V IN Limited current I D Of course, although not shown, the input voltage signal V can be generated by a digital-to-analog converter (DAC) in the same or similar manner as the current source 120D, based on the corresponding digital signal. IN .

[0087] As described, the current source may include at least one transistor. The third and fourth switches of circuit 100 may be larger than at least one transistor (of the current source) and optionally larger than the first and second switches. The third and fourth switches may be larger in size than at least one transistor (of the current source) and optionally the first and second switches, and therefore also larger in gate capacitance. Thus, the transistor sizes along the respective current paths determined by the first pair of switches and the second pair of switches include smaller transistors along the signal path in the pre-charge configuration and larger transistors along the signal path in the output configuration.

[0088] Figure 5 A schematic diagram is shown that helps to understand the current source 120 and, in fact, any of the current sources 120B, 120D, and 120F.

[0089] Figure 5 The current source 120G is shown, which is implemented as a field-effect transistor with respect to current sources 120B, 120D and 120F, and it is simply indicated that source degradation can be applied (by means of a resistor R1 connected in series with the source terminal of the transistor).

[0090] Typically, a controllable current source may include multiple transistors connected to control a defined current based on their respective gate voltages, and the multiple transistors of the controllable current source may be connected such that their gate voltages depend on a control signal.

[0091] Figure 5 A current source 120H with multiple current sources is shown, implemented as field-effect transistors connected in series and correspondingly controlled by their gate terminals. Current source 120H can be understood as a single current source implemented with multiple field-effect transistors. A current source 120I is also shown, indicating that the current source can be implemented as a parallel arrangement (or array) of field-effect transistors connected in parallel and correspondingly controlled by their gate terminals. All transistors in the parallel arrangement (or array) are connected between a shared node (i.e., switch SW1) and a shared reference voltage node (i.e., GND). Of course, a combination of series and parallel connections of field-effect transistors can also be used.

[0092] Figure 6 This is a schematic diagram that helps to understand another possible implementation of the current source 120, and shows the current source 120J implemented as a field-effect transistor consistent with the current source 120I in parallel connection.

[0093] In this case, the current source 120J is a controllable current source, and its control signal CS includes the input voltage signal V. INExample bits b0 to bn of the digital control signals. The leftmost transistor is controlled by the input voltage signal V. IN The control signal is used to control the remaining transistors, which are controlled by bits b0 to bn. The dimensions of the remaining transistors (controlled by bits b0 to bn) can be binary-weighted in accordance with the binary weighting of bits b0 to bn. As shown by bit bn and the dashed line between transistors b1 and bn, the digital control signal can have any number of bits, and the total number of transistors is adjusted accordingly.

[0094] When I is needed D In the case of digital control, implementing 120I and 120J can be useful.

[0095] An example variant implementing 120J could include individual switches controlled by bit signals b0 to bn, which then control (based on the associated bit value) the gate of their corresponding transistors to be connected to V. IN It is still connected to ground (GND). In this case, when all bit signals b0 to bn are selected (i.e., have a logic value of 1), all of the gates can be connected to V. IN And when any of the bit signals b0 to bn is disabled (i.e., has a logic value of 0), their corresponding transistors can have their gates connected to ground (GND). Additional DAC / reference voltages may be unavailable (e.g., due to space, power, or the number of parallel bootstrap circuits). In this case, binary scaling of the additional parallel devices enables the bit signals b0 to bn to be used to implement a current-driven DAC. In this case, V IN It can be shared by parallel bootstrap circuits and can be connected via a reference current I. REF Generate, where I REF This can be a controllable current signal. For example, such a reference current I can be provided at the drain terminal of a diode-connected field-effect transistor. REF Its drain terminal is connected to ground (GND) and its gate voltage is used as V. IN .

[0096] Figure 7 This is a schematic diagram illustrating the sampling switch circuit 200 of the present invention. The sampling switch circuit 200 may be referred to as, for example, a sampling circuit, a switching circuit, a sampler circuit, a sampler front-end circuit, an ADC front-end circuit, a sample-and-hold circuit, or a sample-and-hold switch circuit, and the present disclosure will be understood accordingly.

[0097] The sampling switch circuit 200 can be considered an example implementation of the sampling switch circuit 100, and similarly, similar components have been indicated with similar reference numerals. The basic structure of the circuit can be described with respect to... Figure 3 A comparison is made, where, for ease of understanding, with Figure 3Similarly, mark the components.

[0098] As explained above, circuit 200 is connected to... Figure 3 It operates in a similar manner, wherein a protection circuit 240 is added to help prevent the voltage across a given transistor from exceeding the safe operating range. The protection circuit 240 is indicated by a dashed box surrounding transistors M7 through M9, an additional voltage reference node, and capacitor C2. Depending on the application, the protection circuit 240 may not be required, as will be commented on later.

[0099] Detailed description Figure 7 Similar to circuit 100, circuit 200 includes input node V. IN The system consists of a sampling transistor (sampling switch), capacitor C1, current source 220, switching circuitry (in the form of transistors M1 to M6), and output node V. OUT .

[0100] and Figure 3 Similarly, the input node is connected to receive the input voltage signal V to be sampled. IN Sampling transistor M S It includes a gate terminal, a source terminal, and a drain terminal, with the source terminal connected to the input node.

[0101] Current source 220 is configured to make a defined current I D The current flows through it and can be a controlled or uncontrolled current source as previously described, or... Figures 4 to 6 Any current source configuration shown.

[0102] Capacitor C1 includes capacitors labeled A and B (corresponding to...) Figure 3 The first and second terminals (a and b) in the diagram can be considered as a first capacitor. The switching circuit system includes first transistors to sixth transistors M1 to M6. Such transistors are implemented as MOSFETs, but can be any other type of transistor.

[0103] The first transistor M1 and the second transistor M2 can be considered as the first pair of switches (and are related to) Figure 3 (Comparing SW1 and SW2 in the diagram), and the third transistor M3 and the fourth transistor M4 can be considered as the second pair of switches (and with...). Figure 3 (Compare SW3 and SW4 in the diagram). The fifth transistor M5 and the sixth transistor M6 can work together with... Figure 3 The switch SW5 in the circuit is compared. Transistors M7 through M9 can be considered as a group of protective switches, or switches forming part of the protection circuit 240. Each of transistors M1 through M9 includes a gate terminal, a source terminal, and a drain terminal.

[0104] To fully understand the operation of circuit 200 as detailed below, transistors M1 to M9 will be described in terms of the operation of N-type MOSFETs and P-type MOSFETs relative to clock signals CLK and / CLK. In this configuration, the N-type transistor is turned on when the gate signal is high (HIGH) or on (ON), and turned off when the gate signal is low (LOW) or off (OFF). The P-type transistor is turned on when the gate signal is low or off, and turned off when the gate signal is high (HIGH) or on (ON).

[0105] It will be understood that in other implementations, the type of MOSFET used and the clock signal can be varied together (i.e., using clock signal CLK with an N-type transistor instead of clock signal / CLK with a P-type transistor) to achieve the same functionality in a given precharge configuration or output configuration.

[0106] Focusing on the first pair of switches, the first transistor M1 is connected between the first terminal A of capacitor C1 and the current source 220, and the second transistor M2 is connected between the second terminal B of capacitor C1 and the first voltage reference node V. DD1 Between. Current source 220 is connected between the first transistor M1 and another reference voltage node, which can be considered as a ground voltage reference node (GND). Transistor M1 is an N-type transistor, and transistor M2 is a P-type transistor. Transistor M1 has its gate terminal connected to the clock signal CLK.

[0107] Switching to the second pair of switches, the third transistor M3 is connected between the first terminal A of capacitor C1 and the second voltage reference node V. DD2 Between, and the fourth transistor M4 is connected to the second terminal B of capacitor C1 and the sampling transistor is marked as node C (corresponding to Figure 3 The gate terminals of node c) are connected to each other. Node C is also connected to the gate terminal of transistor M2. Transistors M3 and M4 are P-type transistors. Transistor M3 has its gate terminal connected to the clock signal CLK.

[0108] like Figure 3 As shown, the first voltage reference node V DD1 Configured to provide a first reference voltage signal, and a second voltage reference node V DD2 It is configured to provide a second reference voltage signal, which can be a DC (supply) voltage signal. As before, node V DD1 and V DD2The voltage levels at these points can be the same or different from each other. The ground voltage reference node GND is configured to provide a ground reference voltage signal, which can be a DC (supply) voltage signal. Nominally, the voltage level at the ground voltage reference node GND can be referred to as 0V. For convenience, node V... DD1 and V DD2 The (supply) voltage level at a point can be referred to as V. DD1 and V DD2 .

[0109] The sixth transistor M6 is connected between the gate terminal of the sampling transistor, i.e., node C, and the fifth transistor M5, and the fifth transistor M5 is connected between the sixth transistor M6 and the third reference voltage node. The third reference voltage node can also be the ground voltage reference node (GND) as indicated, but in other arrangements, the third reference voltage node can provide a DC voltage signal with a voltage level different from the ground voltage (i.e., 0V).

[0110] Transistor M5 (or a combination of fifth transistor M5 and sixth transistor M6) can be described as a holding switch connected between the gate terminal of the sampling transistor and a third reference voltage node. In the precharge configuration, the holding switch is on, and in the output configuration, the holding switch (M5) is off. The third reference voltage node is configured to provide a third reference voltage signal, which may optionally be a DC voltage signal and may optionally have a voltage level such that the difference between the voltage levels provided at the gate and source terminals of the sampling transistor when the switching circuit system is in the precharge configuration is less than that provided at the gate terminal of the sampling transistor M5. S The threshold voltage. This voltage causes the sampling transistor M... S Turn off.

[0111] Transistor M5 indicates Figure 3 Transistor M5 is connected to transistor M6, which is placed between node C and M5 to protect transistor M4. This is because the drain-source voltage on transistor M4 may exceed its safe operating range, where a relatively large voltage is seen at the source terminal of transistor M4 due to the charging of capacitor C1, and a relatively low voltage (i.e., GND) is seen at the drain terminal of transistor M4 through transistor M5. Transistors M5 and M6 are N-type transistors. Transistor M5 has its gate terminal connected to the clock signal CLK, and transistor M6 has its gate terminal connected to a constant voltage source V. DD The gate terminal.

[0112] The set of protective switches M7 to M9, together with an additional reference node and capacitor C2, form protection circuit 240. Capacitor C2 can be described as a second capacitor. Capacitor C2 is connected between node B and transistor M9, where transistor M9 is also connected to another reference node (i.e., GND). Transistor M8 is connected between transistor M9 and the gate terminal of transistor M4, labeled node D. Transistor M7 is connected between node D and another reference voltage node V. DD Between. The switching circuit 100 can be considered as the sampling transistor M. S In the same manner as the bootstrap circuit, the protection circuit 240 can be considered as the bootstrap circuit of transistor M4. Transistor M7 is a P-type transistor, and transistors M8 and M9 are N-type transistors. Transistors M7 and M8 have their respective gate terminals connected to the clock signal / CLK, and transistor M9 has its gate terminal connected to the clock signal CLK.

[0113] like Figure 3 As shown, the sampling capacitor C S Connected to sampling switch M S The drain terminal is used as the output node, and the output signal V is generated at the drain terminal. OUT Sampling capacitor C S Connected between the drain terminal and another reference voltage node, as shown, this other reference voltage node can also be a ground voltage reference node (GND). Although in some arrangements the sampling capacitor C S It is indicated as a discrete component, but it can be a parasitic capacitance.

[0114] Similar to circuit 100, circuit 200 is configured to operate in a precharge configuration and an output configuration (switching or alternating between the precharge configuration and the output configuration) according to a clock signal CLK. In the precharge configuration, the switching circuitry of sampling switch circuit 200 connects capacitor C1 to current source 220 and the first voltage reference node V. DD1 In the current path between them, a current I is formed across capacitor C1 that depends on a defined current. D The potential difference. In the output configuration, the switching circuitry connects capacitor C1 to the second voltage reference node V. DD2 Between the sampling transistor and its gate terminal, such that the voltage level applied at the gate terminal of the sampling transistor, i.e., node C, depends on a defined current I. D .

[0115] When CLK is high (e.g., V) DD When / CLK is low (e.g., GND), the switching circuitry is configured into a precharge configuration.

[0116] In this configuration, the first transistor M1 is turned on and the third transistor M3 is turned off. Both the fifth transistor M5 and the sixth transistor M6 are turned on, and thus the switching circuitry is configured to connect the gate terminal of the sampling transistor to a third voltage reference node, such that the voltage level applied to the gate terminal of the sampling transistor in the pre-charge configuration depends on the voltage level provided at the third voltage reference node. Figure 7 In the diagram, node C is supplied with ground voltage (i.e., GND) through transistors M5 and M6. This ground voltage at node C turns on transistor M2, supplying voltage V to node B. DD1 And provide voltage V to the first terminal of capacitor C2. DD1 Transistor M7 is turned on, and transistor M8 is turned off, thus supplying voltage V to node D through transistor M7. DD This turns off transistor M4. Transistor M9 turns on and provides ground voltage to the second terminal of capacitor C2.

[0117] In this arrangement, therefore, the sampling transistor M is fed through node C. S The gate terminal provides ground voltage, and the sampling transistor M S It is controlled to be off, so that the sample (presents a value based on V from the previous clock cycle) IN The potential difference (in the form of) is maintained at the sampling capacitor C. S superior.

[0118] Similarly, in the pre-charge configuration, capacitor C1 is connected to current source 220 and the first voltage reference node V. DD1 In the current path between. As previously mentioned, it depends on the defined current I. D A potential difference is formed across capacitor C1. Specifically, the potential difference across capacitor C1 becomes related to the defined current I. D Proportional. For example, if the current I is limited. D Increase, the voltage V at node A A This will decrease, causing the potential difference V across capacitor C1 to... DD1 -V A It will increase.

[0119] The switching circuit system connects a second capacitor C2 to create a given potential difference across the second capacitor. Capacitor C2 is connected to node B (which is provided with a first reference voltage V) via transistor M9. DD1 In the current path between the voltage and ground, C2 is charged to voltage V. DD1 .

[0120] When CLK is low and / CLK is high, the switching circuitry is configured in the output configuration.

[0121] In this configuration, the first transistor M1 is off, and the third transistor M3 is on. The fifth transistor M5 is off (the sixth transistor M6 remains on), and therefore node C is no longer supplied with ground voltage (i.e., GND). Transistor M7 is off, transistor M8 is on, and transistor M9 is off, and therefore transistor M9 no longer supplies ground voltage to the second terminal of capacitor C2. Therefore, node D is connected to the second terminal of capacitor C2, and the switching circuit connects the second capacitor C2 between the gate terminal (node ​​D) and source terminal (node ​​B) of the fourth transistor (switch) M4, such that the gate-source voltage of the fourth transistor (switch) M4 is limited by the potential difference stored across the second capacitor C2 at the end of the pre-charge phase, and becomes an effective Vo. DD1 The V DD1 Turn on the fourth transistor (switch) M4.

[0122] In this arrangement, the sampling transistor M is fed through transistor M4 and node C. S The gate terminal (node ​​C) provides a voltage V DD2 +(V DD1 -V A (Turn off transistor M2), and sample transistor M S It is controlled to be turned on, so that the sampling transistor M S The drain terminal and sampling capacitor C S Tracked samples (presented with V) IN (in the form of potential difference).

[0123] Note that if the protection circuit 240 is removed and the gate terminal of the fourth transistor (switch) M4 is driven by the clock signal CLK, the magnitude of the gate-source voltage of the fourth transistor (switch) M4 in this arrangement will become V. DD2 +(V DD1 -V A This is the same voltage level as at node B, and this may exceed the operating limit of the gate-source voltage of the fourth transistor (switch) M4. By providing protection circuit 240, the magnitude of the gate-source voltage of the fourth transistor (switch) M4 in this arrangement becomes V as described above. DD1 This keeps the gate-source voltage within acceptable limits. In some arrangements, as previously mentioned, the protection circuit 240 may be unnecessary, and the gate terminal of the fourth transistor (switch) M4 may be driven by the clock signal CLK.

[0124] Similar to circuit 100, in circuit 200, the sampling transistor M in the output configuration S The gate-source voltage can be expressed as V DD2 +(V DD1 -VA )-V IN Similarly to circuit 100, in circuit 200, current source 220 can be a controllable current source and is connected to an input voltage signal V. IN Control (first mode) to ensure a limited current I D Depends on the input voltage signal V IN (For example, with the input voltage signal V) IN (Proportional). In this case, the voltage V A Possibly related to V IN Inversely proportional, causing the gate-source voltage (V) of the sampling transistor in the output configuration to be... DD2 +(V DD1 -V A )-V IN ) becomes with V IN Basically unrelated (i.e., V) GS (It is constant). Similarly, current source 220 is not necessarily a controllable current source, or necessarily subject to the input voltage signal V. IN Control. A controllable current source can be configured such that a defined current depends on a control signal, wherein the control signal is related to V. IN Irrelevant (Second Mode). For example, in current source 220, which is a controllable current source and is subject to the input voltage signal V. IN Different (e.g., in the second mode, with the input voltage signal V) IN When controlled by an unrelated control signal, the gate-source voltage (V) of the sampling transistor in the output configuration is... DD2 +(V DD1 -V A )-V IN It may retain the input voltage signal V IN Some dependencies (i.e., V) GS With V IN (Changes). However, as before, for the input voltage signal V IN This kind of dependency can be acceptable in some arrangements.

[0125] Focusing on the first mode, in which the current source 220 is subjected to the input voltage signal V IN Under controlled conditions, the voltage (V) at the gate of the sampling transistor DD2 +(V DD1 -V A As described above, via V A Having V IN The dependence of the input voltage signal V during the precharge configuration clock cycle, i.e., at a time before the subsequent output configuration clock cycle. IN The influence stored in the sampling capacitor C SWhen the voltage is applied, the relevant component (V) A The capacitor C1 is charged. This component can be described as V. IN,T-1 This value depends on V at the pre-charge configuration period prior to the output configuration. IN Due to the input signal V IN and V IN The components at the gate terminal are taken from different clock cycles (especially half a clock cycle), therefore the input signal V IN With V IN,T-1 Small differences may exist between the values ​​of V. In other words, V IN The value may vary slightly between the precharge configuration and the output configuration, and the sampling transistor M S V at the source extreme IN The value may be related to the value in the sampling transistor M S V seen at the gate terminal IN The components are different (or out of phase), thus introducing an error. However, it will be understood that when the clock frequency is (much) greater than the input signal frequency, such a difference can be considered negligible, and in any case, this error may be non-critical in some applications.

[0126] In Figure 2 In bootstrap circuits similar to those used in other bootstrap circuits, when V... IN Before being added to and applied to the gate of the sampling transistor, it can be charged to the supply voltage V using a capacitor. DD Compared to such a circuit, Figure 3 and Figure 7 The capacitor C1 in the middle is first charged to V. IN The value, then add V. DD (Specifically, V DD2 In addition to the increased input impedance and reduced signal load previously described, the benefit of this implementation is that a smaller (lower capacitance) transistor can be used for V during the pre-charge configuration. IN Signal path, and during output configuration, when driving sampling transistor M S Larger transistors (with higher capacitance) can be used on the output path. This allows the circuit to operate at higher frequencies and over a wider bandwidth.

[0127] As mentioned above, and to avoid any doubt, the transistors described herein can be implemented as field-effect transistors or any other type of transistor. The transistors can also be implemented as MOSFET-type transistors.

[0128] This disclosure also extends to multi-channel sampling circuit systems, including multiple sampling switch circuits. These multiple sampling switch circuits may correspond to multiple channels arranged for time-interleaved operation. It should be understood that such a configuration can be used as the front end of a time-interleaved ADC.

[0129] Figure 8 An example of a multi-channel sampling circuit 300 is shown. Each channel can have its own sampling switch circuit, shown as sampling switch circuit 100 for simplicity, where n corresponds to the number of channels. The input node V of each channel... IN They can be connected together to form a common input node V IN (As shown) and receive the same input voltage signal from each other. It will be understood that a multi-channel sampling circuit can have any number of channels n.

[0130] like Figure 8 As shown, the first reference voltage V DD1 Second reference voltage V DD2 and the power supply voltage V DD It can be shared by different channels (i.e., shared between different channels), or each channel can have its own first reference voltage V. DD1 Second reference voltage V DD2 and the power supply voltage V DD As mentioned above, in some arrangements, V DD1 and V DD2 Both can be equal to V DD In this case, only the supply voltage V needs to be provided. DD .

[0131] As before, the switching circuitry of each sampling switch circuit may include a controllable or uncontrollable current source. Figure 8 The (optional) control signal CS is shown as a common (shared) input to the switching circuitry system for channels 1 to n. The control signal CS input can be omitted, connected individually to each channel, or used in conjunction with the input signal V. IN The connection replacement allows the controllable current source in each channel to be configured to be controlled by V. IN control.

[0132] Each channel has its own output node and its own corresponding sampling capacitor C. S,n (Not shown).

[0133] Each channel's switching circuitry can be controlled by its own clock signal CLK and its own inverted clock signal / CLK (not shown). If the clock signals CLK1 to CLK... nIf (corresponding to channels 1 to n) is a set of time-interleaved clock signals, then channels 1 to n will time-interleave the input signal V. IN Sampling is performed. That is, multiple sampling switches (M) S,1 M S,2 ... M S,n —(not shown) is driven by n switching circuits (not shown), which are powered by n sampling clocks (CLK1, CLK2, ..., CLK). n ) drive. It will be understood that clock CLK and / CLK can be relative to Figure 3 The timing diagrams shown in the upper right corner vary in terms of their frequency and duty cycle for such a multi-channel configuration.

[0134] It will be understood that any single-channel sampling switch circuit configuration (circuit 100 or 200) disclosed herein or its use Figures 4 to 6 Any variation of those circuits configured with any current source can be used as the basis for a multichannel configuration.

[0135] As detailed above, the current source can be connected to the input signal V. IN Alternatively, it can be connected to the control signal CS, or even to a constant reference supply voltage. This effectively creates two different operating modes, referencing... Figure 9 and Figure 10 This allows for a better understanding of these two operating modes.

[0136] Figure 9 This diagram shows the voltage signal at node C of circuit 200 when circuit 200 operates in the first mode, where the current source is affected by the input signal V. IN Control. In this mode, the circuit controls... Figure 2 It operates in a similar manner to a bootstrap circuit. As can be seen from the diagram, the voltage seen at node C (and the voltage applied to the sampling transistor M) S (Voltage at the gate terminal) Tracking example input signal V IN In this case, the example input signal V IN It is a sine wave. Assume the example input signal V. IN It has a DC bias voltage of ~450mV, and is biased by V DD2 Applying ~0.9V, the DC bias voltage at node C increases to approximately 1.35V. Therefore, the sampling transistor M... S Gate-source voltage V GS It becomes approximately 0.9V (1.35–0.45).

[0137] As can be seen from a detailed consideration of the graph, the voltage level tracks the input signal V. INThe voltage alternates between a peak value and 0V, corresponding to the output configuration (sampling / tracking phase) and the precharge configuration (hold phase), respectively. This corresponds to clock signals CLK and / CLK, where, in the precharge configuration, the voltage seen at C is 0V, while in the output configuration, the voltage at node C (V... DD2 +(V DD1 -V A It is proportional to the input signal.

[0138] Figure 10 The diagram shows a graph of the voltage signal at node C of circuit 200 when circuit 200 operates in the second mode, where the current source is controlled by a (constant) reference voltage or control signal. Instead of tracking the voltage signal at node C... Figure 9 Using the same example input signal VIN, it can be seen that the peak value has the same height in each cycle, indicating a constant peak voltage. Since the reference signal or control signal of the control current source is constant, V... A The voltage remains constant, and capacitor C1 is always charged to the same voltage level. Because V IN The current source is not controlled, therefore the voltage supplied at node C is the same as that supplied and varies with time, V. IN Irrelevant.

[0139] Circuit 200 configured to operate in the second mode may be useful in some situations. For example, in the case of capacitor C S During charging, maintain sampling switch M S constant V at both ends GS It helps in the input signal V IN The switching resistance changes at both ends of the signal swing. When the signal swing is small enough but the input signal V... IN When the common mode is in the middle rail, for example, when V IN The swing is ~300mV but the common-mode voltage is 500mV (or higher), and therefore M S V on GS When the voltage changes from 250mV to 750mV, the V at 250mV is... GS It can be proven that it is very small. In these cases, by using M S The gate signal level is shifted by 250mV, M S It can provide V from 500mV to 900mV. GS If M S The device is sized accordingly, which is sufficient to avoid distortion (where the second mode reduces V). IN The load on the signal path is removed (i.e., the load is removed from the signal path). Furthermore, when it is greater than V... DD2 or V DD1 When the power supply is unavailable, this level will M SThe gate signal is shifted to V DD2 That's all. This further reduces the switch M. S The on-resistance allows switch M to... S It is implemented as a single NMOS (instead of, for example, where PMOS and NMOS devices are used in parallel and the input signal V). IN (There is an increased load on the complementary switch).

[0140] Of course, in the second mode, since V is no longer present in the gate voltage... IN Components, sampling transistor M S The gate voltage and therefore its gate-source voltage V GS No longer with V IN It's irrelevant. However, in some applications, such as the example above, this might be acceptable.

[0141] Figure 10 It can certainly be interpreted as being related to the first mode, in which V... IN It has a constant value, and therefore means that all peak values ​​of the voltage at node C over time are equal.

[0142] As mentioned above, the sampling switch circuit embodying the present invention can be implemented as part of an ADC, for example as the front end of an ADC, in order to generate the input signal V at a sampling rate defined by the clock signal CLK as described earlier. IN Voltage mode sample V OUT .

[0143] In summary, the above circuit is an example of a sample-and-hold bootstrap circuit, where the signal is applied to V during the pre-charge configuration. IN Proportional node A (or Figure 3 Node a) in the output is sampled and used as a reference voltage for the output configuration. Similar to... Figure 2 The bootstrap circuit precharges the capacitor to the supply voltage (V). DD And then, after the capacitor is charged, V is applied. IN However, in Figure 3 and Figure 7 In the topology, the capacitor is precharged to V IN A proportional voltage, and then the supply voltage (V) is applied. DD or V DD2 ).

[0144] It will now be apparent that capacitor C1 in circuits 100 and 200 represents something similar to... Figure 2 The bootstrap circuit has a capacitor, and capacitor C2 acts as a bootstrap capacitor for transistor M4, thereby helping transistor M4 to remain within its safe operating range.

[0145] If the circuit is used in the first mode, V IN The frequency may be lower than the clock CLK frequency. The frequency difference between the two signals is determined by the sampling transistor M. S The maximum output on-resistance variation is used to limit this. The voltage at node C is proportional to the sampled signal during pre-charge, and therefore at the beginning of the tracking cycle, the sampling transistor M... S V at the source extreme IN The value of the sampling transistor M S The component V at the gate terminal IN A difference exists between them. This difference relates to the input voltage signal V in the pre-charge configuration and the subsequent output configuration. IN The difference between them is proportional.

[0146] The circuit described above relates to a dual-purpose switching circuit, including two operating modes. The first mode involves tracking V... IN The second mode is related to the operation of the current source, and it is related to the operation of the current source by using a constant control signal.

[0147] The benefits of this circuit can include reduced load on the input signal, thanks to an effective buffer stage in the form of a current source 120 or 220. The input resistance can be relaxed and can be in the order of kiloohms.

[0148] Figure 11 This is a schematic diagram illustrating the ADC 1000 of the present invention. The ADC 1000 includes any of the sampling switching circuits disclosed herein; for simplicity, ... Figure 11 The value is 100, but of course, the sampling switch circuit 200 also applies. As shown, the ADC 1000 can be converted to a voltage-mode sample V. OUT Output digital signal.

[0149] Any circuit system disclosed herein can be implemented as an integrated circuit system or integrated circuit, for example, as an IC chip such as a flip chip (or as part thereof). Figure 12 This is a schematic diagram illustrating an integrated circuit system 2000 of the present invention. The integrated circuit system 2000 may include... Figure 11 The ADC 1000 and / or any sampling switch circuits previously disclosed herein (e.g., circuits 100 and 200), for simplicity, are described below. Figure 12 The value is 100.

[0150] Integrated circuit system 2000 may represent some or all of IC chips. The present invention extends to the aforementioned integrated circuit systems and IC chips, circuit boards including such IC chips, communication networks (e.g., Internet fiber optic networks and wireless networks) including such circuit boards, and network devices for such networks.

[0151] Within the spirit and scope of the appended claims, the invention may be embodied in many different ways based on the above disclosure.

Claims

1. A sampling switch circuit, comprising: The input node is connected to receive the input voltage signal to be sampled; A sampling transistor includes a gate terminal, a source terminal, and a drain terminal, the source terminal being connected to the input node; Capacitor; A current source configured to allow a defined current to flow through it; as well as The switching circuitry is configured to alternate between a precharge configuration and an output configuration based on a clock signal. in: In the pre-charge configuration, the switching circuit system connects the capacitor to the current path between the current source and the first voltage reference node to form a potential difference across the capacitor that depends on the defined current. and In the output configuration, the switching circuit system connects the capacitor between the gate terminal of the sampling transistor and a second voltage reference node configured to provide a DC voltage signal, such that the voltage level applied at the gate terminal of the sampling transistor depends on the defined current.

2. The sampling switch circuit according to claim 1, wherein, The current source is a controllable current source and is configured such that the defined current is a current dependent on the control signal.

3. The sampling switch circuit according to claim 2, wherein: The control signal includes a control voltage signal, and the controllable current source is configured such that the defined current depends on the voltage level of the control voltage signal; and / or The control signal includes a control digital signal, and the controllable current source is configured such that the defined current depends on the digital value of the control digital signal.

4. The sampling switch circuit according to claim 3, wherein, The control signal or the control voltage signal is the input voltage signal or depends on the input voltage signal.

5. The sampling switch circuit according to any one of claims 2 to 4, wherein: The controllable current source includes at least one transistor, which is configured to control the current based on the gate voltage of the at least one transistor; and The at least one transistor of the controllable current source is connected such that the gate voltage of the at least one transistor depends on the control signal.

6. The sampling switch circuit according to any one of claims 1 to 4, wherein: The capacitor includes a first terminal and a second terminal; The switching circuit system includes a first pair of switches and a second pair of switches; The first pair of switches includes a first switch connected between a first terminal of the capacitor and the current source, and a second switch connected between a second terminal of the capacitor and the first voltage reference node; and The second pair of switches includes a third switch connected between the first terminal of the capacitor and the second voltage reference node, and a fourth switch connected between the second terminal of the capacitor and the gate terminal of the sampling transistor.

7. The sampling switch circuit according to claim 6, wherein: The switching circuit system is configured such that, in the pre-charge configuration, the first switch and the second switch are turned on, and the third switch and the fourth switch are turned off, and in the output configuration, the first switch and the second switch are turned off, and the third switch and the fourth switch are turned on.

8. The sampling switch circuit according to claim 6, wherein, The first switch, the second switch, the third switch, and the fourth switch are implemented as transistors, optionally as field-effect transistors.

9. The sampling switch circuit according to claim 8, wherein, The current source includes at least one transistor, and wherein the third switch and the fourth switch are larger than the at least one transistor and optionally larger than the first switch and the second switch.

10. The sampling switch circuit according to claim 6, wherein: The fourth switch is a transistor comprising a gate terminal, a source terminal, and a drain terminal; The capacitor is the first capacitor; The sampling switch circuit includes a second capacitor; and In the pre-charge configuration, the switching circuit system is connected to the second capacitor to create a given potential difference across the second capacitor; and In the output configuration, the switching circuit system connects the second capacitor between the gate terminal and the source terminal of the fourth switch, such that the gate-source voltage of the fourth switch is limited by the given potential difference.

11. The sampling switch circuit according to any one of claims 1 to 4, wherein, The switching circuit system is configured, in the precharge configuration, to connect the gate terminal of the sampling transistor to a third voltage reference node such that the voltage level applied at the gate terminal of the sampling transistor in the precharge configuration depends on the voltage level provided at the third voltage reference node, the third reference voltage signal having a voltage level configured such that the difference between the voltage levels provided at the gate terminal and the source terminal of the sampling transistor is less than a threshold voltage of the sampling transistor.

12. The sampling switch circuit according to claim 11, wherein: The switching circuit system includes a hold switch connected between the gate terminal of the sampling transistor and the third reference voltage reference node; and The switching circuit system is configured such that the holding switch is on in the pre-charge configuration and the holding switch is off in the output configuration. Optionally, the holding switch is implemented as a transistor.

13. A multi-channel sampling circuit system, comprising a plurality of sampling switch circuits according to any one of the preceding claims, wherein: Each of the aforementioned sampling switch circuits is configured to operate based on its own clock signal; and The input nodes used in the sampling switch circuit are connected together to form a common input node and receive the same input voltage signal from each other.

14. An analog-to-digital converter, comprising a sampling switch circuit according to any one of claims 1 to 12 or a multi-channel sampling circuit system according to claim 13.

15. An integrated circuit system comprising a sampling switch circuit according to any one of claims 1 to 12, a multi-channel sampling circuit system according to claim 13, or an analog-to-digital converter according to claim 14.

16. The integrated circuit system of claim 15, wherein the integrated circuit system is an IC chip.

Images