Apparatus and method for improving accuracy of average power measurement of complex modulated signal

Abstract

The application discloses a device and method for improving average power measurement accuracy of complex modulation signals, and belongs to the field of microwave power measurement. The device comprises an FPGA, a high-speed chopping circuit and a driving circuit, and the FPGA, the driving circuit and the high-speed chopping circuit are sequentially connected through lines. The application adopts the high-speed chopping circuit and a digital chopping technology based on the FPGA, can basically perform data collection without losing points in one chopping period, simultaneously designs a variable chopping period, so that the measurement length is always an integer multiple of the complex modulation signal period and contains an integer number of chopping periods, and accurate measurement of the average power of the complex modulation signal is realized.

Description

Technical Field

[0001] This invention belongs to the field of microwave power measurement, specifically relating to a device and method for improving the accuracy of average power measurement of complex modulated signals. Background Technology

[0002] Chopper amplification technology is widely used in signal measurement due to its advantage in suppressing 1 / f noise. Microwave power measurement also uses this technology. The closest solution to this invention is to build a chopper circuit using discrete components, use a fixed chopper frequency to chop the power signal under test, and collect and process the effective data within a fixed measurement length (including several complete positive and negative chopper cycles).

[0003] Because the chopper circuit is built using discrete components, the overshoot introduced during chopper switching is difficult to handle, and the long tail of the overshoot drowns out the real signal. Therefore, a significant number of data points must be discarded, and only the valid data is used for calculation. Figure 1 As shown. Meanwhile, due to overshoot and tailing, the usable chopping frequency is typically in the hundreds of Hz, which is detrimental to 1 / f noise suppression. Furthermore, since the chopping period is invariant, and hundreds of Hz is close to the modulation frequency of most modulated signals, when the chopping period is close to the period of a complex modulated signal and not an integer multiple thereof, such as... Figure 2 The data obtained from each chopping cycle varies considerably, requiring multiple averagings to obtain a stable result, which is time-consuming. In summary, accurate measurement of the average power of complex modulated signals cannot be achieved. Summary of the Invention

[0004] In view of the above-mentioned technical problems in the prior art, the present invention proposes a device and method for improving the accuracy of average power measurement of complex modulation signals. The device and method are reasonably designed, overcome the shortcomings of the prior art, and have good effects.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] An apparatus for improving the accuracy of average power measurement of complex modulated signals includes an FPGA, a driving circuit, and a high-speed chopper circuit; the FPGA, the driving circuit, and the high-speed chopper circuit are connected sequentially via lines.

[0007] The FPGA is configured to generate chopped signals in digital form and to de-chop the chopped test signal.

[0008] The driving circuit is configured to convert the FPGA's CMOS level into a drive signal for a high-speed chopper circuit to achieve chopper control.

[0009] A high-speed chopper circuit, including a matrix switch, is configured to perform positive and negative chopping operations on the measured signal.

[0010] Preferably, the high-speed chopper switch employs a microwave mixer.

[0011] Preferably, the FPGA is configured with a time delay setting, which is set in the form of the number of ADCs.

[0012] Preferably, the FPGA is provided with an interface for setting the measurement length, which is used to receive the measurement time set by the user, and the chopper control module can automatically set the chopper period according to this value.

[0013] Furthermore, this invention also mentions a method for improving the accuracy of average power measurement of complex modulated signals. This method employs an apparatus for improving the accuracy of average power measurement of complex modulated signals as described above, and specifically includes the following steps:

[0014] Step 1: The FPGA receives the measurement length and sampling delay time;

[0015] Step 2: The FPGA determines the chopping period based on the received measurement length, generates a chopping signal with a 50% duty cycle in CMOS level format, and sends the chopping signal to the driver circuit.

[0016] Step 3: The driving circuit receives the CMOS level format chopper signal from the FPGA and converts the high and low levels of the CMOS signal into 3.3V and -3.3V levels respectively to drive the matrix switch;

[0017] Step 4: Upon initial startup, the FPGA uses its own chopping signal as the time base. After issuing the positive chopping drive signal, it starts accumulating the sampled values ​​after a fixed delay based on the sampling delay time. When the number of sampling points for half a chopping cycle is reached, the sampling points at the positive and negative chopping switching points are discarded, and then the sampling points are accumulated and subtracted. When the number of sampling points for the entire chopping cycle is reached, the result is stored.

[0018] Step 5: Discard the sampling points at the positive and negative chopping switching points, and then accumulate the sampling values ​​of the positive chopping cycle. When the number of sampling points for half a chopping cycle is reached, discard the sampling points at the positive and negative chopping switching points, and then accumulate and subtract the sampling points. When the number of sampling points for the entire chopping cycle is reached, store the result.

[0019] Step 6: Repeat step 5 until the set measurement length is reached, then the data acquisition is complete.

[0020] Preferably, the FPGA is provided with an interface for setting the measurement length, which is used to receive the measurement time set by the user, and the chopper control module can automatically set the chopper period according to this value.

[0021] The beneficial technical effects of this invention are as follows:

[0022] This invention employs a high-speed chopper circuit and FPGA-based digital chopper technology, enabling data acquisition with virtually no data loss within a single chopper cycle. Furthermore, the design of a variable chopper cycle ensures that the measurement length is always an integer multiple of the complex modulation signal, encompassing an integer number of chopper cycles. The sampling results within each measurement length are completely consistent and accurately reflect the measurement results, thus achieving accurate measurement of the average power of complex modulation signals. Attached Figure Description

[0023] Figure 1 This is a sample diagram illustrating effective data from existing technologies.

[0024] Figure 2 This is an example of how the frequency of the chopper signal is close to that of the signal being measured, leading to incorrect results in existing technologies.

[0025] Figure 3 This is a schematic diagram illustrating the implementation principle of the method of the present invention.

[0026] Figure 4 This is a hardware schematic diagram of the method of the present invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0028] Example 1:

[0029] like Figure 3 As shown, a device for improving the accuracy of average power measurement of complex modulated signals includes an FPGA, a driving circuit, and a high-speed chopper circuit; the FPGA, the driving circuit, and the high-speed chopper circuit are connected in sequence via lines.

[0030] FPGA is used to generate digital chopped signals and to de-chop the chopped test signals.

[0031] The driving circuit is used to convert the FPGA's CMOS level into a driving signal for the high-speed chopper circuit to achieve chopper control.

[0032] A high-speed chopper circuit, including a matrix switch, is used to perform positive and negative chopping operations on the measured signal.

[0033] Example 2:

[0034] Based on Embodiment 1 above, this invention proposes a method for improving the accuracy of average power measurement of complex modulated signals in microwave power measurement. Through a chopping measurement method with virtually no data loss and a variable period, accurate measurement of the average power of complex modulated signals is achieved, with a power measurement accuracy of less than 0.1 dB (average power 0 dBm measurement), thus meeting users' needs for accurate measurement of the average power of complex modulated signals. Details are as follows:

[0035] (1) Use microwave mixers as high-speed chopper switches to reduce the impact of switching.

[0036] Ordinary electronic switches have long on and off times and large overshoot during switching. To eliminate these disadvantages, a microwave mixer is used as a high-speed chopper switch. The driver circuit converts the FPGA's CMOS level into a drive signal for the mixer to achieve chopper control, such as... Figure 4 As shown. Actual measurements show a small and short overshoot, requiring only the sampling points during switch switching to be discarded. This allows the chopping frequency to reach a maximum of 50kHz, further suppressing 1 / f noise.

[0037] (2) FPGA-based chopper control and acquisition technology enables full data and variable period chopper acquisition.

[0038] a. Implementation of full data acquisition

[0039] Because a microwave mixer is used as the chopper switch, all sampled data, except for the sampling point during switch switching, reflects the information of the measured signal, i.e., all are valid data. However, in actual use, due to the effects of hardware circuit delay, ADC group delay, and FPGA internal data acquisition and processing delay, there is a time difference between the actual read-back ADC value of the measured signal and the chopper signal. If this effect is ignored and the chopper signal is directly used as a reference for de-chopping the sampled ADC, it will introduce a large error into the acquisition results. To ensure accurate measurement, all available sampling points should be used; therefore, a time delay setting is added to the FPGA, set in the form of the number of ADCs. The specific setting value can be obtained based on theoretical analysis and combined with actual engineering experiments.

[0040] b. Set the variable chopper period according to the measurement length.

[0041] The measurement results are most accurate when the measurement length is the same as or an integer multiple of the period of the complex modulation signal being measured. Therefore, this invention designs an interface for setting the measurement length in the FPGA to receive the user-defined measurement time. The chopper control module can automatically set the chopper period based on this value. Table 1 shows the correspondence between the chopper period and the measurement length in this invention.

[0042] Table 1

[0043] <![CDATA[Measure the length T mear > <![CDATA[Chopping period T chop > <![CDATA[20us≤T mear ≤100us]]> <![CDATA[T mear ]]> <![CDATA[100us<T mear ≤200us]]> <![CDATA[T mear / 5]]> <![CDATA[200us<T mear ≤1ms]]> <![CDATA[T mear / 10]]> <![CDATA[1ms<T mear ]]> 100us

[0044] This invention has virtually no data loss and can accurately measure the average power of complex modulated signals;

[0045] The variable chopping period can be set according to the measurement length to ensure the accuracy of the measurement results each time.

[0046] Of course, the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A method for improving the accuracy of average power measurement of complex modulated signals, characterized in that: A device for improving the accuracy of average power measurement of complex modulated signals is provided. The device includes an FPGA, a driving circuit, and a high-speed chopper circuit; the FPGA, the driving circuit, and the high-speed chopper circuit are connected sequentially by lines. The FPGA is configured to generate chopped signals in digital form and to de-chop the chopped test signal. The driving circuit is configured to convert the FPGA's CMOS level into a drive signal for a high-speed chopper circuit to achieve chopper control. A high-speed chopper circuit, including a matrix switch, is configured to perform positive and negative chopping operations on the measured signal. The high-speed chopper switch employs a microwave mixer. A time delay setting is configured in the FPGA, expressed as the number of ADCs. The FPGA also includes an interface for setting the measurement length, which receives the user-defined measurement time. The chopper control module can automatically set the chopping period based on the measurement time. The method specifically includes the following steps: Step 1: The FPGA receives the measurement length and sampling delay time; Step 2: The FPGA determines the chopping period based on the received measurement length, generates a chopping signal with a 50% duty cycle in CMOS level format, and sends the chopping signal to the driver circuit. Step 3: The driving circuit receives the CMOS level format chopper signal from the FPGA and converts the high and low levels of the CMOS signal into 3.3V and -3.3V levels respectively to drive the matrix switch; Step 4: Upon initial startup, the FPGA uses its own chopping signal as the time base. After issuing the positive chopping drive signal, it starts accumulating the sampled values ​​after a fixed delay based on the sampling delay time. When the number of sampling points for half a chopping cycle is reached, the sampling points at the positive and negative chopping switching points are discarded, and then the sampling points are accumulated and subtracted. When the number of sampling points for the entire chopping cycle is reached, the result is stored. Step 5: Discard the sampling points at the positive and negative chopping switching points, and then accumulate the sampling values ​​of the positive chopping cycle. When the number of sampling points for half a chopping cycle is reached, discard the sampling points at the positive and negative chopping switching points, and then accumulate and subtract the sampling points. When the number of sampling points for the entire chopping cycle is reached, store the result. Step 6: Repeat step 5 until the set measurement length is reached, then the data acquisition is complete.

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