High-speed data interface master-slave automatic switching logic control system and method

Abstract

A kind of high-speed data interface master-slave automatic switching logic control system and method, logic control system includes data sending FPGA, data mainboard, data backup board, backplane, peripheral device, data mainboard, data backup board obtains the state quantity related to power-on state by peripheral device after power-on and generates working state feedback signal, the state quantity related to power-on state is sent back to data sending FPGA by signal form by high-speed interconnection differential connector via backplane, data sending FPGA realizes data information interaction by high-speed interconnection differential connector using backplane, according to the power-on state related to state quantity, working state feedback signal analysis data mainboard, data backup board power-on state, sends the 1st group high-speed data to data mainboard or or sends the 2nd group high-speed data to data backup board, carries out master-slave data receiving switching.

Description

TECHNICAL FIELD

[0001] The application relates to a high-speed data interface master-slave automatic switching logic control system and method, and belongs to the technical field of visible light detection of remote sensing cameras. BACKGROUND

[0002] Visible light detection of remote sensing cameras is an active remote sensing detection technology, the data transmission code rate between functional components has reached the Ghz level, and in order to ensure the reliability of key functional components, master-slave design is required, and the system requires that when the master works and the slave does not work, only the master functional component can receive high-speed data, and the slave functional component interface is in a high resistance state; when the slave works and the master does not work, only the slave functional component can receive high-speed data, and the master functional component interface is in a high resistance state.

[0003] The high-speed data interface master-slave automatic switching and control logic design adopts few peripheral devices, and through strict logic design of a data sending FPGA, a data mainboard and a data backup board, high-reliability high-speed data master-slave interface design is realized, which has important significance for realizing high-reliability visible light detection of remote sensing cameras. SUMMARY

[0004] The application solves the technical problem that in the prior art, the relay element has the risk of mis-triggering and aging in a high-frequency switching state, and brings potential problems of switching failure.

[0005] The application solves the above technical problem by the following technical scheme:

[0006] The application solves the above technical problem by the following technical scheme:

[0007] The data sending FPGA sends two groups of consistent high-speed data to the backboard through a high-speed interconnection differential connector;

[0008] The data mainboard obtains power-on state related state quantities from peripheral devices after power-on, generates a working state feedback signal, and returns the power-on state related state quantities to the data sending FPGA through the backboard via the high-speed interconnection differential connector in the form of a signal; if there is a working state feedback signal generated by the data backup board, the working state feedback signal generated by the data backup board is merged and returned to the data sending FPGA through the backboard via the high-speed interconnection differential connector;

[0009] The data backup board obtains power-on state related state quantities from peripheral devices after power-on, generates a working state feedback signal, and returns the power-on state related state quantities to the data sending FPGA through the backboard via the high-speed interconnection differential connector in the form of a signal; if there is a working state feedback signal generated by the data mainboard, the working state feedback signal generated by the data mainboard is merged and returned to the data sending FPGA through the backboard via the high-speed interconnection differential connector;

[0010] The backboard realizes data information interaction among the data sending FPGA, the data mainboard, and the data backup board through the high-speed interconnection differential connector.

[0011] The data sending FPGA receives the merged working state feedback signal returned by the data mainboard and the data backup board, analyzes the power-on state of the data mainboard and the data backup board according to the power-on state related state quantities and the working state feedback signal, sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board, and performs main backup data receiving switching.

[0012] The peripheral devices include peripheral device RS and peripheral device RM, which correspond to the data backup board and the data mainboard, respectively. The peripheral device RM obtains power-on state related state quantity MEN with the data mainboard and sends it to the data sending FPGA through the backboard via the high-speed interconnection differential connector. The peripheral device RS obtains power-on state related state quantity SEN with the data backup board and sends it to the data sending FPGA through the backboard via the high-speed interconnection differential connector.

[0013] The data mainboard generates corresponding working state feedback signals including MCLK, SYN, and RST signals. The data backup board generates corresponding working state feedback signals including MCLK, SYN, and RST signals, which are merged into a group of working state feedback signals and sent to the data sending board.

[0014] In the data sending FPGA, an AND gate circuit is adopted, the data mainboard generates a high-level control signal MEN, the data backup board generates a low-level control signal SEN, the data sending FPGA performs logical AND operation on the high-level control signal MEN and the low-level control signal SEN through the AND gate to generate control enable signals MOE and SOE, and selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board according to the level of the control enable signals.

[0015] When the data mainboard is powered on and the data backup board is not powered on, the control enable signal MOE is high level, the control enable signal SOE is low level, the first group of high-speed data is sent to the data mainboard, and the second group of high-speed data transmission path is kept in high resistance state.

[0016] When the data backup board is powered on and the data mainboard is not powered on, the control enable signal MOE is low level, the control enable signal SOE is high level, the second group of high-speed data is sent to the data backup board, and the first group of high-speed data transmission path is kept in high resistance state.

[0017] A high-speed data interface master-slave automatic switching logic control method is realized through a logic control system, comprising:

[0018] The power-on state related state quantities of the data mainboard and the data backup board are obtained through peripheral devices, and corresponding working state feedback signals are generated according to the power-on state related state quantities;

[0019] Two working state feedback signals are received by the data sending FPGA, and are merged into a group of working state feedback signals through hot connection;

[0020] According to the working state feedback signals, the data sending FPGA selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board, and keeps the transmission path of the other group of high-speed data in high resistance state, thereby completing the master-slave data receiving switching.

[0021] The peripheral devices include a peripheral device RS and a peripheral device RM, which correspond to the data backup board and the data mainboard respectively, the peripheral device RM obtains the power-on state related state quantity MEN of the data mainboard and sends it to the data sending FPGA through the high-speed interconnection differential connector via the backplane, and the peripheral device RS obtains the power-on state related state quantity SEN of the data backup board and sends it to the data sending FPGA through the high-speed interconnection differential connector via the backplane.

[0022] In the data sending FPGA, an AND gate circuit is adopted, the data mainboard generates a high-level control signal MEN, the data backup board generates a low-level control signal SEN, the data sending FPGA performs logical AND operation on the high-level control signal MEN and the low-level control signal SEN through the AND gate to generate control enable signals MOE and SOE, and selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board according to the level of the control enable signals.

[0023] When the data mainboard is powered on and the data backup board is not powered on, the control enable signal MOE is high level, the control enable signal SOE is low level, the first group of high-speed data is sent to the data mainboard, and the second group of high-speed data transmission path is kept in high resistance state.

[0024] When the data backup board is powered on and the data mainboard is not powered on, the control enable signal MOE is low level, the control enable signal SOE is high level, the second group of high-speed data is sent to the data backup board, and the first group of high-speed data transmission path is kept in high resistance state.

[0025] Compared with the prior art, the application has the following advantages:

[0026] The application provides a high-speed data interface main backup automatic switching logic control system and method, by introducing two peripheral devices RM and RS, using the key function component power-on state to form state quantities MEN and SEN, in the FPGA internal logic design, according to MEN and SEN, the first group of data output or the second group of data output of the data sending FPGA is controlled, and meanwhile, the consistency of the data mainboard and the data backup board logic design is ensured, and the mutual information coordination work of multiple data sending FPGAs can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The application provides a high-speed data interface main backup automatic switching schematic diagram;

[0028] Figure 2 The application provides a high-speed data interface main backup automatic switching control logic schematic diagram; DETAILED DESCRIPTION

[0029] The application provides a high-speed data interface main backup automatic switching logic control system, which adopts few peripheral devices, realizes high-reliability high-speed data main backup interface design through strict logic design of the data sending FPGA, the data mainboard and the data backup board, has important significance for realizing high-reliability remote sensing camera visible light detection, and the logic control system specifically comprises:

[0030] The data sending FPGA sends two groups of consistent high-speed data to the backboard through a high-speed interconnection differential connector;

[0031] The data mainboard obtains power-on state related state quantities from peripheral devices after power-on, generates a working state feedback signal, and returns the power-on state related state quantities to the data sending FPGA through the backboard via the high-speed interconnection differential connector in the form of a signal; if there is a working state feedback signal generated by the data backup board, the working state feedback signal generated by the data backup board is merged and returned to the data sending FPGA through the backboard via the high-speed interconnection differential connector;

[0032] The data backup board obtains power-on state related state quantities from peripheral devices after power-on, generates a working state feedback signal, and returns the power-on state related state quantities to the data sending FPGA through the backboard via the high-speed interconnection differential connector in the form of a signal; if there is a working state feedback signal generated by the data mainboard, the working state feedback signal generated by the data mainboard is merged and returned to the data sending FPGA through the backboard via the high-speed interconnection differential connector;

[0033] The backboard realizes data information interaction among the data sending FPGA, the data mainboard, and the data backup board through the high-speed interconnection differential connector.

[0034] The data sending FPGA receives the merged working state feedback signal returned by the data mainboard and the data backup board, analyzes the power-on state of the data mainboard and the data backup board according to the power-on state related state quantities and the working state feedback signal, sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board, and performs main backup data receiving switching.

[0035] The following will be further described in combination with the drawings of the specification and the preferred embodiments:

[0036] In the current embodiment, the peripheral devices include peripheral device RS and peripheral device RM, which correspond to the data backup board and the data mainboard, respectively. The peripheral device RM obtains power-on state related state quantity MEN with the data mainboard and sends it to the data sending FPGA through the backboard via the high-speed interconnection differential connector. The peripheral device RS obtains power-on state related state quantity SEN with the data backup board and sends it to the data sending FPGA through the backboard via the high-speed interconnection differential connector.

[0037] The data mainboard generates corresponding working state feedback signals including MCLK, SYN, and RST signals. The data backup board generates corresponding working state feedback signals including MCLK, SYN, and RST signals, which are merged into a group of working state feedback signals through hard connection. For the data sending board, only one group of MCLK, SYN, and RST signals is needed, which come from the main data receiving board and the backup data receiving board and need to be merged on the hardware and sent to the data sending board.

[0038] In the data sending FPGA, an AND gate circuit is designed, the data mainboard generates a high-level control signal MEN, the data backup board generates a low-level control signal SEN, the data sending FPGA performs a logic AND operation on the high-level control signal MEN and the low-level control signal SEN to generate control enable signals MOE and SOE, and selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board according to the level of the control enable signals;

[0039] When the data mainboard is powered on and the data backup board is not powered on, the control enable signal MOE is high, the control enable signal SOE is low, the first group of high-speed data is sent to the data mainboard, and the second group of high-speed data transmission path is kept in a high-impedance state;

[0040] When the data backup board is powered on and the data mainboard is not powered on, the control enable signal MOE is low, the control enable signal SOE is high, the second group of high-speed data is sent to the data backup board, and the first group of high-speed data transmission path is kept in a high-impedance state;

[0041] According to the above-mentioned logic control system, a high-speed data interface master-slave automatic switching logic control method is proposed, which is realized by the logic control system and has the following steps:

[0042] The power-on state related state quantities of the data mainboard and the data backup board are obtained through peripheral devices, and corresponding working state feedback signals are generated according to the power-on state related state quantities;

[0043] Two working state feedback signals are received by the data sending FPGA, and are merged into a group of working state feedback signals through hot connection;

[0044] According to the working state feedback signal, the data sending FPGA selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board, and keeps the transmission path of the other group of high-speed data in a high-impedance state, thereby completing the master-slave data receiving switching;

[0045] The peripheral devices include a peripheral device RS and a peripheral device RM, which correspond to the data backup board and the data mainboard, respectively. The peripheral device RM obtains the power-on state related state quantity MEN from the data mainboard and sends it to the data sending FPGA through the high-speed interconnection differential connector via the backplane. The peripheral device RS obtains the power-on state related state quantity SEN from the data backup board and sends it to the data sending FPGA through the high-speed interconnection differential connector via the backplane.

[0046] In the data sending FPGA, an AND gate circuit is adopted, the data mainboard generates a high-level control signal MEN, the data backup board generates a low-level control signal SEN, the data sending FPGA performs logical AND operation on the high-level control signal MEN and the low-level control signal SEN through the AND gate to generate control enable signals MOE and SOE, and selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board according to the level of the control enable signals;

[0047] When the data mainboard is powered on and the data backup board is not powered on, the control enable signal MOE is high level, the control enable signal SOE is low level, the first group of high-speed data is sent to the data mainboard, and the second group of high-speed data sending path is kept in high resistance state;

[0048] When the data backup board is powered on and the data mainboard is not powered on, the control enable signal MOE is low level, the control enable signal SOE is high level, the second group of high-speed data is sent to the data backup board, and the first group of high-speed data sending path is kept in high resistance state.

[0049] The structure of the high-speed data interface main-backup automatic switching logic control system is shown in Figure 1 As shown in Figure 2 When the data mainboard is powered on and the data backup board is not powered on, the data mainboard generates a high-level control signal MEN, the data backup board generates a low-level control signal SEN, and in the data sending FPGA, MEN and SEN signals are respectively logically AND operated with the delayed power-on state signals through the AND gate to form the control enable signals MOE and SOE of the data output logic unit, at this time, the MOE signal is "high" and the SOE signal is "low", the first group of data output logic outputs the first group of high-speed data to the data mainboard when the MOE signal is "high", and the second group of data output is in high resistance state when the SOE signal is "low".

[0050] When the data mainboard is not powered on and the data backup board is powered on, the data mainboard generates a low-level control signal MEN, the data backup board generates a high-level control signal SEN, and in the data sending FPGA, MEN and SEN signals are respectively logically AND operated with the delayed power-on state signals through the AND gate to form the control enable signals MOE and SOE of the data output logic unit, at this time, the MOE signal is "low" and the SOE signal is "high", the first group of data output logic is in high resistance state when the MOE signal is "low", and the second group of data output outputs the second group of high-speed data to the data backup board when the SOE signal is "high".

[0051] Thus, the control logic formed by the data receiving FPGA power-on state is formed, the high-speed data interface automatic switching function is realized, and the power-off protection function of the data receiving FPGA is realized.

[0052] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall fall within the protection scope of the technical solutions of the present application.

[0053] The contents not described in detail in the specification of the present application belong to the known technology of the person skilled in the art.

Claims

1. A high-speed data interface master-slave automatic switching logic control system, characterized in that: it comprises a data sending FPGA, a data mainboard, a data backup board, a backboard and peripheral devices, wherein: the data sending FPGA sends two groups of completely consistent high-speed data to the backboard through a high-speed interconnection differential connector; after the data mainboard is powered on, the peripheral devices obtain power-on state related state quantities, the data mainboard generates a working state feedback signal, and the power-on state related state quantities are returned to the data sending FPGA through the backboard by the high-speed interconnection differential connector in the form of a signal; if there is a working state feedback signal generated by the data backup board, the working state feedback signal generated by the data backup board is merged and returned to the data sending FPGA through the backboard by the high-speed interconnection differential connector; after the data backup board is powered on, the peripheral devices obtain power-on state related state quantities, the data backup board generates a working state feedback signal, and the power-on state related state quantities are returned to the data sending FPGA through the backboard by the high-speed interconnection differential connector in the form of a signal; if there is a working state feedback signal generated by the data mainboard, the working state feedback signal generated by the data mainboard is merged and returned to the data sending FPGA through the backboard by the high-speed interconnection differential connector; the backboard realizes data information interaction among the data sending FPGA, the data mainboard and the data backup board through the high-speed interconnection differential connector; the data sending FPGA receives the merged working state feedback signal returned by the data mainboard and the data backup board respectively, analyzes the power-on state of the data mainboard and the data backup board according to the power-on state related state quantities and the working state feedback signal, sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board, and performs master-slave data receiving switching; the peripheral devices comprise peripheral device RS and peripheral device RM, which correspond to the data backup board and the data mainboard respectively, the peripheral device RM obtains power-on state related state quantity MEN with the data mainboard and sends it to the data sending FPGA through the backboard by the high-speed interconnection differential connector, and the peripheral device RS obtains power-on state related state quantity SEN with the data backup board and sends it to the data sending FPGA through the backboard by the high-speed interconnection differential connector; the data mainboard generates corresponding working state feedback signals including MCLK, SYN and RST signals, the data backup board generates corresponding working state feedback signals including MCLK, SYN and RST signals, which are merged into a group of working state feedback signals and sent to the data sending board; in the data sending FPGA, an AND gate circuit is designed, the data mainboard generates a high-level control signal MEN, the data backup board generates a low-level control signal SEN, the data sending FPGA performs logical AND operation on the high-level control signal MEN and the low-level control signal SEN to generate control enable signals MOE and SOE, and selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board according to the high-low level of the control enable signal. ​ ​ ​ ​ ​ ​ ​ ​ ​ When the data master board is powered on and the data backup board is not powered on, the control enable signal MOE is high, the control enable signal SOE is low, the first group of high-speed data is sent to the data master board, and the second group of high-speed data transmission path is kept in a high-impedance state; When the data backup board is powered on and the data master board is not powered on, the control enable signal MOE is low, the control enable signal SOE is high, the second group of high-speed data is sent to the data backup board, and the first group of high-speed data transmission path is kept in a high-impedance state; In the master-slave automatic switching control logic, when the data master board is powered on and the data backup board is not powered on, the data master board generates a high-level control signal MEN, and the data backup board generates a low-level control signal SEN. In the data sending FPGA, the MEN and SEN signals are logically ANDed with the delayed power-on state signals through an AND gate to form the control enable signals MOE and SOE of the data output logic unit. At this time, the MOE signal is "high", the SOE signal is "low", the first group of data output logic outputs the first group of high-speed data to the data master board when the MOE signal is "high", and the second group of data output is in an output high-impedance state when the SOE signal is "low"; When the data master board is not powered on and the data backup board is powered on, the data master board generates a low-level control signal MEN, and the data backup board generates a high-level control signal SEN. In the data sending FPGA, the MEN and SEN signals are logically ANDed with the delayed power-on state signals through an AND gate to form the control enable signals MOE and SOE of the data output logic unit. At this time, the MOE signal is "low", the SOE signal is "high", the first group of data output logic is in an output high-impedance state when the MOE signal is "low", and the second group of data output outputs the second group of high-speed data to the data backup board when the SOE signal is "high"; Thus, a control logic formed by the power-on state of the data receiving FPGA is formed to realize the automatic switching function of the high-speed data interface and realize the power-off protection function of the data receiving FPGA.

2. A method for controlling the automatic switchover of a high-speed data interface master-slave logic, implemented by means of the logic control system according to claim 1, characterized in that It includes: Obtaining the power-on state related state quantities of the data master board and the data backup board through peripheral devices, and generating corresponding working state feedback signals according to the power-on state related state quantities; Receiving two working state feedback signals by the data sending FPGA, and performing hot connection to merge them into a group of working state feedback signals; According to the working state feedback signal, the data sending FPGA selectively sends the first group of high-speed data to the data master board or the second group of high-speed data to the data backup board, and keeps the transmission path of the other group of high-speed data in a high-impedance state, thereby completing the master-slave data receiving switching; The peripheral device includes a peripheral device RS and a peripheral device RM, which correspond to the data backup board and the data master board respectively. The peripheral device RM obtains the power-on state related state quantity MEN from the data master board and sends it to the data sending FPGA through the high-speed interconnection differential connector via the backplane. The peripheral device RS obtains the power-on state related state quantity SEN from the data backup board and sends it to the data sending FPGA through the high-speed interconnection differential connector via the backplane. In the data sending FPGA, an AND gate circuit is adopted, a data mainboard generates a high-level control signal MEN, a data backup board generates a low-level control signal SEN, the data sending FPGA performs a logic AND operation on the high-level control signal MEN and the low-level control signal SEN to generate control enable signals MOE and SOE, and selectively sends the first group of high-speed data to the data mainboard or the second group of high-speed data to the data backup board according to the level of the control enable signals; When the data mainboard is powered on and the data backup board is not powered on, the control enable signal MOE is high level, the control enable signal SOE is low level, the first group of high-speed data is sent to the data mainboard, and the second group of high-speed data sending path is kept in high resistance state; When the data backup board is powered on and the data mainboard is not powered on, the control enable signal MOE is low level, the control enable signal SOE is high level, the second group of high-speed data is sent to the data backup board, and the first group of high-speed data sending path is kept in high resistance state.

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