Instruction obtaining method and device based on reduced instruction set and computer device

Abstract

This application relates to an instruction fetching method, apparatus, and computer device based on a reduced instruction set (RISC). The method includes: obtaining the address of the instruction to be executed; searching for the address of the instruction to be executed in a cache block group; if a first or second cache block is hit, reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the corresponding hit cache block; if a third or fourth cache block is hit, writing the instruction currently stored in the corresponding hit cache block into a free cache block in the first or second cache block; and reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group interconnected structure with the dual cache blocks that implement general read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity.

Description

Technical Field

[0001] This application relates to the field of basic electronic circuit technology, and in particular to an instruction fetching method, apparatus, computer device, storage medium and computer program product based on a reduced instruction set. Background Technology

[0002] Reduced Instruction Set Computer (RISC) architecture processors employ efficient pipelined operations, enabling parallel processing of instructions within the pipeline. The first step in the processor pipeline is "instruction fetch," which refers to the process by which the processor core reads instructions from external memory. To reduce the time consumed in the interaction between the processor core and external memory, an I-Cache (Instruction Cache) can be used to map instructions from external memory into a limited-capacity instruction cache.

[0003] The construction of instruction cache space utilizes the principle of locality, trading space for time to accelerate instruction fetching. On the one hand, a larger instruction cache space is beneficial to improving cache hit rate; on the other hand, a larger instruction cache space corresponds to higher power consumption and cost.

[0004] When the instruction cache capacity is limited, the processor core is prone to cache misses when accessing the cache to read instructions. Once a cache miss occurs, the data needs to be read from external memory again, resulting in a long delay. Summary of the Invention

[0005] Therefore, it is necessary to provide an instruction fetching method, apparatus, computer device, computer-readable storage medium, and computer program product based on a reduced instruction set to address the aforementioned technical problems, with the aim of improving the instruction fetching rate of the reduced instruction set.

[0006] In a first aspect, this application provides an instruction fetching method based on a reduced instruction set, implemented through a cache block group, the cache block group including a first cache block, a second cache block, a third cache block, and a fourth cache block, the method comprising:

[0007] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0008] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0009] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0010] In one embodiment, after reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed, the process includes:

[0011] If the instruction to be executed is a conditional jump instruction, determine whether there is a jump address for the conditional jump instruction in the cache block group;

[0012] If there is no jump address for a conditional jump instruction in the cache block group, read the next N instructions after the conditional jump instruction is executed from external memory, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0013] In one embodiment, after reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed, the method further includes:

[0014] If the instruction to be executed is an unconditional jump instruction, determine whether there is a jump address for the unconditional jump instruction in the cache block group;

[0015] If there is no jump address for an unconditional jump instruction in the cache block group, read the next N instructions after the unconditional jump instruction is executed from external memory and write them to the free cache blocks in the first and second cache blocks. Back up the discarded instructions in the free cache blocks to the fourth cache block. N is a positive integer not less than 1.

[0016] In one embodiment, the instruction fetching method based on the reduced instruction set further includes:

[0017] When all read and output instructions are non-jump instructions, for a double-buffered block consisting of a first buffer block and a second buffer block, while reading instructions through one buffer block, new instructions are cached through the other buffer block.

[0018] In one embodiment, before obtaining the address of the instruction to be executed, the method further includes:

[0019] Obtain the starting address of the instruction to be executed, burst-fetch the instruction from the starting address in the external memory, and write the burst-fetched instruction into the first cache block and the second cache block in sequence until both the first cache block and the second cache block are full.

[0020] In one embodiment, if the third or fourth cache block is hit, the method further includes:

[0021] Based on the address of the last instruction currently stored in the corresponding cache block, continue to prefetch instructions after the last instruction and write them into the free cache block;

[0022] When writing the currently stored instruction and the instructions after the last instruction to the free cache block, the instructions discarded in the free cache block are backed up to the fourth cache block.

[0023] Secondly, this application also provides an instruction fetching apparatus based on a reduced instruction set, which implements instruction fetching through a cache block group, the cache block group including a first cache block, a second cache block, a third cache block, and a fourth cache block, the apparatus comprising:

[0024] The PC lookup module is used to obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0025] The cache block read selection module is used to read and output the instruction to be executed corresponding to the address of the instruction to be executed in the first or second cache block when the first cache block or the second cache block is hit; and to write the instruction currently stored in the third or fourth cache block into the free cache block of the first or second cache block when the third or fourth cache block is hit, and to read and output the instruction to be executed corresponding to the address of the instruction to be executed in the free cache block.

[0026] In one embodiment, the instruction fetching device based on a reduced instruction set further includes:

[0027] The PC generation module is used to generate and output the address of the instruction to be executed before the PC lookup module obtains the address of the instruction to be executed. Specifically, the output address is zero during initialization, the output address is incremented sequentially during instruction execution, and the address of the instruction after the jump is output when an instruction jumps.

[0028] The preliminary decoding module is used to decode the instruction to be executed corresponding to the address of the instruction to be executed after the PC lookup module finds the address of the instruction to be executed in the cache block group. If the address of the instruction to be executed exists in the cache block group, the module will determine the type of the instruction to be executed and output the corresponding jump address if the type of the instruction to be executed is a jump instruction.

[0029] The PC prediction module is used to read the next N instructions after the jump instruction is executed from external memory when there is no jump address in the cache block group after the initial decoding module outputs the corresponding jump address, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block. N is a positive integer not less than 1.

[0030] The cache block write selection module is used to send a read request to the external interface driver module after the PC lookup module has searched for the address of the instruction to be executed in the cache block group. If the address of the instruction to be executed is not found in the cache block group, the module will write the instruction read by the external interface driver module from the external memory based on the read request into the corresponding cache block in the cache block group.

[0031] The external interface driver module is used to receive read requests from the cache block write selection module and, based on the read requests, burst read instructions to the external memory.

[0032] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0033] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0034] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0035] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0036] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0037] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0038] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0039] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0040] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0041] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0042] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0043] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0044] The aforementioned instruction fetching method, apparatus, computer device, storage medium, and computer program product based on Reduced Instruction Set Computing (RISC) implements instruction fetching through a cache block group consisting of four cache blocks. It obtains the address of the instruction to be executed and searches for it within the cache block group. If the first or second cache block is hit, the instruction to be executed corresponding to the current instruction address is read and output from the corresponding hit cache block. If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written to a free cache block in the first and second cache blocks. The instruction to be executed corresponding to the current instruction address is then read and output from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group connected to the dual cache blocks that implement general-purpose read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity. Attached Figure Description

[0045] Figure 1 This is an application environment diagram of an instruction fetching method based on a reduced instruction set in one embodiment;

[0046] Figure 2 This is a flowchart illustrating an instruction fetching method based on a reduced instruction set in one embodiment.

[0047] Figure 3 This is a flowchart illustrating the instruction acquisition steps based on a reduced instruction set in one embodiment.

[0048] Figure 4 This is a schematic diagram of a cache replacement strategy with unconditional jump in one embodiment;

[0049] Figure 5 This is a schematic diagram of a conditional jump cache replacement strategy in one embodiment;

[0050] Figure 6 This is a diagram of an instruction fetching device based on a reduced instruction set in one embodiment;

[0051] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] The instruction fetching method based on the Reduced Instruction Set Computing (RISC) provided in this application can be applied to, for example... Figure 1 In the application environment shown, the cache controller 200 is connected to the central processing unit 100, the cache memory 300, and the external memory 400. The cache controller 200, the central processing unit 100, the cache memory 300, and the external memory 400 can be contained within a terminal, which can be, but is not limited to, various personal computers, laptops, smartphones, and tablets.

[0054] In this embodiment, the cache memory 300 includes four cache blocks with fast read / write capabilities, all composed of Static Random Access Memory (SRAM) within the processor core. Specifically, the first and second cache blocks are large-capacity general-purpose read / write cache blocks, the third cache block is a small-capacity static predictive cache block, and the fourth cache block is a small-capacity sacrifice cache block. During the instruction fetching phase, the cache memory controller 200 obtains the address of the instruction to be executed and searches for it in the cache memory 300. If the first or second cache block is hit, the cache memory controller 200 reads the instruction to be executed corresponding to the address in the corresponding hit cache block and outputs it to the central processing unit 100. If the third or fourth cache block is hit, the cache memory controller 200 controls the writing of the instruction currently stored in the corresponding hit cache block into a free cache block in the first or second cache block. In the free cache block, the instruction to be executed corresponding to the address is read and output to the central processing unit 100.

[0055] In one embodiment, such as Figure 2 As shown, an instruction fetching method based on a reduced instruction set is provided, implemented through a cache block group. The cache block group includes a first cache block, a second cache block, a third cache block, and a fourth cache block. This method is applied to... Figure 1 The following steps are used as an example to illustrate the process of using the high-speed cache memory controller 200:

[0056] S220: Get the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group.

[0057] Here, the address of the instruction to be executed is the address of the instruction to be executed, which corresponds to the address of the instruction output by the PC generation module; searching for the address of the instruction to be executed in the cache block group means searching for the tag part of the cache line corresponding to each cache block in the cache block group.

[0058] The address of each instruction in memory space is called its Program Counter (PC). The address of the instruction to be executed is generated by the PC generation module. During initialization, the PC generation module outputs an address of zero. During sequential instruction execution, the address output by the PC generation module is incremented one instruction at a time. When a jump occurs, the PC generation module outputs the address of the instruction after the jump.

[0059] The PC lookup module is responsible for finding the address of the instruction to be executed in the cache block group. After receiving the address of the instruction to be executed, the PC lookup module searches the tag part of the corresponding cache line for each cache block. If the address is found, the lookup result flag of the corresponding cache block is updated.

[0060] In practical applications, while the PC generation module outputs the address of the instruction to be executed, it also sends the address to the PC lookup module, which then updates the lookup result flag in the hit cache block.

[0061] S240: If the first or second cache block is hit, read and output the instruction to be executed corresponding to the address of the instruction to be executed in the corresponding cache block.

[0062] Among them, "hitting the first or second cache block" means that the address of the instruction to be executed is found in the tag part of the first or second cache block; "reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed" means that the cache block read selector reads the correct instruction and outputs it for preliminary decoding based on the lookup result flag of the hit cache block.

[0063] In this embodiment, the first cache block and the second cache block are large-capacity general-purpose read-write caches. In practical applications, the cache block read selector reads the correct instruction result from the cache block group according to the search result flag updated by the PC search module and outputs it to the preliminary decoding module, which then performs simple decoding on the read instruction.

[0064] S260: If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0065] Among them, a third or fourth cache block hit means that the address of the instruction to be executed is found in the tag part of the third or fourth cache block; a free cache block refers to any cache block in the first or second cache block that has not been read or written.

[0066] In this embodiment, the third cache block is a small-capacity static prediction cache, which stores the statically predicted jump address when a conditional jump occurs. A third cache block hit indicates that a conditional jump instruction has occurred and the static prediction result is correct. After a third cache block hit, the cache block write selector writes the instruction corresponding to the jump address and other subsequent instructions stored in the third cache block into the free cache blocks of the first and second cache blocks. The fourth cache block is a small-capacity victim cache, which backs up the data discarded from the other three cache blocks in the cache block group. A fourth cache block hit indicates that the discarded data in the other three cache blocks may be reused. After a fourth cache block hit, the cache block write selector writes the currently stored instructions in the fourth cache block into the free cache blocks of the first and second cache blocks.

[0067] The aforementioned instruction fetching method, apparatus, computer device, storage medium, and computer program product based on Reduced Instruction Set Computing (RISC) implements instruction fetching through a cache block group consisting of four cache blocks. It obtains the address of the instruction to be executed and searches for it within the cache block group. If the first or second cache block is hit, the instruction to be executed corresponding to the current instruction address is read and output from the corresponding hit cache block. If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written to a free cache block in the first and second cache blocks. The instruction to be executed corresponding to the current instruction address is then read and output from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group connected to the dual cache blocks that implement general-purpose read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity.

[0068] In one embodiment, after reading and outputting the instruction corresponding to the address of the instruction to be executed, the process includes: if the instruction to be executed is a conditional jump instruction, determining whether there is a jump address for the conditional jump instruction in the cache block group; if there is no jump address for the conditional jump instruction in the cache block group, reading the next N instructions after the conditional jump instruction is executed from the external memory, writing the next N instructions into the third cache block, and backing up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0069] After the cache block read selector outputs the instruction to be executed, the preliminary decoding module performs preliminary decoding on the instruction output by the cache block read selector and determines the type of the instruction to be executed based on the decoding result. If the instruction to be executed is a conditional jump instruction, the conditional jump instruction is predicted to occur through static prediction, and the jump address of the conditional jump instruction is searched in the cache block group by the PC lookup module. If the jump address is not found in the cache block group, the cache block write selector reads the next N instructions after the conditional jump instruction from external memory and writes the next N instructions into the third cache block.

[0070] Additionally, while writing new instructions to the third cache block, the fourth cache block backs up the instructions that were discarded after the new instructions were written to the third cache block for later use. For example, if the static prediction result is correct and a nested jump occurs subsequently, the data in the fourth cache block can be immediately written to a free cache block in the first or second cache block.

[0071] In this embodiment, a conditional jump instruction is assumed to occur by static prediction. If the corresponding jump address does not exist in the cache block group, the conditional jump instruction is read from external memory, the jump instruction is executed, and the instruction after the jump is written to the third cache block. This ensures that the next instruction is read before the current instruction to be executed is executed. In addition, while writing new instructions to the third cache block, the original instructions that were discarded are backed up to the fourth cache block, which improves the cache hit rate and thus achieves fast instruction fetching.

[0072] In one embodiment, after reading and outputting the instruction corresponding to the address of the instruction to be executed, the method further includes: if the instruction to be executed is an unconditional jump instruction, determining whether there is a jump address of the unconditional jump instruction in the cache block group; if there is no jump address of the unconditional jump instruction in the cache block group, reading the next N instructions after the unconditional jump instruction is executed from the external memory and writing them into the free cache block in the first cache block and the second cache block, and backing up the discarded instructions in the free cache block to the fourth cache block, where N is a positive integer not less than 1.

[0073] The preliminary decoding module performs preliminary decoding based on the instruction to be executed output by the cache block read selector. When it is determined that the instruction to be executed is an unconditional jump instruction, the PC lookup module searches for the jump address of the unconditional jump instruction in the cache block group. For cases where the jump address does not exist in the cache block group, the cache block write selector reads the next N instructions after the jump from external memory for a conditional jump instruction, and writes the next N instructions into the free cache blocks of the first and second cache blocks.

[0074] In this embodiment, if the instruction for an unconditional jump is not in the cache block group, the next N instructions after the jump are read and executed by accessing external memory, and written to the free cache block in the first and second cache blocks. In addition, while writing new instructions to the free cache block, the original instructions that were discarded are backed up to the fourth cache block so that they can be read from the cache block group when nested jumps occur later. With limited cache space resources, the use of the victim cache improves the cache hit rate, thereby achieving fast instruction fetching.

[0075] In one embodiment, the instruction fetching method based on the reduced instruction set further includes: when all the instructions read and output are non-jump instructions, for a dual cache block consisting of a first cache block and a second cache block, while reading instructions through one cache block, new instructions are cached through the other cache block.

[0076] The instructions read and output are all non-jump instructions, meaning they are read sequentially up to the last instruction stored in the first or second cache block, and the last instruction does not trigger a jump. In this case, a ping-pong operation is performed within the dual cache block formed by the first and second cache blocks. Specifically, when the PC lookup module reaches the end of cache block 1, it switches to cache block 2 for a read operation, while the cache block write selector performs a write operation in cache block 1, writing the instruction following the last instruction in cache block 2. Similarly, when the PC lookup module reaches the end of cache block 2, it switches to cache block 1 for a read operation, while the cache block write selector performs a write operation in cache block 2, writing the instruction following the last instruction in cache block 1. This ensures that one cache block is always performing a read operation, while the other cache block is ready or updating data.

[0077] In this embodiment, a ping-pong operation is performed based on a dual cache block consisting of a first cache block and a second cache block to achieve simultaneous reading of data in one cache block and writing of data in the other cache block, thus completing seamless caching and reading of instructions and improving the efficiency of pipelined operations in the reduced instruction set architecture.

[0078] In one embodiment, before obtaining the address of the instruction to be executed, the method further includes: obtaining the starting address of the instruction to be executed, burst reading the instruction from the starting address in the external memory, and sequentially writing the burst-read instruction into the first cache block and the second cache block until both the first cache block and the second cache block are full.

[0079] Before obtaining the address of the instruction to be executed, the cache block group needs to be initialized. The specific process is to burst read the instruction from the external memory according to the address of the instruction to be executed, and write the read instruction into the first cache block and the second cache block in sequence until both general read and write cache blocks are full.

[0080] In addition, based on the above-mentioned cache block group initialization steps, this application also sets up a lookup protection function, that is, in the case that the cache block read selector reads the instruction from the external memory at the wrong starting address or writes the instruction incorrectly, it returns to the cache block group initialization step, that is, reads the instruction from the external memory again, and updates the first cache block first. After the first cache block is updated, the second cache block is updated.

[0081] In this embodiment, the step of initializing the cache block group, by sequentially updating the first cache block and the second cache block, can promptly detect errors in the starting address of read instructions or errors in write instructions, and can correct these errors in a timely manner, thus achieving efficient and accurate instruction fetching.

[0082] In one embodiment, if the third or fourth cache block is hit, the method further includes: prefetching instructions following the last instruction based on the address of the last instruction currently stored in the corresponding hit cache block and writing them into the free cache block; and backing up the instructions discarded in the free cache block to the fourth cache block when writing the currently stored instructions and instructions following the last instruction into the free cache block.

[0083] In the event of a cache hit in the third or fourth cache block, in addition to writing the instructions stored in the above two cache blocks into the free cache blocks in the first and second cache blocks, this application also adopts a cache prefetch strategy, that is, continuing to write the instructions after the last instruction currently stored in the corresponding hit cache block into the free cache block.

[0084] In this embodiment, after transferring the data stored in the third or fourth cache block to the free cache block, the instructions following the transfer instruction are written to the free cache block. By using a cache prefetching strategy, instructions that may be used in the future are predicted and written to the cache block group in advance, which effectively reduces cache misses and achieves fast instruction fetching.

[0085] To illustrate the technical solution of the instruction fetching method based on the Reduced Instruction Set Computing (RISC) of this application in detail, specific application examples will be used below in conjunction with... Figure 3 The entire process is described, and it specifically includes the following steps:

[0086] 1. Cache block initialization: The PC generation module generates the starting address 0x00 of the instruction to be executed. The external interface driver module bursts and reads instructions from external memory according to the starting address of the current instruction to be executed. The cache block write selector sequentially writes the instructions burst-read from external memory into the first cache block (e.g., ...). Figure 3 The cache1 shown) and the second cache block (as shown) Figure 3 As shown in cache2), until both the first and second cache blocks are full.

[0087] 2. The first cache block sends a message indicating that the cache block group initialization is complete to the PC lookup module and the cache block read selector. The PC lookup module searches for the instruction to be executed in the cache block group based on the address of the instruction to be executed. If found, the lookup result flag in the cache block is updated; if not found, the process returns to the cache block group initialization step, that is, the instruction is read from the external memory again, and the first cache block is updated first. After the first cache block is updated, the second cache block is updated.

[0088] 3. The cache block read selector reads the correct instruction result from the cache block group according to the lookup result flag and outputs it to the preliminary decoding module. The preliminary decoding module performs simple decoding on the read instruction and determines the type of the instruction to be executed.

[0089] a) If the instruction to be executed is determined to be a non-jump instruction, then read and output the next instruction to be executed in sequence.

[0090] When reading to the first cache block or the second cache block (e.g.) Figure 3 If the last instruction stored in cache1 / 2 is not jumpable, then a ping-pong operation is performed in the double cache block consisting of the first cache block and the second cache block. That is, while reading the instruction through one cache block, the new instruction is cached through the other cache block.

[0091] b) If the instruction to be executed is determined to be an unconditional jump instruction, the PC lookup module searches the cache block group for the existence of a jump address for the unconditional jump instruction. If an unconditional jump address exists in the cache block group, the jump proceeds normally and the next instruction to be executed is read. If no unconditional jump address exists in the cache block group, the subsequent instructions following the jump are read from external memory and written to the free cache blocks in the first and second cache blocks. Simultaneously, instructions discarded in the free cache blocks are backed up to the fourth cache block (e.g., ...). Figure 3 As shown in cache4), it then reads the next instruction to be executed from the free cache block.

[0092] c) If the instruction to be executed is determined to be a conditional jump instruction, then a jump is assumed to occur by static prediction. The PC lookup module searches the cache block group for the jump address of the conditional jump instruction. If the conditional jump address exists in the cache block group, it waits for the jump result feedback of the instruction to be executed; if the conditional jump address does not exist in the cache block group, it reads the N instructions following the jump from external memory and writes the N instructions to the third cache block (e.g., ...). Figure 3 The cache3 shown is used to wait for the jump result of the currently executed instruction.

[0093] When a conditional jump instruction has been executed and a jump is detected, the instruction currently stored in the third cache block is transferred to the free cache block in the first and second cache blocks. The discarded instructions in the free cache block are backed up to the fourth cache block. The next instruction to be executed is read from the free cache block and output.

[0094] If the conditional jump instruction has been executed and no jump occurs in the feedback, the instruction currently stored in the third cache block is backed up to the fourth cache block, and the next instruction to be executed is read and output in sequence.

[0095] 4. When searching for the address of the instruction to be executed in the cache block group through the PC lookup module, once the fourth cache block is hit, the instruction in the fourth cache block is immediately moved to the free cache block in the first and second cache blocks and the subsequent instructions are prefetched.

[0096] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0097] For the cache replacement strategy involved in this application, please refer to [link / reference]. Figure 4 and Figure 5 Among them, cache1 and cache2 are large-capacity general-purpose read-write cache blocks that cache instructions that are burst-read from external memory; cache3 is a small-capacity static prediction cache block that caches predicted jump instructions through static prediction when a conditional jump occurs; cache4 is a small-capacity victim cache that caches data discarded in other cache blocks when a jump occurs.

[0098] In one embodiment, the cache replacement strategy when an unconditional jump occurs is as follows: Figure 4 As shown, if an unconditional jump instruction "JUMP,A" is read in cache1 and the jump address "A" of an unconditional jump instruction exists in cache2, the system will jump normally to cache2 to read the instruction, and at the same time, back up the data that was discarded in cache1 during the jump to cache4.

[0099] In one embodiment, the cache replacement strategy when a conditional jump occurs is as follows: Figure 5 As shown, when a conditional jump instruction "JUMP_IF,A" is read from cache1, a jump is predicted to occur using static prediction. Since the jump address "A" for this conditional jump instruction does not exist in cache2, the instruction following the jump is read from external memory and written to cache3. If the conditional jump instruction has been executed and no jump is detected, the next instruction is read sequentially. If the conditional jump instruction has been executed and a jump is detected, the instruction currently stored in cache3 is transferred to the free cache block cache2, and the instruction following the jump is read from cache2. At the same time, the discarded instructions in cache2 are backed up to cache4.

[0100] Based on the same inventive concept, such as Figure 6 As shown in the embodiments of this application, an instruction fetching device based on a reduced instruction set (RISC) is also provided for implementing the methods described above. Instruction fetching is achieved through a cache block group, which includes a first cache block, a second cache block, a third cache block, and a fourth cache block. The device includes:

[0101] PC lookup module 601 is used to obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0102] The cache block read selection module 602 is used to read and output the instruction to be executed corresponding to the address of the instruction to be executed in the corresponding cache block when the first cache block or the second cache block is hit; and to write the instruction currently stored in the corresponding cache block into the free cache block of the first cache block and the second cache block when the third cache block or the fourth cache block is hit, and to read and output the instruction to be executed corresponding to the address of the instruction to be executed in the free cache block.

[0103] The aforementioned instruction fetching device based on a reduced instruction set (RISC) implements instruction fetching through a cache block group consisting of four cache blocks. It obtains the address of the instruction to be executed and searches for it within the cache block group. If the first or second cache block is hit, the device reads and outputs the instruction to be executed corresponding to the current instruction address from the corresponding hit cache block. If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written to a free cache block in the first and second cache blocks. The device then reads and outputs the instruction to be executed corresponding to the current instruction address from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group connected to the dual cache blocks that implement general read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity.

[0104] In one embodiment, the instruction fetching device based on a reduced instruction set further includes:

[0105] PC generation module 603 is used to generate and output the address of the instruction to be executed before the PC lookup module obtains the address of the instruction to be executed. The output address is zero when the initialization state is reached, the output address is incremented one by one when the instructions are executed sequentially, and the address of the instruction after the jump is output when an instruction jumps.

[0106] The preliminary decoding module 604 is used to decode the instruction to be executed corresponding to the address of the instruction to be executed after the PC lookup module finds the address of the instruction to be executed in the cache block group. If the address of the instruction to be executed exists in the cache block group, the module will determine the type of the instruction to be executed and output the corresponding jump address if the type of the instruction to be executed is a jump instruction.

[0107] The PC prediction module 605 is used to read the next N instructions after the jump instruction is executed from the external memory when there is no jump address in the cache block group after the initial decoding module outputs the corresponding jump address, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0108] The cache block write selection module 606 is used to send a read request to the external interface driver module after the PC lookup module has searched for the address of the instruction to be executed in the cache block group. If the address of the instruction to be executed is not found in the cache block group, the module writes the instruction read by the external interface driver module from the external memory based on the read request into the corresponding cache block in the cache block group.

[0109] The external interface driver module 607 is used to receive read requests from the cache block write selection module and to send read instructions to the external memory according to the read requests.

[0110] In one embodiment, the PC prediction module 605 is further configured to determine whether there is a jump address for a conditional jump instruction in the cache block group when the current instruction to be executed is a conditional jump instruction; if there is no jump address for a conditional jump instruction in the cache block group, read the next N instructions after the conditional jump instruction is executed from the external memory, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0111] In one embodiment, the PC lookup module 601 is further configured to determine whether there is a jump address for an unconditional jump instruction in the cache block group when the current instruction to be executed is an unconditional jump instruction; if there is no jump address for an unconditional jump instruction in the cache block group, read the next N instructions after the unconditional jump instruction is executed from the external memory and write them to the free cache block in the first cache block and the second cache block, and back up the discarded instructions in the free cache block to the fourth cache block, where N is a positive integer not less than 1.

[0112] In one embodiment, the cache block read selection module 602 is further configured to, when all read and output instructions are non-jump instructions, for a dual cache block consisting of a first cache block and a second cache block, simultaneously read instructions through one cache block and cache new instructions through the other cache block.

[0113] In one embodiment, the external interface driver module 607 is further configured to obtain the starting address of the instruction to be executed, burst-read the instruction from the starting address in the external memory, and write the burst-read instruction into the first cache block and the second cache block in sequence until both the first cache block and the second cache block are full.

[0114] In one embodiment, the cache block write selection module 606 is further configured to prefetch instructions following the last instruction based on the address of the last instruction currently stored in the corresponding hit cache block and write them into the free cache block; when writing the currently stored instructions and instructions following the last instruction into the free cache block, the instructions discarded in the free cache block are backed up to the fourth cache block.

[0115] Each module in the aforementioned instruction fetching device based on a reduced instruction set can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0116] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores reduced instruction sets (RISC). The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements an instruction fetching method based on a reduced instruction set.

[0117] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0118] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0119] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0120] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0121] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0122] In one embodiment, when the processor executes a computer program, it further performs the following steps: if the instruction to be executed is a conditional jump instruction, it determines whether there is a jump address for the conditional jump instruction in the cache block group; if there is no jump address for the conditional jump instruction in the cache block group, it reads the next N instructions after the conditional jump instruction is executed from external memory, writes the next N instructions into the third cache block, and backs up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0123] In one embodiment, when the processor executes a computer program, it further performs the following steps: if the instruction to be executed is an unconditional jump instruction, it determines whether there is a jump address for the unconditional jump instruction in the cache block group; if there is no jump address for the unconditional jump instruction in the cache block group, it reads the next N instructions after the unconditional jump instruction is executed from the external memory and writes them into the free cache block in the first cache block and the second cache block, and backs up the discarded instructions in the free cache block to the fourth cache block, where N is a positive integer not less than 1.

[0124] In one embodiment, when the processor executes a computer program, it further performs the following steps: when all the instructions read and output are non-jump instructions, for a dual cache block consisting of a first cache block and a second cache block, while reading instructions through one cache block, new instructions are cached through the other cache block.

[0125] In one embodiment, when the processor executes a computer program, it further performs the following steps: obtaining the starting address of the instruction to be executed, burst reading the instruction from the starting address in the external memory, and sequentially writing the burst-read instruction into the first cache block and the second cache block until both the first cache block and the second cache block are full.

[0126] In one embodiment, when the processor executes a computer program, it further performs the following steps: based on the address of the last instruction currently stored in the corresponding hit cache block, it continues to prefetch instructions after the last instruction and writes them into the free cache block; when writing the currently stored instructions and instructions after the last instruction into the free cache block, the instructions discarded in the free cache block are backed up to the fourth cache block.

[0127] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0128] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0129] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0130] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0131] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the instruction to be executed is a conditional jump instruction, determine whether there is a jump address for the conditional jump instruction in the cache block group; if there is no jump address for the conditional jump instruction in the cache block group, read the next N instructions after the conditional jump instruction is executed from the external memory, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0132] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the instruction to be executed is an unconditional jump instruction, it determines whether there is a jump address for the unconditional jump instruction in the cache block group; if there is no jump address for the unconditional jump instruction in the cache block group, it reads the next N instructions after the unconditional jump instruction is executed from the external memory and writes them into the free cache block in the first cache block and the second cache block, and backs up the discarded instructions in the free cache block to the fourth cache block, where N is a positive integer not less than 1.

[0133] In one embodiment, when the computer program is executed by the processor, the following steps are also performed: when all the instructions read and output are non-jump instructions, for a dual cache block consisting of a first cache block and a second cache block, while reading instructions through one cache block, new instructions are cached through the other cache block.

[0134] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining the starting address of the instruction to be executed, burst reading the instruction from the starting address in the external memory, and sequentially writing the burst-read instruction into the first cache block and the second cache block until both the first cache block and the second cache block are full.

[0135] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: based on the address of the last instruction currently stored in the corresponding hit cache block, it continues to prefetch instructions after the last instruction and writes them into the free cache block; when writing the currently stored instructions and instructions after the last instruction into the free cache block, the instructions discarded in the free cache block are backed up to the fourth cache block.

[0136] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0137] Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group;

[0138] If the first or second cache block is hit, the instruction to be executed at the address of the instruction to be executed is read and output from the corresponding cache block.

[0139] If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output.

[0140] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the instruction to be executed is a conditional jump instruction, determine whether there is a jump address for the conditional jump instruction in the cache block group; if there is no jump address for the conditional jump instruction in the cache block group, read the next N instructions after the conditional jump instruction is executed from the external memory, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1.

[0141] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the instruction to be executed is an unconditional jump instruction, it determines whether there is a jump address for the unconditional jump instruction in the cache block group; if there is no jump address for the unconditional jump instruction in the cache block group, it reads the next N instructions after the unconditional jump instruction is executed from the external memory and writes them into the free cache block in the first cache block and the second cache block, and backs up the discarded instructions in the free cache block to the fourth cache block, where N is a positive integer not less than 1.

[0142] In one embodiment, when the computer program is executed by the processor, the following steps are also performed: when all the instructions read and output are non-jump instructions, for a dual cache block consisting of a first cache block and a second cache block, while reading instructions through one cache block, new instructions are cached through the other cache block.

[0143] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining the starting address of the instruction to be executed, burst reading the instruction from the starting address in the external memory, and sequentially writing the burst-read instruction into the first cache block and the second cache block until both the first cache block and the second cache block are full.

[0144] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: based on the address of the last instruction currently stored in the corresponding hit cache block, it continues to prefetch instructions after the last instruction and writes them into the free cache block; when writing the currently stored instructions and instructions after the last instruction into the free cache block, the instructions discarded in the free cache block are backed up to the fourth cache block.

[0145] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0146] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for instruction fetching based on a reduced instruction set, characterized in that, This is achieved through a cache block group, wherein the cache block group includes a first cache block, a second cache block, a third cache block, and a fourth cache block, and the method includes: Obtain the address of the instruction to be executed and search for the address of the instruction to be executed in the cache block group; If the first cache block or the second cache block is hit, the current instruction to be executed corresponding to the address of the current instruction to be executed is read and output from the corresponding hit cache block; The first cache block and the second cache block are large-capacity general-purpose read-write caches. Ping-pong operation is performed based on the dual cache block formed by the first cache block and the second cache block. The ping-pong operation means that when the instructions read and output are all non-jump instructions, for the dual cache block formed by the first cache block and the second cache block, while reading instructions through one cache block, new instructions are cached through the other cache block. If the third or fourth cache block is hit, the instruction currently stored in the corresponding hit cache block is written into the free cache block in the first and second cache blocks. In the free cache block, the instruction to be executed corresponding to the address of the instruction to be executed is read and output. The third cache block is a small-capacity static prediction cache, which stores the statically predicted jump address when a conditional jump occurs; the fourth cache block is a small-capacity victim cache, which backs up the data discarded by the other three cache blocks in the cache block group.

2. The method according to claim 1, characterized in that, After reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed, the following steps are included: If the instruction to be executed is a conditional jump instruction, determine whether the jump address of the conditional jump instruction exists in the cache block group; If the jump address of the conditional jump instruction does not exist in the cache block group, the next N instructions after the conditional jump instruction is executed are read from the external memory, the next N instructions are written into the third cache block, and the discarded instructions in the third cache block are backed up to the fourth cache block, where N is a positive integer not less than 1.

3. The method according to claim 1, characterized in that, After reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed, the following steps are included: If the instruction to be executed is an unconditional jump instruction, determine whether the jump address of the unconditional jump instruction exists in the cache block group; If the jump address of the unconditional jump instruction does not exist in the cache block group, the next N instructions after the unconditional jump instruction is executed are read from the external memory and written to the free cache blocks in the first cache block and the second cache block. The instructions discarded in the free cache block are backed up to the fourth cache block, where N is a positive integer not less than 1.

4. The method according to claim 1, characterized in that, The method further includes: The free cache block is used to write the instruction following the last instruction currently stored in the corresponding cache block.

5. The method according to claim 1, characterized in that, Before obtaining the address of the instruction to be executed, the method further includes: Obtain the starting address of the instruction to be executed, burst-read the instruction from the starting address in the external memory, and write the burst-read instruction into the first cache block and the second cache block in sequence until both the first cache block and the second cache block are full.

6. The method according to claim 1, characterized in that, In the event of a cache hit in the third or fourth cache block, the method further includes: Based on the address of the last instruction currently stored in the corresponding hit cache block, continue to prefetch instructions after the last instruction and write them into the free cache block; When writing the currently stored instruction and the instructions following the last instruction into the free cache block, the instructions discarded in the free cache block are backed up to the fourth cache block.

7. An instruction fetching device based on a reduced instruction set, characterized in that, Instruction fetching is achieved through a cache block group, wherein the cache block group includes a first cache block, a second cache block, a third cache block, and a fourth cache block, and the device includes: The PC lookup module is used to obtain the address of the instruction to be executed and to search for the address of the instruction to be executed in the cache block group; The cache block read selection module is used to read and output the current instruction to be executed corresponding to the address of the current instruction to be executed from the corresponding cache block when the first cache block or the second cache block is hit; the first cache block and the second cache block are large-capacity general-purpose read and write caches, and a ping-pong operation is performed based on the dual cache block composed of the first cache block and the second cache block. The ping-pong operation means that when the instructions read and output are all non-jump instructions, for the dual cache block composed of the first cache block and the second cache block, while reading instructions through one cache block, new instructions are cached through the other cache block. The cache block read selection module is further configured to, in the event of a hit in the third or fourth cache block, write the currently stored instruction in the corresponding hit cache block into the free cache block of the first and second cache blocks, and read and output the currently to-be-executed instruction corresponding to the address of the currently to-be-executed instruction in the free cache block; the third cache block is a small-capacity static prediction cache, which stores the statically predicted jump address when a conditional jump occurs; the fourth cache block is a small-capacity victim cache, which backs up the data discarded by the other three cache blocks in the cache block group.

8. The apparatus according to claim 7, characterized in that, Also includes: The PC generation module is used to generate and output the address of the instruction to be executed before the PC lookup module obtains the address of the instruction to be executed. The output address is zero during initialization, the output address is incremented sequentially during instruction execution, and the address of the instruction after the jump is output when an instruction jumps. The preliminary decoding module is used to decode the current instruction to be executed corresponding to the current instruction to be executed address after the PC lookup module finds the address of the current instruction to be executed in the cache block group. If the address of the current instruction to be executed exists in the cache block group, the module determines the type of the current instruction to be executed and outputs the corresponding jump address if the type of the current instruction to be executed is a jump instruction. The PC prediction module is used to read the next N instructions after the jump instruction is executed from the external memory when the jump address is not found in the cache block group after the initial decoding module outputs the corresponding jump address, write the next N instructions into the third cache block, and back up the discarded instructions in the third cache block to the fourth cache block, where N is a positive integer not less than 1. The cache block write selection module is used to send a read request to the external interface driver module after the PC lookup module has searched for the address of the currently to be executed instruction in the cache block group. If the address of the currently to be executed instruction does not exist in the cache block group, the module writes the instruction read by the external interface driver module from the external memory based on the read request into the corresponding cache block in the cache block group. An external interface driver module is used to receive read requests from the cache block write selection module and, based on the read requests, burst read instructions to the external memory.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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