A data processing method and related apparatus

Abstract

The application discloses a data processing method applied to a terminal. The method comprises the following steps: acquiring a first instruction, wherein the first instruction is used for indicating that a first data is written into a first target area, the first target area is a storage area on a first memory, and the first memory does not have an error checking and correction (ECC) function; determining a second target area in a second memory according to the first instruction, wherein the second target area is a storage area on the second memory, and the second memory has the ECC function; and writing the first data into the second target area. In the scheme, the target data indicating the writing into the specific memory area is changed to be written into the memory with the ECC function, the protection of the target data is realized by the memory with the ECC function, the large-scale program is avoided to be executed, and the time cost during the program running is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a data processing method and related apparatus. BACKGROUND

[0002] Memory is a necessary component in a computer system, and is usually in the form of a memory stick in systems of different architectures. During system operation, memory may have hard failure or soft failure. Hard failure refers to unrecoverable data errors introduced due to hardware problems. Soft failure refers to data errors that can be recovered by power-on, power-off or rebooting, introduced due to data toggling. In order to maintain normal operation of the system, it is usually necessary to detect and repair data errors introduced due to soft failure.

[0003] In related technologies, data errors introduced due to soft failure are mainly detected by an error detection method based on instruction replication. The error detection method based on instruction replication is to replicate each original instruction by a compiler to obtain a copy instruction, and to assign different memory units to the original instruction and the copy instruction. During execution of the instruction, if it is detected that the data of the original instruction and the copy instruction are inconsistent, it is considered that soft failure has occurred, and thus repair of the data is performed.

[0004] However, since the original instruction needs to be replicated in related technologies, the size of the program finally obtained by compilation is increased, thereby causing an increase in time overhead during program execution. SUMMARY

[0005] The present application provides a data processing method. By writing target data, such as instruction data of a program itself or data generated during program execution, into a specific memory region, the target data is written into memory having an error checking and correction (ECC) function, protection of the target data is implemented by the memory having the ECC function, execution of a large-scale program is avoided, and time overhead during program execution is effectively reduced.

[0006] A first aspect of the present application provides a data processing method, which can be applied to a thread running in a virtualization privileged layer. The method comprises: a thread acquiring a first instruction. The first instruction can include a logical address of a first target region, and the first instruction is used to indicate writing of first data into the first target region in a first memory. The first target region is a storage region on the first memory, and the first memory does not have an error checking and correction (ECC) function. The logical address of the first target region can be pre-configured on the thread. Therefore, during execution of the first instruction by the terminal, the thread can intercept the first instruction according to the logical address of the first target region.

[0007] Then, the thread determines a second target region in the second memory according to the first instruction, the second target region being a storage region on the second memory, the second memory having an ECC function. In this case, the thread can search for a memory region marked as a reserved memory region in the second memory to determine the second target region; or the thread can allocate a memory region in the second memory as the second target region corresponding to the first target region after obtaining the first instruction. The thread can also determine the second target region corresponding to the first target region based on a preset second mapping relationship. The second mapping relationship is preset and used to indicate that the first target region corresponds to the second target region.

[0008] Finally, the thread writes the first data to the second target region. For example, the thread can modify a physical address mapped by a logical address of the first target region to a physical address of the second target region. In this way, when the terminal executes the first instruction, the terminal determines the physical address of the second target region mapped by the logical address of the first target region in the first instruction, and writes the first data in the first instruction to the second target region.

[0009] In this solution, a specific memory region on the memory without the ECC function is specified, and target data to be stored in the specific memory region is changed to be stored in the memory with the ECC function, so that the memory with the ECC function performs error detection and correction on the target data, and the execution of a large-scale program is avoided, thereby effectively reducing time overhead during program execution.

[0010] In a possible implementation, in the case where the thread searches for a memory region marked as a reserved memory region in the second memory to determine the second target region, or allocates a memory region in the second memory as the second target region corresponding to the first target region, the thread can further establish a mapping relationship between the first target region and the second target region, to facilitate subsequent reading or writing of data.

[0011] Specifically, the method further includes that the thread establishes a first mapping relationship between the second target region and the first target region, the first mapping relationship being used to indicate reading or writing of data. In this case, the first mapping relationship between the second target region and the first target region established by the thread can actually be a mapping relationship between a logical address of the first target region and a physical address of the second target region.

[0012] By establishing the first mapping relationship between the second target region and the first target region, it can be ensured that data can be written to the second target region or read from the second target region when an instruction of writing data to the first target region or an instruction of reading data in the first target region is subsequently received.

[0013] In a possible implementation, the method further includes: the terminal obtaining a second instruction, the second instruction being used to instruct reading data in the first target area, and the second instruction carrying the logical address of the first target area. Then, the terminal reads the first data in the second target area according to the above-mentioned relationship and the second instruction. That is, the terminal can determine, according to the above-mentioned first mapping relationship, that the physical address corresponding to the logical address of the first target area in the second instruction is the physical address of the second target area, and thus reads the first data from the second target area.

[0014] In a possible implementation, the method further includes: the terminal obtaining a third instruction, the third instruction being used to instruct writing second data to the first target area, and the third instruction also carrying the logical address of the first target area. Then, the terminal can write, according to the above-mentioned first mapping relationship and the third instruction, the second data indicated in the third instruction to the second target area. That is, the terminal can determine, according to the above-mentioned first mapping relationship, that the physical address corresponding to the logical address of the first target area in the third instruction is the physical address of the second target area, and thus writes the second data to the second target area.

[0015] In a possible implementation, before writing the first data to the second target area, the method further includes: if there is no free storage space in the second target area, the thread moves third data in the second target area out of the second target area.

[0016] By moving the third data in the second target area out of the second target area, it can be ensured that the second target area has enough space to store the first data.

[0017] In a possible implementation, the thread moving the third data in the second target area out of the second target area includes: the thread writing the third data in the second target area to the first target area and a backup area, the backup area having a first mapping relationship with the first target area, and the backup area being located on a memory without ECC function; and the thread deleting the third data in the second target area.

[0018] The first target area and the backup area can be located on the same memory, or the first target area and the backup area can be located on different memories. Moreover, the memory where the first target area and the backup area are located is without ECC function. After the terminal configures the first target area that needs to perform error detection, the thread can allocate a backup area corresponding to the first target area on the memory without ECC function, to backup the data stored in the first target area.

[0019] In the solution, the data in the second target region is moved to the first target region and the backup region in the case that there is no free storage space in the second target region, and the error detection of the data is realized by the first target region and the backup region, so that the error detection of the data in the memory can be performed, and the reliability of system operation is ensured. In addition, the error detection of the data is realized based on the first target region and the backup region, and the program with increased scale can also be avoided, so that the memory occupation of the program during running is reduced.

[0020] In a possible implementation, the third data is determined according to a least recently used (LRU) algorithm.

[0021] In a possible implementation, the method further includes: a thread acquires a fourth instruction, the fourth instruction being used to instruct to read the third data; the thread reads the data in the first target region and the data in the backup region based on the fourth instruction; and if the data in the first target region and the data in the backup region are the same, the thread returns the data in the first target region.

[0022] The second aspect of the present application provides a data processing method, including: acquiring a fifth instruction, the fifth instruction being used to instruct to write target data to a first region; determining a second region according to the fifth instruction; and writing the target data to the first region and the second region.

[0023] In the solution, the error detection of the data is realized based on writing the data into the first region and the second region, so that the program with increased scale can also be avoided, and the memory occupation of the program during running is reduced.

[0024] In a possible implementation, the method further includes: acquiring a sixth instruction, the sixth instruction being used to instruct to read the data in the first region; reading the data in the first region and the data in the second region according to the sixth instruction; if the data in the first region and the data in the second region are the same, returning the data in the first region; and if the data in the first region and the data in the second region are different, determining that the data has an error.

[0025] The third aspect of the present application provides a data processing apparatus, comprising an obtaining unit and a processing unit; the obtaining unit is configured to obtain a first instruction, the first instruction is used to indicate writing first data to a first target area, the first target area is a storage area on a first memory, and the first memory does not have an error checking and correction (ECC) function; the processing unit is configured to determine a second target area in a second memory according to the first instruction, the second target area is a storage area on the second memory, and the second memory has an ECC function; and the processing unit is further configured to write the first data to the second target area.

[0026] In a possible implementation, the processing unit is further configured to establish a first mapping relationship between the second target area and the first target area, and the first mapping relationship is used to indicate reading or writing of data.

[0027] In a possible implementation, the obtaining unit is further configured to obtain a second instruction, the second instruction is used to indicate reading data in the first target area; and the processing unit is further configured to read the first data in the second target area according to the first mapping relationship and the second instruction.

[0028] In a possible implementation, the obtaining unit is further configured to obtain a third instruction, the third instruction is used to indicate writing second data to the first target area; and the processing unit is further configured to write the second data to the second target area according to the first mapping relationship and the third instruction.

[0029] In a possible implementation, the processing unit is further configured to determine the second target area in the second memory according to the first instruction and a preset second mapping relationship; and the second mapping relationship is used to indicate that the first target area corresponds to the second target area.

[0030] In a possible implementation, the processing unit is further configured to move third data in the second target area out of the second target area if the second target area does not have a free storage space.

[0031] In a possible implementation, the processing unit is further configured to write third data in the second target area to the first target area and a backup area, the backup area has a first mapping relationship with the first target area, and the backup area is located on a memory without an ECC function; and the processing unit is further configured to delete the third data in the second target area.

[0032] In a possible implementation, the third data is determined according to a least recently used (LRU) algorithm.

[0033] In a possible implementation, the obtaining unit is further configured to obtain a fourth instruction, where the fourth instruction is used to instruct to read the third data; the processing unit is further configured to read the data in the first target region and the data in the backup region based on the fourth instruction; and the processing unit is further configured to return the data in the first target region if the data in the first target region and the data in the backup region are the same.

[0034] In a possible implementation, the apparatus is applied to a thread running at a virtualization privilege layer, and the thread is used to obtain the first instruction according to an address of the first target region.

[0035] The fourth aspect of the present application provides a data processing apparatus, comprising: an obtaining unit and a processing unit; the obtaining unit is configured to obtain a fifth instruction, where the fifth instruction is used to instruct to write target data to a first region; and the processing unit is configured to determine a second region according to the fifth instruction; and the processing unit is further configured to write the target data to the first region and the second region.

[0036] In a possible implementation, the obtaining unit is further configured to obtain a sixth instruction, where the sixth instruction is used to instruct to read data in the first region; the processing unit is further configured to read the data in the first region and the data in the second region according to the sixth instruction; return the data in the first region if the data in the first region and the data in the second region are the same; and determine that data error occurs if the data in the first region and the data in the second region are different.

[0037] The fifth aspect of the present application provides a terminal, comprising: a memory and a processor; the memory stores a code, and the processor is configured to execute the code, when the code is executed, the terminal executes the method according to any one of the implementation manners of the first aspect or the second aspect.

[0038] The sixth aspect of the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program, when the computer program is executed on a computer, the computer program causes the computer to execute the method according to any one of the implementation manners of the first aspect or the second aspect.

[0039] The seventh aspect of the present application provides a computer program product, when the computer program product is executed on a computer, the computer program product causes the computer to execute the method according to any one of the implementation manners of the first aspect or the second aspect.

[0040] The eighth aspect of the present application provides a chip comprising one or more processors. Part or all of the processors are used to read and execute a computer program stored in a memory to execute the method in any possible implementation manner of any aspect of the present application.

[0041] Optionally, the chip comprises a memory connected to the processor through a circuit or a wire. Optionally, the chip further comprises a communication interface connected to the processor. The communication interface is used to receive data and / or information to be processed, the processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. The communication interface can be an input / output interface. The method provided by the present application can be implemented by one chip or by multiple chips in cooperation. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A schematic diagram of a system software level related to an exception level provided by an embodiment of the present application;

[0043] Figure 2 A structural schematic diagram of a terminal 101 provided by an embodiment of the present application;

[0044] Figure 3 A flow schematic diagram of a data processing method 300 provided by an embodiment of the present application;

[0045] Figure 4 A schematic diagram of an HBED thread storing first data based on a first instruction provided by an embodiment of the present application;

[0046] Figure 5 A schematic diagram of an HBED thread storing data to a buffer pool provided by an embodiment of the present application;

[0047] Figure 6 A schematic diagram of an application program / operating system storing data to a buffer pool provided by an embodiment of the present application;

[0048] Figure 7 A schematic diagram of moving data out of a second target area provided by an embodiment of the present application;

[0049] Figure 8 A flow schematic diagram of a data processing method 800 provided by an embodiment of the present application;

[0050] Figure 9 A schematic diagram of an HBED thread storing target data based on a fifth instruction provided by an embodiment of the present application;

[0051] Figure 10A flowchart of a process in which an HBED thread reads data is provided for an embodiment of the present application.

[0052] Figure 11 A structural diagram of a data processing device 1100 is provided for an embodiment of the present application.

[0053] Figure 12 A structural diagram of a computer readable storage medium 1200 is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0054] The embodiments of the present application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Those skilled in the art can know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0055] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or modules does not necessarily have to be limited to those steps or modules clearly listed, but can include other steps or modules that are not clearly listed or inherent to the process, method, product or device. The naming or numbering of the steps appearing in the present application does not mean that the steps in the method flow must be executed in the order / time sequence indicated by the naming or numbering, and the flow steps that have been named or numbered can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0056] For ease of understanding, the technical terms involved in the embodiments of the present application are introduced first.

[0057] Soft failure: Soft failure is a kind of hardware transient fault phenomenon induced by high-energy particle irradiation in external environment or voltage disturbance, geomagnetic interference and other factors. When high-energy subatomic particles pass through silicon in super large scale circuit storage units (flip-flops, register units or random access memory units), free charges are generated. These charges will gather in the circuit nodes within a very short time interval (about 15 ps), and when the charge accumulation exceeds a certain degree, the stored data will change, causing system error. Since the damage to the circuit is not permanent, this phenomenon is called soft failure, also known as soft error. Soft failure can be caused by cosmic rays, boron fission, alpha rays, system noise or electromagnetic interference.

[0058] Soft failure does not destroy the internal structure of the circuit, but can affect the normal operation of the program by changing the processor state or storage unit value, thereby seriously affecting the system reliability. With the development of integrated circuit manufacturing process, the performance of modern microprocessors has been greatly improved, while the threat of soft failure is also becoming more and more serious. For example, sudden electronic interference near the memory and other factors can cause memory soft failure.

[0059] Exception Level (EL): The concept of exception level is first introduced in the processor architecture ARMv8, and each exception level represents a different privilege level. Please refer to Figure 1 , Figure 1 The system software level diagram related to exception level provided by the embodiment of the application. As shown in Figure 1 , the processor has different exception levels when running. Among them, the user level is represented by EL0; the privilege level is represented by EL1; the Hypervisor level is represented by EL2, which is used to implement the mode of virtualization technology; the monitor (Monitor) mode is represented by EL3. And the privileges of EL0, EL1, EL2 and EL3 are different, and the size of the privilege is sorted as: EL0<EL1<EL2<EL3. Generally, EL0 represents the user space layer, which is used to run application programs; EL1 represents the operating system layer, which is used to run the operating system; EL2 represents the virtualization privilege layer, which is used to run the virtual machine; EL3 represents the security monitoring layer, which is used to implement the switching between the secure state and the non-secure state.

[0060] Virtualization technology: Virtualize a physical computer resource into multiple logical computers, each of which can run different operating systems and application programs, and do not affect each other, so as to fully utilize hardware resources.

[0061] Hypervisor: A software that is used to create and execute virtual machines, running in the virtualization privileged layer. Hypervisor is a software that runs directly on the physical hardware, and the function of the hypervisor is to manage the physical hardware so as to share the physical resources (such as processor, memory and peripherals, etc.) among different virtual machines. Since the hypervisor directly interfaces with the physical resources, it needs to run in the virtualization privileged layer. The hypervisor running in the virtualization privileged layer can manage all software programs running in the user space layer and the operating system layer.

[0062] ECC: Error checking and correction technology. ECC can correct single-bit or multi-bit errors in memory, and the calculation speed is very fast. This allows errors in memory to be tolerated and corrected, allowing the system to continue to operate normally without interruption due to errors.

[0063] ECC is developed on the basis of parity check. In digital circuits, the smallest unit of data is called a bit, also known as a data bit. A bit is the smallest unit in memory, and a bit is represented by "1" and "0" to represent the high and low level signals of the data. In digital circuits, 8 consecutive bits are a byte. In memory, each byte in memory without "parity check" has only 8 bits, and if an error occurs in one of the bits, the corresponding data stored therein will change, causing the application program to have an error. A memory with "parity check" has an additional bit for error detection in each byte (8 bits). For example, a byte stores a certain value (1, 0, 1, 0, 1, 0, 1, 1), and the sum of each bit is (1+0+1+0+1+0+1+1=5). If odd parity check is used (i.e. 9 bits corresponding to the sum of the number of a byte (8 bits) plus the error detection bit is odd), then the error detection bit should be 0 (5+0=5 is odd), if even parity check is used (i.e. 9 bits corresponding to the sum of the number of a byte (8 bits) plus the error detection bit is even), then the error detection bit should be 1 (5+1=6 is even). When the processor returns to read the stored data, it will again add the data stored in the first 8 bits, and calculate whether the result is consistent with the check bit. When the processor finds that they are not the same, it will try to correct the errors.

[0064] Parity check is to check the correctness of 8-bit data on the data bit by adding a check bit to the original data bit. With the increase of data bits, the check bit also increases exponentially. Eight-bit data bits require one check bit, and sixteen-bit data bits require two check bits. ECC is also implemented by adding a check bit to the original data bit. The difference between ECC and parity check is that if the data bit is 8 bits, 5 bits need to be added for error checking and correction. ECC only increases one check bit for each doubling of the data bit. That is, when the data bit is 16 bits, the ECC bit is 6 bits, when the data bit is 32 bits, the ECC bit is 7 bits, when the data bit is 64 bits, the ECC bit is 8 bits, and so on. For each doubling of the data bit, the ECC bit only increases one bit. ECC has more check bits, and the error tolerance is stronger.

[0065] ECC memory: memory that applies ECC technology. ECC memory has ECC function, and ECC memory is generally used in servers and graphic workstations, which can improve the reliability of computer operation.

[0066] Logical address: refers to the address of the memory unit seen from the perspective of the application program in the computer architecture. The logical address is often different from the physical address, and the logical address can be converted into the physical address through the address translator or mapping function. In the computer with address conversion function, the address given by the instruction accessing the memory is often called logical address, also called relative address. Generally speaking, based on the logical address, the actual effective address in the memory, that is, the physical address, needs to be calculated or transformed through the addressing mode.

[0067] Physical address: refers to the address signal on the physical memory, which is the final result of address translation. The physical address is actually the real address of the memory.

[0068] In the related art, the data error introduced by soft failure is mainly detected by the error detection method based on instruction replication. The error detection method based on instruction replication is to copy each original instruction by the compiler in the program compilation stage to obtain a copy instruction, and to allocate different memory units for the original instruction and the copy instruction. The compiler needs to copy the original instruction in the program compilation process, and rearrange the positions of the original instruction and the copy instruction, so as to execute the original instruction and the copy instruction in parallel in the program execution process. In the process of executing the instructions of the program, if the processor detects that the data of the original instruction and the copy instruction is inconsistent, it is considered that soft failure has occurred, and the repair of the data is performed.

[0069] Obviously, since the original instruction needs to be copied in the related art, the size of the program finally compiled is increased, thereby causing an increase in the time overhead during program running. In addition, since the instruction needs to be copied and rearranged in the compilation phase in the related art, an intrusive modification is caused to the program, and the protection cannot be implemented for the compiled program.

[0070] Therefore, the embodiment of the present application provides a data processing method. The target data, such as instruction data of a program itself or data generated during program running, is written into a memory with an error checking and correction (ECC) function instead of being written into a specific memory area. The protection of the target data is implemented by the memory with the ECC function, the execution of a large-scale program is avoided, and the time overhead during program running is reduced.

[0071] The terminal related to the embodiment of the present application can include a memory with an ECC function and a memory without an ECC function. Exemplarily, the terminal can be, for example, a personal computer (PC), a notebook computer, a server, a mobile phone, a tablet computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, and the like. The terminal can be a device running an Android system, an IOS system, a windows system, and other systems. For the convenience of understanding, the data processing method provided by the embodiment of the present application will be introduced below by taking a smart phone as an example.

[0072] It can be seen from the above that Figure 2 , Figure 2 A structural schematic diagram of a terminal 101 provided by the embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the terminal 101 can include a memory 1011 and a processor 1012. The memory 1011 can include a memory with an ECC function and a memory without an ECC function. The memory with the ECC function can be used to store target data, such as instruction data of a program itself or data generated during program running. The memory without the ECC function can be used to store other data. Figure 2As shown, the terminal 101 includes a processor 103 coupled with a system bus 105. The processor 103 can be one or more processors, each of which can include one or more processor cores. A video adapter 107 can drive a display 109 coupled to the system bus 105. The system bus 105 is coupled with a bus bridge 111 and an input / output (I / O) bus. An I / O interface 115 is coupled with the I / O bus. The I / O interface 115 communicates with a variety of I / O devices, such as input devices 117 (e.g., touch screen, etc.), external storage 121 (e.g., hard disk, floppy disk, CD-ROM, or DVD-ROM), multimedia interface, etc.), a transceiver 123 (which can send and / or receive radio communication signals), a camera 155 (which can capture still and moving digital video images), and an external USB port 125. Optionally, the interface connected with the I / O interface 115 can be a USB interface.

[0073] The processor 103 can be any conventional processor, including a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, or a combination of the above. Optionally, the processor can be a special purpose device such as an ASIC.

[0074] The terminal 101 can communicate with a software deployment server 149 through a network interface 129. The network interface 129 is an example of a hardware network interface, such as a network card. The network 127 can be an external network, such as the Internet, or an internal network, such as an Ethernet or virtual private network (VPN). Optionally, the network 127 can also be a wireless network, such as a WiFi network, a cellular network, etc.

[0075] A hard drive interface 131 is coupled with the system bus 105. The hard drive interface is connected with a hard drive 133. A memory 135 is coupled with the system bus 105. Data running on the memory 135 can include an operating system (OS) 137 of the terminal 101, an application 143, and a schedule. The memory 135 includes a memory with ECC function (i.e., ECC memory 1351) and a memory without ECC function (i.e., non-ECC memory 1352). The Hypervisor and threads running on the virtualization privilege layer can be deployed on the memory with ECC function, and the operating system (OS) 137 and the application 143 can be deployed on the memory without ECC function.

[0076] The operating system includes a shell 139 and a kernel 141. The shell 139 is an interface between a user and the kernel of the operating system. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waits for the user's input, interprets the user's input to the operating system, and processes various outputs of the operating system.

[0077] The kernel 141 consists of those parts of the operating system that manage memory, files, peripherals, and system resources. The kernel 141 directly interacts with hardware, and the operating system kernel usually runs processes and provides inter-process communication, provides CPU time slice management, interrupts, memory management, and IO management, etc.

[0078] Exemplarily, in the case of the terminal 101 being a smartphone, the application program 143 includes an instant messaging related program. In one embodiment, when the application program 143 needs to be executed, the terminal 101 can download the application program 143 from the software deployment server 149.

[0079] Reference can be made to Figure 3 , Figure 3 A flowchart of a data processing method 300 provided by an embodiment of the present application is shown in FIG. 3. As shown in FIG. 3, the data processing method 300 includes the following steps 301-303. Figure 3

[0080] Step 301, a first instruction is acquired, the first instruction being used to indicate writing first data to a first target area, the first target area being a storage area on a first memory, and the first memory not having an ECC function.

[0081] In the embodiment, the data processing method 300 can be applied to a thread running in a virtualization privileged layer, which can be referred to as a Hypervisor based error detection (HBED) thread for example. The Hypervisor and the HBED thread running in the virtualization privileged layer can be deployed on a memory with an ECC function to ensure the reliability of the Hypervisor and the HBED thread during running. The operating system and the application program in the terminal are both running in a virtual machine managed by the Hypervisor.

[0082] In the process of executing the application program, the processor in the terminal executes the first instruction. The first instruction can include a logical address of the first target area, and the first instruction is used to indicate writing the first data to the first target area in the first memory.

[0083] ​Generally, in the process of executing an application program by a terminal, the instruction code of the application program is usually loaded from a hard disk to a memory by an operating system, and then the instruction code of the application program in the memory is executed by a processor in the terminal. Exemplarily, the first instruction can be an instruction from the operating system, and the first instruction is used to instruct to write the instruction code of the application program to the first target region, i.e., the first data indicated in the first instruction is the instruction code of the application program. The first instruction can also be an instruction from the application program, and the first instruction is used to instruct to write the data generated by the application program to the first target region, i.e., the first data indicated in the first instruction is the data generated by the application program during running.

[0084] Before executing the first instruction, the HBED thread in the terminal can be pre-configured with the logical address of the first target region. The first target region is a storage region on the first memory without ECC function, and the first target region is configured as a protected object, i.e., the data in the first target region needs to be detected for soft failure. Therefore, in the process of executing the first instruction by the terminal, the HBED thread can intercept the first instruction according to the logical address of the first target region. Exemplarily, a user can configure a memory region as the first target region in a user configuration file, such as a device tree blob (DTB), so that the HBED thread can obtain the logical address of the first target region. Specifically, the user can configure a memory region as the first target region by specifying the start address of the memory region and the size of the memory region, or the user can configure a memory region as the first target region by specifying the start address and the end address of the memory region.

[0085] In step 302, a second target region is determined in the second memory according to the first instruction, and the second target region is a storage region on the second memory with ECC function.

[0086] Since the first data to be written into the first target region needs to be detected for soft failure, the HBED thread in the terminal can determine a second target region in the second memory based on the first target region indicated in the first instruction, so as to write the first data into the second target region. The second target region is a storage region on the second memory with ECC function. Therefore, in the case of writing the first data into the second target region, the error detection and correction of the first data can be realized by the second memory with ECC function.

[0087] In a possible implementation, the terminal can reserve a memory region (i.e., the second target region mentioned above) in the second memory to store the data to be written into the first target region, for example, the terminal marks the reserved second target region in the second memory. In this way, after obtaining the first instruction indicating to write data into the first target region, the HBED thread can determine the second target region corresponding to the first target region in the second memory. For example, the HBED thread searches for a memory region marked as a reserved memory region in the second memory, and takes the memory region as the second target region.

[0088] In another possible implementation, the HBED thread can also allocate a memory region in the second memory as the second target region corresponding to the first target region to store the data to be written into the first target region after obtaining the first instruction.

[0089] In yet another possible implementation, the HBED thread can also determine the second target region corresponding to the first target region based on a preset second mapping relationship. The second mapping relationship is pre-established and used to indicate that the first target region corresponds to the second target region.

[0090] Step 303: write the first data into the second target region.

[0091] In a possible implementation, after the HBED thread in the terminal determines the second target region corresponding to the first target region, the HBED thread can modify the physical address mapped by the logical address of the first target region to the physical address of the second target region. In this way, after the address mapping relationship is modified, the logical address of the first target region is mapped to the physical address of the second target region. Therefore, when the terminal executes the first instruction, the physical address of the second target region mapped by the logical address of the first target region in the first instruction is determined based on the first instruction, so that the first data in the first instruction is written into the second target region.

[0092] For example, refer to Figure 4 , Figure 4 A schematic diagram of an HBED thread storing first data based on a first instruction provided by an embodiment of the present application. As shown in Figure 4As shown, during the execution of the application program, the processor in the terminal executes a first instruction in the application program, the first instruction carrying a logical address and first data, for instructing to store the first data to the region corresponding to the logical address. The logical address in the first instruction points to a first target region in the first memory. The HBED thread is pre-configured with the logical address of the entire first target region, so the HBED thread can intercept the first instruction corresponding to the application program based on the logical address of the first target region. And the HBED thread modifies the physical address corresponding to the logical address carried in the first instruction to the physical address of the second target region in the second memory. In this way, when the terminal executes the first instruction, based on the logical address in the first instruction, the second target region in the second memory can be mapped to the physical address of the second target region in the second memory, so as to store the first data to the second target region in the second memory.

[0093] In the embodiment, by specifying a specific memory region on the memory without ECC function and changing the target data to be stored in the specific memory region to be stored in the memory with ECC function, the error detection and correction of the target data are realized by the memory with ECC function, avoiding the execution of large-scale programs and effectively reducing the time overhead during program running.

[0094] In one possible embodiment, in the case that the thread finds a memory region marked as a reserved memory region in the second memory to determine the second target region, or allocates a memory region in the second memory as the second target region corresponding to the first target region, the thread can also establish a mapping relationship between the first target region and the second target region to facilitate subsequent reading or writing of data.

[0095] Specifically, after the HBED thread determines the second target region in the second memory according to the first instruction, the HBED thread can also establish a first mapping relationship between the second target region and the first target region, the first mapping relationship being used to instruct reading or writing of data. By establishing the first mapping relationship between the second target region and the first target region, it can be ensured that data can be written to the second target region or data in the second target region can be read when an instruction of writing data to the first target region or an instruction of reading data in the first target region is subsequently received.

[0096] Specifically, the first mapping relationship between the second target region and the first target region established by the HBED thread can actually be a mapping relationship between a logical address of the first target region and a physical address of the second target region. In this way, after the HBED thread establishes the first mapping relationship between the logical address of the first target region and the physical address of the second target region, when the terminal subsequently executes a related instruction carrying the logical address of the first target region, the physical address of the second target region corresponding to the logical address of the first target region can be determined based on the established first mapping relationship, so that the writing or reading of data in the second target region is performed.

[0097] In one possible example, after the HBED thread establishes the first mapping relationship between the second target region and the first target region, the terminal obtains a second instruction, which is used to instruct to read data in the first target region, that is, the second instruction carries the logical address of the first target region. Then, the terminal reads the first data in the second target region according to the above-mentioned relationship and the second instruction. That is, the terminal can determine that the physical address corresponding to the logical address of the first target region in the second instruction is the physical address of the second target region according to the above-mentioned first mapping relationship, and thus the terminal reads the first data from the second target region.

[0098] In another possible example, after the HBED thread establishes the first mapping relationship between the second target region and the first target region, the terminal obtains a third instruction, which is used to instruct to write second data to the first target region, that is, the third instruction also carries the logical address of the first target region. Then, the terminal can write the second data indicated in the third instruction to the second target region according to the above-mentioned first mapping relationship and the third instruction. That is, the terminal can determine that the physical address corresponding to the logical address of the first target region in the third instruction is the physical address of the second target region according to the above-mentioned first mapping relationship, and thus the terminal writes the second data to the second target region.

[0099] In the above example, by establishing the first mapping relationship between the second target region and the first target region, the terminal can achieve the reading and writing of data from the second target region based on the first mapping relationship when executing an instruction instructing to read and write data in the first target region. Based on the established first mapping relationship between the second target region and the first target region, the step of intercepting an instruction related to the first target region and modifying the physical address mapped by the logical address in the instruction by the HBED thread running in the virtualization privileged layer can be avoided, thereby further reducing the time overhead during program execution.

[0100] Since the capacity on the memory with ECC function is limited, the capacity allocated to the second target area is also limited. Then, in the case that the second target area has stored full of data, it is needed to ensure that new data can still be written into the second target area.

[0101] In one possible embodiment, before the first data is written into the second target area, the method further comprises: if there is no free storage space in the second target area, the HBED thread moves third data in the second target area out of the second target area. By moving the third data in the second target area out of the second target area, it can be ensured that the second target area has enough space to store the first data.

[0102] In one possible implementation, the third data is determined according to a Least Recently Used (LRU) algorithm. The LRU algorithm is a page replacement algorithm, which is used to select a page that has not been used for the longest time to be evicted. Specifically, the LRU algorithm assigns an access field to each page in the memory, which is used to record the time t that a page has experienced since it was last accessed. When a page needs to be evicted, the LRU algorithm selects a page with the largest time value t among existing pages as the page to be evicted. In this way, based on the LRU algorithm, the terminal can determine the third data that has not been used for the longest time in the second target area, and move the third data out of the second target area.

[0103] The amount of data of the third data that needs to be moved out of the second target area can be determined according to the amount of data of the first data indicated by the first instruction. In order to ensure that there is enough free space in the second target area to store the first data after the third data is moved out, the amount of data of the third data can be greater than or equal to the amount of data of the first data. For example, when the amount of data of the first data indicated by the first instruction is 10 Mbytes (MByte), the HBED thread can determine 10 Mbytes of data that has not been used for the longest time in the second target area as the third data, and move the 10 Mbytes of third data out of the second target area.

[0104] In addition, in the case that there is still some free storage space left in the second target area, but the remaining free space is not enough to store the first data, the sum of the amount of data of the third data to be moved out of the second target area and the size of the current free space left in the second target area needs to be greater than or equal to the amount of data of the first data.

[0105] In the embodiment, since the second target region is located on the second memory with ECC function, after the HBED thread moves the third data out of the second target region, the third data is no longer located on the second memory with ECC function. That is, after the third data is moved out, since the third data is no longer detected by the memory with ECC function, other ways are needed to perform error detection on the third data.

[0106] Exemplarily, the HBED thread moves the third data in the second target region out of the second target region, including: the HBED thread writes the third data in the second target region into the first target region and a backup region, the backup region has a first mapping relationship with the first target region, and the backup region is located on a memory without ECC function. After the third data is written into the first target region and the backup region, the HBED thread deletes the third data in the second target region.

[0107] The first target region and the backup region can be located on the same memory, or the first target region and the backup region can be located on different memories. In addition, the memory where the first target region and the backup region are located is a memory without ECC function. After the terminal configures the first target region which needs to perform error detection, the HBED thread can allocate a backup region corresponding to the first target region on the memory without ECC function to backup the data stored in the first target region.

[0108] That is, after the HBED thread moves the third data out of the memory with ECC function, the HBED thread stores the third data on two different memory regions, so as to perform error detection on the third data when the third data is read subsequently.

[0109] In addition, since the instruction obtained by the HBED thread before storing the third data into the second target region actually indicates to store the third data into the first target region, and the instruction also carries the logical address in the first target region for storing the third data. Therefore, after the HBED thread moves the third data out of the second target region, the HBED thread can store the third data into the address in the first target region originally specified, so as to correctly read the third data from the first target region subsequently. For the backup region, the HBED thread can establish a first mapping relationship between the address in the backup region and the address in the target region when the backup region is allocated. In this way, after the HBED thread determines the storage address of the third data in the first target region, the HBED thread can store the third data into the corresponding address of the backup region.

[0110] In the scheme, the data in the second target region is moved to the first target region and the backup region in the case that there is no free storage space in the second target region, and the error detection of the data is realized by the first target region and the backup region, so that the error detection of the data in the memory can be performed, and the reliability of system operation is ensured. In addition, the error detection of the data is realized based on the first target region and the backup region, and the program with increased execution scale can also be avoided, so that the occupation of the memory by the program during execution is reduced.

[0111] In one possible embodiment, after the HBED thread stores the third data into the first target region and the backup region, the method further includes that the HBED thread can acquire a fourth instruction, and the fourth instruction is used to instruct to read the third data. That is, the storage address (which is a logical address) of the third data in the first target region can be carried in the fourth instruction. Since the HBED thread establishes the first mapping relationship between the first target region and the backup region, the HBED thread can read the data in the first target region based on the storage address indicated by the fourth instruction, and read the data in the backup region based on the address in the backup region corresponding to the storage address.

[0112] After the HBED thread reads the data in the first target region and the data in the backup region, the HBED thread compares the two pieces of data read, and if the data in the first target region and the data in the backup region are the same, the data in the first target region is returned to the application that requests to read the third data. If the data in the first target region and the data in the backup region are not the same, the HBED thread can determine that a soft failure error occurs to the data, and the HBED thread can return information prompting the data error, so as to facilitate subsequent execution of data repair.

[0113] For ease of understanding, the data processing method provided in the embodiment will be introduced in detail below in combination with examples.

[0114] Specifically, the HBED thread first reserves a region in the memory with the ECC function as the second target region, which is used to map the protected memory region (i.e., the first target region). The memory region reserved by the HBED thread can be referred to as a buffer pool (Buffer pool)

[0115] It can be referred to Figure 5 , Figure 5The figure shows the process of storing data in buffer pool by HBED thread. When the application program at EL0 or the operating system at EL1 layer writes data into the first target area for the first time, the application program or the operating system falls into the virtualization privileged layer, that is, the data write instruction from the application program or the operating system is intercepted by the HBED thread, and the HBED thread is responsible for implementing the data write. The HBED thread finds a free memory area in the buffer pool based on the data write instruction, which can be referred to as the second target area for example. The HBED thread establishes a mapping relationship between the first target area and the second target area, and writes data into the second target area.

[0116] Referring to FIG. 8, Figure 6 , Figure 6 The figure shows the process of storing data in buffer pool by the application program / operating system. As shown in FIG. 9, Figure 6 after the HBED thread establishes the first mapping relationship between the first target area and the second target area, when the application program / operating system needs to write data into the first target area or read data, it is not necessary to fall into the virtualization privileged layer again, but to directly write data into the corresponding second target area or read data from the second target area.

[0117] Referring to FIG. 8, Figure 7 , Figure 7 The figure shows the process of moving data out of the second target area. As shown in FIG. 10, Figure 7 in the process of continuously writing data into the buffer pool by the HBED thread, if the HBED thread finds that the buffer pool no longer has a free memory area, the HBED thread moves part of the data in the buffer pool out of the buffer pool. Specifically, the HBED thread writes part of the data in the buffer pool into the first target area and the backup area at the same time, and deletes part of the data in the buffer pool.

[0118] The above embodiments introduce the error detection of data by storing data on the memory with ECC function. The following will introduce the error detection of data by storing data in multiple areas.

[0119] Referring to FIG. 8, Figure 8 The figure shows the flowchart of the data processing method 800 provided by the embodiment of the present application. As shown in FIG. 11, Figure 8 the data processing method 800 includes the following steps 801-803.

[0120] Step 801, a fifth instruction is acquired, and the fifth instruction is used to indicate writing target data into a first area.

[0121] In this embodiment, the data processing method 300 can be applied to a thread running in a virtualization privilege layer, for example, the HBED thread described above. During execution of an application program, the processor in the terminal executes a fifth instruction. The fifth instruction can include a logical address of a first region, and the first instruction is used to instruct writing of target data into the first region in the memory.

[0122] Before execution of the fifth instruction, the HBED thread in the terminal can be pre-configured with the logical address of the first region. The first region is a storage region on the memory without ECC function, and the first region is configured as a protected object, i.e., the data in the first region needs to be subjected to soft failure detection. Therefore, during execution of the fifth instruction by the terminal, the HBED thread can intercept the fifth instruction according to the logical address of the first region.

[0123] Step 802, determining a second region according to the fifth instruction.

[0124] Since the target data to be written into the first region needs to be subjected to soft failure detection, the HBED thread in the terminal can determine a second region outside the first region in the memory based on the first region indicated in the fifth instruction, so as to write the target data into the second region at the same time. The second region and the first region are two non-overlapping memory regions.

[0125] In a possible implementation, the HBED thread can allocate another memory region in the memory as the second region corresponding to the first region to store the data to be written into the first region after obtaining the fifth instruction. The size of the second region can be the same as that of the first region.

[0126] Step 803, writing the target data into the first region and the second region.

[0127] After determining the second region, the HBED thread can write the target data indicated in the fifth instruction into the first region and the second region based on the fifth instruction, i.e., achieving storage of the target data in the first region and the second region.

[0128] In this way, since the target data is stored in the first region and the second region at the same time, when the target data needs to be read, the corresponding data can be read from the first region and the second region and compared, so as to achieve error detection of the target data.

[0129] For example, refer to Figure 9 , Figure 9 An HBED thread based on a fifth instruction to store target data provided by an embodiment of the present application is shown in FIG. 8. As shown in FIG. 8, the HBED thread can intercept the fifth instruction, and determine a second region corresponding to the first region indicated in the fifth instruction. Then, the HBED thread can write the target data indicated in the fifth instruction into the first region and the second region. Figure 9As shown, during the execution of the application program, the processor in the terminal executes a fifth instruction in the application program, which carries a logical address and target data, for instructing to store the target data to the first region corresponding to the logical address. The HBED thread is pre-configured with the logical address of the first region, so the HBED thread can intercept the fifth instruction corresponding to the application program based on the logical address of the first region. Finally, the HBED thread stores the target data indicated in the fifth instruction in the first region and the second region at the same time.

[0130] In this solution, the error detection of data is implemented based on the simultaneous writing of data into the first region and the second region, which can avoid the execution of the program after the increase of the scale, thereby reducing the occupation of the memory during the program running.

[0131] For the data processing method provided in the embodiments of the present application, the HBED thread reads the data. Referring to Figure 10 , Figure 10 For the data processing method provided in the embodiments of the present application, the HBED thread reads the data. Referring to Figure 10 As shown, in one possible embodiment, the data processing method 800 further includes that the HBED thread acquires a sixth instruction, and the sixth instruction is used to instruct to read the data in the first region. The HBED thread reads the data in the first region and the data in the second region according to the sixth instruction. If the data in the first region is the same as the data in the second region, the HBED thread returns the data in the first region to the application program which issues the sixth instruction; if the data in the first region is not the same as the data in the second region, it is determined that the data has an error, and the HBED thread can return the information prompting the error, so as to facilitate the subsequent execution of the repair of the data.

[0132] In order to verify the beneficial effects of the data processing method described in the above embodiments, the present embodiment carries out corresponding tests based on the above data processing method.

[0133] Specifically, in the test, a protected environment keystone (PEK) is used as a Hypervisor running in a virtualization privileged layer, and an HBED thread is built in the PEK. The PEK and the HBED are deployed on a memory with an ECC function to ensure the reliability of the PEK and the HBED thread. In addition, a virtual machine is started by the PEK, and an application program runs in the virtual machine. A DTB file is used as a configuration file of the PEK, and a protected memory region is configured in the DTB. To detect the time overhead of the HBED thread at runtime, the application program in the virtual machine reads and writes 50000 times to the protected memory region, respectively. Specifically, the read-write time overheads between the existing scheme and the error detection scheme based on the HBED and the memory with the ECC function (i.e., the data processing method 300) provided in the embodiment are shown in Table 1.

[0134] Table 1

[0135] 50000 reads 50000 writes delta 50000 reads delta 50000 writes Prior art 0.025112 0.022782 HBED + ECC memory 0.016288 0.0140736 64.86％ 61.78％

[0136] As can be seen from Table 1, the runtime time overheads of the method provided in the embodiment when performing 50000 times of reading and writing are 64.86% and 61.78% of the existing scheme, respectively, and the time overhead is obviously lower than that of the existing scheme.

[0137] In addition, in terms of memory occupation, since the existing scheme replicates each instruction, the size of the target program is doubled compared with the original program, while the method provided in the embodiment does not modify the original program, and the program size remains unchanged.

[0138] In Figures 1 to 10 Based on the corresponding embodiments, in order to better implement the above scheme of the embodiments of the present application, the following related devices for implementing the above scheme are further provided.

[0139] Specifically, refer to Figure 11 , Figure 11 A structure diagram of a data processing apparatus 1100 provided in the embodiments of the present application is shown in FIG. 11. The data processing apparatus 1100 includes an acquisition unit 1101 and a processing unit 1102. The acquisition unit 1101 is configured to acquire a first instruction, and the first instruction is used to indicate writing of first data to a first target region. The first target region is a storage region on a first memory, and the first memory does not have an error checking and correction (ECC) function. The processing unit 1102 is configured to determine a second target region in a second memory according to the first instruction. The second target region is a storage region on a second memory, and the second memory has an ECC function. The processing unit 1102 is further configured to write the first data to the second target region.

[0140] In a possible implementation, the processing unit 1102 is further configured to establish a first mapping relationship between the second target region and the first target region, where the first mapping relationship is used to indicate reading or writing of data.

[0141] In a possible implementation, the obtaining unit 1101 is further configured to obtain a second instruction, where the second instruction is used to instruct reading of data in the first target region; and the processing unit 1102 is further configured to read the first data in the second target region according to the first mapping relationship and the second instruction.

[0142] In a possible implementation, the obtaining unit 1101 is further configured to obtain a third instruction, where the third instruction is used to instruct writing of second data to the first target region; and the processing unit 1102 is further configured to write the second data to the second target region according to the first mapping relationship and the third instruction.

[0143] In a possible implementation, the processing unit 1102 is further configured to determine the second target region in the second memory according to the first instruction and a preset second mapping relationship, where the second mapping relationship is used to indicate that the first target region corresponds to the second target region.

[0144] In a possible implementation, the processing unit 1102 is further configured to move third data in the second target region out of the second target region if the second target region does not have a free storage space.

[0145] In a possible implementation, the processing unit 1102 is further configured to write third data in the second target region to the first target region and a backup region, where the backup region has a first mapping relationship with the first target region, and the backup region is located on a memory without an ECC function; and the processing unit 1102 is further configured to delete the third data in the second target region.

[0146] In a possible implementation, the third data is determined according to an LRU algorithm.

[0147] In a possible implementation, the obtaining unit 1101 is further configured to obtain a fourth instruction, where the fourth instruction is used to instruct reading of the third data; and the processing unit 1102 is further configured to read data in the first target region and data in the backup region based on the fourth instruction; and the processing unit 1102 is further configured to return the data in the first target region if the data in the first target region and the data in the backup region are the same.

[0148] In a possible implementation, the apparatus is applied to a thread running at a virtualization privilege layer, and the thread is configured to acquire the first instruction according to an address of the first target region.

[0149] In another possible embodiment, the acquisition unit 1101 is configured to acquire a fifth instruction, and the fifth instruction is configured to indicate writing target data into a first region; the processing unit 1102 is configured to determine a second region according to the fifth instruction; and the processing unit 1102 is further configured to write the target data into the first region and the second region.

[0150] In a possible implementation, the acquisition unit 1101 is further configured to acquire a sixth instruction, and the sixth instruction is configured to indicate reading data in the first region; and the processing unit 1102 is further configured to read the data in the first region and the data in the second region according to the sixth instruction; if the data in the first region is the same as the data in the second region, return the data in the first region; and if the data in the first region is different from the data in the second region, determine that data error occurs.

[0151] The data processing method provided by the embodiments of the present application can be executed by a chip in a terminal, which includes a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin, or a circuit, etc. The processing unit can execute computer execution instructions stored in a storage unit, so that the chip in the server executes the data processing method described in the embodiments. Figures 1 to 10 The data processing method described in the embodiments. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0152] With reference to Figure 12 The present application also provides a computer readable storage medium. In some embodiments, the above Figure 3 The disclosed method can be implemented as computer program instructions coded in a machine-readable format on a computer readable storage medium or other non-transitory medium or article of manufacture.

[0153] Figure 12 A conceptual partial view of an example computer readable storage medium arranged in accordance with at least some embodiments presented herein is schematically shown, the example computer readable storage medium including a computer program for executing a computer process on a computing device.

[0154] In one embodiment, the computer-readable storage medium 1200 is provided using a signal bearing medium 1201. The signal bearing medium 1201 can include the one or more program instructions 1202 embodied in the medium 1203, which when executed by one or more processors, can provide the functionality or some of the functionality described above with respect to Figure 2 the embodiments shown in FIG. 12. Thus, for example, one or more of the features of steps 301-303 can be undertaken by one or more instructions associated with the signal bearing medium 1201. Further, the program instructions 1202 in the signal bearing medium 1201 also describe example instructions. Figure 3 Figure 12 The program instructions 1202 in the signal bearing medium 1201 further describe example instructions.

[0155] In some examples, the signal bearing medium 1201 can comprise a computer- readable medium 1203, such as, but not limited to, a hard disk drive, a Compact Disk (CD), a Digital Video Disk (DVD), a memory, a ROM, a RAM, or the like.

[0156] In some embodiments, the signal bearing medium 1201 can comprise a computer- recordable medium 1204, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, and the like. In some embodiments, the signal bearing medium 1201 can comprise a communications medium 1205, such as, but not limited to, a digital and / or an analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, and the like). Thus, for example, the signal bearing medium 1201 can be conveyed by a wireless form of the communications medium 1205 (e.g., a wireless communication medium complying with the IEEE 802.12 standard, or another transmission protocol).

[0157] The one or more program instructions 1202 can be, for example, computer- executable instructions, or logic-implemented instructions. In some examples, a computing device of a computing device can be configured to provide various operations, functions, or actions in response to the program instructions 1202 conveyed to the computing device by one or more of the computer-readable medium 1203, the computer-recordable medium 1204, and / or the communications medium 1205.

[0158] It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will appreciate that other arrangements and other elements (e.g., machines, interfaces, functions, orders, and the like) can be used instead, and some elements can also be omitted altogether for the sake of conciseness, as

[0159] ​Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0160] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0161] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0162] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0163] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that makes a contribution or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various program code storage media.

Claims

1. A data processing method, characterized by, The method comprises: obtaining a first instruction, the first instruction being used for instructing to write first data to a first target area, the first target area being a storage area on a first memory, the first memory not having an error checking and correction (ECC) function; determining a second target area in a second memory according to the first instruction, the second target area being a storage area on the second memory, the second memory having the ECC function; writing the first data to the second target area.

2. The method of claim 1, wherein, The method further comprises: establishing a first mapping relationship between the second target area and the first target area, the first mapping relationship being used for instructing reading or writing of data.

3. The method of claim 2, wherein, The method further comprises: obtaining a second instruction, the second instruction being used for instructing to read data in the first target area; reading the first data in the second target area according to the first mapping relationship and the second instruction.

4. The method according to claim 2 or 3, characterized in that, The method further comprises: obtaining a third instruction, the third instruction being used for instructing to write second data to the first target area; writing the second data to the second target area according to the first mapping relationship and the third instruction.

5. The method of claim 1, wherein, The determining of the second target area in the second memory according to the first instruction comprises: determining the second target area in the second memory according to the first instruction and a preset second mapping relationship; the second mapping relationship being used for instructing that the first target area corresponds to the second target area.

6. The method according to any one of claims 1, 2, 3 and 5, characterized in that, Before the writing of the first data to the second target area, the method further comprises: if there is no free storage space in the second target area, moving third data in the second target area out of the second target area.

7. The method of claim 6, wherein, The moving of the third data in the second target area out of the second target area comprises: writing the third data in the second target area to the first target area and a backup area, the backup area having a mapping relationship with the first target area, and the backup area being located on a memory not having the ECC function; deleting the third data in the second target area.

8. The method of claim 6, wherein, The third data is determined according to a least recently used (LRU) algorithm.

9. The method of claim 7, wherein, The method further comprises: obtaining a fourth instruction, the fourth instruction being used for instructing to read the third data; reading data in the first target area and data in the backup area based on the fourth instruction; if the data in the first target area and the data in the backup area are the same, returning the data in the first target area.

10. The method according to any one of claims 1, 2, 3 and 5, characterized in that, The method is applied to a thread running in a virtualization privilege layer, the thread being used for obtaining the first instruction according to an address of the first target area.

11. A terminal, characterized by comprising: The terminal comprises a memory and a processor; the memory stores code, and the processor is configured to execute the code, when the code is executed, the terminal executes the method in any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, The computer readable instruction, when running on a computer, causes the computer to execute the method in any one of claims 1 to 10.

13. A computer program product, characterised in that, computer readable instructions, which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 10.

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