Entity storage mapping table generation apparatus and method

Abstract

Embodiments of the present invention provide an entity storage map generating device, which comprises a direct memory access controller, an extension circuit and a controller. The extension circuit extends first entity location information in the entity storage map corresponding to a request of a host device into second entity location information represented by a larger number of bytes, so that the second entity location information conforms to an output format of a flash memory storage standard specification. The controller returns the second entity location information to the host device. By using the extension circuit to generate the second entity location information conforming to the output format of the flash memory storage standard specification, the waiting time for outputting the entity storage map to the host device can be reduced.

Description

[0001] This application is a divisional application. The original application was filed on June 25, 2018; the application number is 201810664292.7; and the invention title is: Apparatus and Method for Generating Entity Storage Lookup Table. Technical Field

[0002] This invention relates to storage devices, and more particularly to a physical storage lookup table generation apparatus and method. Background Technology

[0003] Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. NOR flash memory devices are random access devices; the host device can provide any address to access the NOR flash memory device on its address pins and promptly retrieve the data stored at that address from the data pins. Conversely, NAND flash memory devices are not random access devices but sequential access devices. Unlike NOR flash memory devices, NAND flash memory devices cannot access any random address. Instead, the host device needs to write sequential bytes of data into the NAND flash memory device to define the type of request command (e.g., read, write, erase), and the address used for that command. The address can point to a page (the smallest data block in a write operation in the flash memory device) or a block (the smallest data block in a erase operation in the flash memory device).

[0004] In practice, to improve write speed, data at a contiguous logical location may be distributed across several physical flash memory cells. NAND flash memory devices use a physical memory lookup table to indicate where the data is written within the physical flash memory cells. When the host device sends a read command containing the logical location to the NAND flash memory device, the NAND flash memory device must convert the logical location to a physical location based on the physical memory lookup table, then read the data from the physical location and send it back to the host device. However, due to the limited space in the data buffer of the NAND flash memory device, it cannot store the complete physical memory lookup table for fast lookup; only a portion of it can be stored. When the logical location in the read command issued by the host device cannot match a portion of the physical memory lookup table in the data buffer, the NAND flash memory device must spend a significant amount of time reading the appropriate portion of the physical memory lookup table from the flash memory cells, increasing the host device's latency in obtaining the data.

[0005] To reduce latency, the new flash memory standard allows the host device to directly send data read commands containing physical locations to the NAND flash memory device. However, the host device needs to obtain a physical memory lookup table from the NAND flash memory device before performing logical physical address translation. To enable communication between the host device and NAND flash memory devices from different manufacturers, the flash memory standard specifies the output format of the physical memory lookup table. However, the standard-specified output format often differs from the internal format used by the NAND flash memory device, requiring conversion. Therefore, this invention proposes an apparatus and method to save time in generating a compliant physical memory lookup table. Summary of the Invention

[0006] In view of this, how to alleviate or eliminate the deficiencies in the aforementioned related areas is a problem that needs to be solved.

[0007] This invention provides an embodiment of an entity memory lookup table generation apparatus, comprising: a direct memory access controller, an expansion circuit, and a controller. The direct memory access controller reads first entity location information corresponding to a logical location in the entity memory lookup table from a data buffer. The expansion circuit expands the first entity location information to second entity location information represented using a larger number of bytes. The controller replies the second entity location information to a master device.

[0008] The advantage of the above embodiments is that by using an extended charging circuit to generate second entity location information in an output format that conforms to the flash memory storage standard specification, the waiting time for the output entity storage lookup table to be sent to the main device is reduced.

[0009] Another advantage of the above embodiments is that it avoids the need for additional space in the data buffer configuration to store the second entity location information in an output format conforming to the flash storage standard specification.

[0010] Other advantages of the present invention will be explained in more detail below with reference to the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are provided to further illustrate this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application.

[0012] Figure 1 This is a sequence diagram of the main device requesting a physical storage lookup table from the flash memory storage device according to an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram illustrating the physical storage according to an embodiment of the present invention.

[0014] Figure 3 This is a system block diagram for some implementation methods.

[0015] Figure 4 This is a system block diagram for generating a physical storage lookup table for a flash memory storage device according to an embodiment of the present invention.

[0016] Figure 5 This is a flowchart of a method for generating a physical storage lookup table for a flash memory storage device according to an embodiment of the present invention.

[0017] Figure 6 This is a schematic diagram showing the connection between the access sub-interface and multiple storage sub-units.

[0018] Figures 7 to 13 This is a block diagram of an extended charging circuit according to an embodiment of the present invention.

[0019] Figure 14 This is a schematic diagram of the functional module for generating a physical storage lookup table for a flash memory storage device according to an embodiment of the present invention.

[0020] Symbol explanation:

[0021] 110 Main Unit

[0022] 130 Flash Memory Device

[0023] 151 Read Request

[0024] 153 Looping through the entity storage lookup table

[0025] 155 Read Replies

[0026] 210 Entity Storage Reference Table

[0027] 230 Entity Location Information

[0028] 230-0 Entity Block Number

[0029] 230-1 Starting unit number of the main page

[0030] 250 entity blocks

[0031] 251 Main Page

[0032] 310 Physical Layer

[0033] 320 Data Link Layer

[0034] 330 processing unit

[0035] 351 Controller

[0036] 353 Direct Memory Access Controller

[0037] 370, 450 data buffers

[0038] 380, 430 Direct Memory Access Controller

[0039] 375, 480 Flash Memory Controller

[0040] 390 flash memory cells

[0041] 410, 410_1~410_13 Expansion circuit

[0042] 470 processing units

[0043] 490 Controller

[0044] S510~S550 Method Steps

[0045] 610 Access Subinterface

[0046] 630_0~630_i memory sub-units

[0047] 650 data cable

[0048] 670_0~670_i Chip Enable Control Signals

[0049] 710, 710_1~710_2 Fill Registers

[0050] 730, 730_1~730_2 Entity Location Registers

[0051] 750_1~750_2 Scrambling Registers

[0052] 770_1~770_2 Scrambler

[0053] 780, 780_1~780_2 Parity Registers

[0054] Parity check generators 790, 790_1~790_2

[0055] Program modules 1410, 1430, and 1450 Detailed Implementation

[0056] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals denote the same or similar components or method flows.

[0057] It must be understood that the words “comprising” and “including” used in this specification are used to indicate the presence of specific technical features, values, method steps, operation processes, parts and / or components, but do not preclude the addition of more technical features, values, method steps, operation processes, parts, components, or any combination thereof.

[0058] In this invention, terms such as "first," "second," and "third" are used to modify components in the claims and are not intended to indicate a priority order, a precedence relationship, or that one component precedes another, or the chronological order of the execution of method steps. They are only used to distinguish components with the same name.

[0059] Figure 1 This is a sequence diagram illustrating the process of a master device requesting a physical storage mapping table from a flash memory device according to an embodiment of the present invention. The flash memory system includes a master device 110 and a flash memory device 130, which communicate with each other using a flash memory communication protocol (e.g., Universal Flash Storage UFS). The flash memory device 130 may be a NAND flash memory device. Since a NAND flash memory device is not a random access device, to improve write efficiency, the master device 110 can provide at least one length of continuous data, such as 128KB, allowing the flash memory device 130 to efficiently write data to several storage sub-cells in a parallel operation. After successfully writing user data to a logical location, the flash memory device 130 needs to update the correspondence information between this logical location and the written physical location in the temporary physical storage mapping table temporarily stored in static random access memory. Furthermore, after successfully writing user data to a predetermined number of logical locations, the storage mapping table (also known as the H2F host-to-flash table) stored in the non-volatile flash memory cell is updated based on the contents of a temporary physical storage mapping table. Therefore, the contents of the physical storage mapping table are maintained by the flash memory device 130, not the host device 110. The physical storage mapping table records which physical location in the flash memory cell the user data for each logical location is actually stored in.

[0060] Figure 2This is a schematic diagram of entity storage mapping according to an embodiment of the present invention. Entity storage mapping table 210 stores entity location information corresponding to each logical location sequentially. The space required for entity storage mapping table 210 varies from 64M to 1G bytes. A logical location can be represented by a Logical Block Address (LBA), with each LBA corresponding to a fixed-size entity storage space, such as 512 bytes. For example, entity storage mapping table 210 stores entity location information from LBA0 to LBA65535 sequentially. Data from several consecutive logical locations (e.g., LBA0 to LBA7) can form a host page. Entity location information 230 can be represented by four bytes: the first two bytes 230-0 record the physical block number; the last two bytes 230-1 record the unit number. For example, entity location information 230 corresponding to logical location LBA2 can point to an entity portion 251 within entity block 250. Byte 230-0 records the number of entity block 250, and byte 230-1 records the unit number of entity part 251.

[0061] Because the flash memory storage device 130 can update the contents of the physical memory lookup table 210 according to actual operation, such as performing data write operations, garbage collection (GC) processes, wear leveling processes, read reclaim processes, and read reflash processes, when the contents of the physical memory lookup table 210 are modified, the flash memory storage device 130 can notify the master device 110 that it needs to re-obtain the modified physical memory lookup table 210 for the corresponding logical location range. Upon receiving the notification, the master device 110 can issue a read request 151 for the physical memory lookup table at any time. The read request 151 can contain information about the logical location range, such as LBA0 to LBA199. For example, the master device 110 can send a UFS Protocol Information Unit (CMDUPIU) command to the flash memory storage device 130, where the CMD UPIU contains the read request 151. Flash storage device 130 obtains the physical storage lookup table 210 of the requested logical location range and can execute a loop 153 to transmit the physical storage lookup table 210 of the requested logical location range to the host device 110 in segments. In each loop, flash storage device 130 can load a portion of the physical storage lookup table 210 of the requested logical location range into the data segment area of ​​the DATA IN UPIU. When the transmission of the requested physical location information is complete, flash storage device 130 sends a read response 155 to the host device 110. Flash storage device 130 can send a UFS communication protocol information unit response (Response UPIU) to the host device 110, and the Response UPIU contains the read response 155.

[0062] To prevent the loss of the physical memory lookup table 210 in the data buffer due to unexpected power outages, the flash memory storage device 130 can store the complete physical memory lookup table 210 in non-volatile flash memory cells. To save space in the data buffer and flash memory cells, the physical location information corresponding to each logical location is typically recorded with a minimum number of bytes. However, to ensure compatibility of the host device 110 with flash memory storage devices from all manufacturers, the output format of the physical memory lookup table specified by the flash memory standard typically uses more bytes to record the physical location information corresponding to each logical location. For example, the flash memory storage device 130 uses four bytes to store the physical location information corresponding to each logical location, but the flash memory standard uses eight bytes to store the same information. Therefore, the flash memory storage device 130 needs to expand the physical location information 230 of the physical memory lookup table 210 to a more byte-based output format.

[0063] In some implementations, the flash memory storage device 130 may have space configured in the data buffer for format conversion. Figure 3 This is a system block diagram for some implementation methods. It is assumed that the flash memory storage device 130 uses, as shown below... Figure 2 The four-byte storage shown corresponds to the physical location information for each logical location, while the flash memory standard uses eight bytes for storing physical location information: After receiving a read request 151 from the host device 110, the processing unit 330 drives the flash memory storage unit 390 to read the physical memory lookup table 210 of the requested logical location range and store it in the data buffer 370. The data buffer 370 is configured with two locales to store the original physical memory lookup table 210 and the expanded physical memory lookup table, respectively. Next, the processing unit 330 drives the Direct Memory Access (DMA) controller 380 to copy the original physical memory lookup table 210 into two copies (i.e., the expanded physical memory lookup table) and store them in a designated locale in the data buffer 370. Then, the processing unit 330 drives the DMA controller 353 through the controller 351 to read the expanded physical memory lookup table from the designated locale in the data buffer 370 and reply to the host device 110 via the data link layer 320 (e.g., UniPro) and the physical layer 310. However, such an implementation requires a local space in the data buffer 370 to store the expanded entity memory lookup table. For example, for 1KB of original entity location information (corresponding to 256 logical locations), the data buffer 370 must be allocated an additional 2KB of space to store the expanded entity location information. The data buffer 370 is a scarce resource, and adding a local space to store the expanded entity memory lookup table may crowd out the storage of other important data. Furthermore, the above-described implementation requires the processing unit 330 to spend time controlling the direct memory access controller 380.

[0064] To improve the shortcomings of the implementation method described above, Figure 4 This is a system block diagram illustrating the generation of a physical storage lookup table for a flash memory storage device according to an embodiment of the present invention. The controller 490 is electrically connected (coupled) to the host device 110 via the data link layer 320 and the physical layer 310, and is connected between the processing unit 470, the expansion circuit 410, and the direct memory access controller 430. The processing unit 470 is connected to the flash memory storage controller 480 and is used to drive the flash memory storage controller 480 to read user data from a specific physical location of the flash memory storage unit 390 and store it in the data buffer 450 according to commands sent by the host device 110, retrieve user data from the data buffer 450 and write it to a specific physical location of the flash memory storage unit 390, or perform an erase operation on a specific physical location of the flash memory storage unit 390. The controller 490 can read user data from the data buffer 450 through the direct memory access controller 430 and sequentially knock it out to the host device 110 by driving the data link layer 320 and the physical layer 310. The controller 490 can store user data that the host device 110 wants to write into the data buffer 450 through the direct memory access controller 430. The processing unit 470 can be implemented in various ways, such as using general-purpose hardware, such as a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, a lightweight general-purpose processor, or other processor with computing power, and providing the functionality described later when executing instructions, macrocode, or microcode. The controller 490 can be a UFS controller, communicating with the host device 110 via the UFS communication protocol. Although this embodiment of the invention uses the UFS communication protocol as an example, the invention can also be applied to other communication protocols, such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), or other interface communication protocols, when other communication protocols allow the host device to directly send read commands containing physical location information in the future.

[0065] The direct memory access controller 430 reads the original entity location information corresponding to each logical location from the entity memory lookup table 210 in the data buffer 450, and the original entity location information is represented using a first number of bytes. An expansion circuit 410 is connected to or coupled to the direct memory access controller 430 to obtain the original entity location information, expand the original entity location information into expanded entity location information represented using a second number of bytes, and outputs the expanded entity location information to the controller 490, where the second number is greater than the first number. The controller 490 is connected to or coupled to the expansion circuit 410 and transmits (or replies to) the expanded entity location information to the master device 110 through the data link layer 320 and the physical layer 310.

[0066] The processing unit 470 is responsible for maintaining the contents of the physical storage lookup table 210, not the main device 110. The physical storage lookup table 210 records which physical location in the flash memory storage unit 390 the user data of each logical location is actually stored in.

[0067] Figure 5 This is a flowchart illustrating a method for generating a physical memory lookup table for a flash memory storage device according to an embodiment of the present invention. This method is implemented by a processing unit 470 when loading and executing instructions, macrocode, or microcode. After receiving a read request 151 from the host device 110 via a controller 490 (step S510), the processing unit 470 drives the flash memory controller 480 to read the physical memory lookup table 210 (i.e., the physical location information corresponding to the logical location range) from the flash memory storage unit 390 and stores it in the data buffer 450 (step S530). It should be noted that the data buffer 450 only needs to be configured to store the original physical memory lookup table 210. Next, the processing unit 470 drives the direct memory access controller 430 to read the physical location information from the physical memory lookup table 210 from the data buffer 450 and outputs it to the expansion circuit 410 (step S550).

[0068] The flash memory controller 480 uses several electronic signals to coordinate data and command transmission with the flash memory cell 390, including data lines, clock signals, and control signals. Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), and Write Enable (WE). The processing unit 470 can communicate with the flash memory cell 390 using a Double Data Rate (DDR) communication protocol, such as an Open NAND Flash Interface (ONFI), a DDR toggle, or other interfaces.

[0069] Flash memory cell 390 may contain multiple memory sub-cells, each communicating with processing unit 470 using its associated access sub-interface. One or more memory sub-cells may be packaged into a die. The access sub-interface and the memory sub-cells connected thereafter are collectively referred to as input / output channels and can be identified by a Logical Unit Number (LUN). In other words, multiple memory sub-cells share a single access sub-interface. For example, when flash memory cell 390 contains four access sub-interfaces, and each access sub-interface connects to four memory sub-cells, flash memory cell 390 has a total of 16 memory sub-cells. Processing unit 470 can drive one of the access sub-interfaces to read data from the specified memory sub-cell. Each memory sub-cell has an independent chip enable (CE) control signal. In other words, when data needs to be read from a specified memory sub-cell, the associated access sub-interface needs to be driven to enable the chip enable control signal of that memory sub-cell. Figure 6 This is a schematic diagram showing the connection between the access sub-interface and multiple memory sub-cells. The processing unit 470 can select one of the connected memory sub-cells 630_0 to 630_i through the access sub-interface 610 using independent chip enable control signals 670_0 to 670_i, and then read data from the specified physical address of the selected memory sub-cell through the shared data line 650.

[0070] refer to Figure 4The expansion circuit 410 expands the entity location information in the entity memory lookup table 210 corresponding to each logical location in read request 151 to the byte length specified by the flash memory standard. Then, the controller 490 obtains the expanded entity location information corresponding to each logical location from the expansion circuit 410 and replies to the master device 110 via the data link layer 320 and the physical layer 310. The physical layer 310 may include differential output pairs (Rx pairs) to transmit data or reply information to the master device 110, and differential input pairs (Tx pairs) to receive data or commands from the master device 110. In some embodiments, the expansion circuit 410 may be integrated into the internals of the direct memory access controller 430.

[0071] Figures 7 to 13 This is a block diagram of an expansion circuit according to an embodiment of the present invention. It should be noted that the flash memory storage device 130 may use more or less than four bytes to store physical location information corresponding to each logical location. The flash memory standard specification may use more than eight bytes, or less than eight bytes but more than the number of bytes used by the flash memory storage device 130, to store physical location information. The present invention is not limited thereto.

[0072] refer to Figure 7 The expansion circuit 410 can generate expanded entity position information using a padding method. Specifically, the expansion circuit 410 receives entity position information from the data buffer 450 via the direct memory access controller 430, adds padding data to obtain the expanded entity position information, and outputs it to the controller 490. Expansion circuits 410_1 to 410_3 are padding-type expansion circuits.

[0073] The expansion circuit 410_1 may include a four-byte padding register 710 and a physical location register 730. The padding register 710 latches a fixed dummy value, such as 0x0000, 0xFFFF, 0xAAAA, or other data patterns. The physical location register 730 is electrically connected to the output of the direct memory access controller 430 and can receive and latch physical location information corresponding to a logical location [0..3]. The controller 490 obtains the dummy value of the padding register 710 as the expanded physical location information [0..3], obtains the physical location information of the physical location register 730 as the expanded physical location information [4..7], and combines them for output to the data link layer 320. The above description may be referred to as pre-padding.

[0074] Similarly, the expansion circuit 410_2 may include a four-byte physical location register 730 and a padding register 710. The controller 490 obtains the physical location information from the physical location register 730 as the expanded physical location information [0..3], obtains the dummy value from the padding register 710 as the expanded physical location information [4..7], and combines them for output to the data link layer 320. The above can be referred to as post-padding.

[0075] The expansion circuit 410_3 uses interleaved-padding to generate the expanded entity location information. The expansion circuit 410_3 may include two two-byte padding registers 710_1 and 710_2, and two two-byte entity location registers 730_1 and 730_2. Padding registers 710_1 and 710_2 can latch identical or different spurious values. Entity location registers 730_1 and 730_2, for example, can latch the entity block number and cell number from the entity location information, respectively. The controller 490 can read the values ​​of entity location register 730_1, padding register 710_1, entity location register 730_2, and padding register 710_2 as the expanded entity location information [0..1], [2..3], [4..5], and [6..7], and combine them for output to the data link layer 320. Those skilled in the art can replace the components in expansion circuit 410_3, for example, by using four single-byte fill registers and four single-byte physical location registers, or by changing the arrangement of the components in expansion circuit 410_3 to achieve a similar but different interleaving and filling method. Therefore, the present invention is not limited thereto.

[0076] Figure 7 The filling expansion circuit 410_1 shown can be further improved by adding a scrambler to encode the entity location information and prevent it from being used maliciously. The scrambler can transpose or otherwise encode the entity location information in the flash memory storage device 130 so that the encoded information cannot be deciphered when the master device 110 or other devices are not configured with a properly set descrambler. Figure 8The improved expansion circuits 410_4 and 410_5 are described. Expansion circuit 410_4 may include an eight-byte scrambling register 750_1 for latching scrambling codes [0..7]. Expansion circuit 410_4 may be further configured with a scrambler 770_1, connected to the outputs of scrambling register 750_1, fill register 710, and entity position register 730, and the input of controller 490. Scrambling register 770_1 uses the value in scrambling register 750_1 to perform scrambling operations on the expanded entity position information and outputs the scrambled expanded entity position information to controller 490. Scrambling register 770_1 may include multiple XOR gates that perform exclusive OR operations on the value in scrambling register 750_1 and the expanded entity position information. Controller 490 then replies with this scrambled expanded entity position information to master device 110.

[0077] The expansion circuit 410_5 may include a four-byte scrambling register 750_2 for latching scrambling codes [0..3]. The expansion circuit 410_5 may also include a scrambler 770_2, connected to the inputs of the scrambling register 750_1, the entity location register 730, and the output of the direct memory access controller 430. The scrambler 770_2 uses the value in the scrambling register 750_2 to perform scrambling operations on the original entity location information and outputs the scrambled entity location information to the entity location register 730. The scrambler 770_2 may include multiple mutually exclusive OR gates to perform mutually exclusive OR operations on the value in the scrambling register 750_1 and the expanded entity location information. The controller 490 obtains the spurious value of the filling register 710 as the expanded entity location information [0..3], obtains the scrambled entity location information of the entity location register 730 as the expanded entity location information [4..7], and combines and outputs it to the data link layer 320 to reply to the master device 110.

[0078] Figure 7 The shown filler expansion circuit 410_2 can be further improved by adding a scrambler 770_1 or 770_2 and a scrambling register 750_1 or 750_2 to encode the (expanded) entity location information and prevent malicious use. Those skilled in the art can deduce the technical details of the modification of the filler expansion circuit 410_2 based on the content of the expansion circuit 410_1 described above; for the sake of brevity, these details will not be elaborated further.

[0079] Figure 7 The filling expansion circuit 410_3 shown can be further improved by adding a scrambler to encode the entity location information and prevent it from being used maliciously. Figure 9The improved expansion circuits 410_6 and 410_7 are described. Expansion circuit 410_6 can be further equipped with a scrambler 770_1, connected to the outputs of scrambling register 750_1, fill registers 710_1 and 710_2, and entity position registers 730_1 and 730_2, and the input of controller 490. Scrambling register 770_1 uses the value in scrambling register 750_1 to perform scrambling operations on the expanded entity position information (combining the values ​​of entity position registers 730_1 and 730_2 and fill registers 710_1 and 710_2), and outputs the scrambled expanded entity position information to controller 490. Controller 490 then replies with this scrambled expanded entity position information to master device 110.

[0080] The expansion circuit 410_7 can be further equipped with a scrambler 770_2, which is connected to the input terminals of the scrambling register 750_2, the entity position registers 730_1 and 730_2, and the output terminal of the direct memory access controller 430. The scrambling register 770_2 uses the value in the scrambling register 750_2 to perform scrambling operations on the original entity position information, and outputs the scrambled entity position information [0..1] and [2..3] to the entity position registers 730_1 and 730_2 respectively. The controller 490 obtains the scrambled entity location information from entity location register 730_1 as the expanded entity location information [0..1], obtains the spurious value of filling register 710_1 as the expanded entity location information [2..3], obtains the scrambled entity location information from entity location register 730_2 as the expanded entity location information [4..5], obtains the spurious value of filling register 710_2 as the expanded entity location information [6..7], and combines and outputs them to data link layer 320 to reply to master device 110.

[0081] Those skilled in the art can replace the components in expansion circuits 410_6 or 410_7, for example, by using four single-byte fill registers and four single-byte physical location registers, or by changing the component arrangement in expansion circuits 410_6 or 410_7 to achieve similar but different interleaving and filling methods. Therefore, the present invention is not limited thereto.

[0082] refer to Figure 4The expansion circuit 410 can generate expanded entity location information using parity coding. Specifically, the expansion circuit 410 receives entity location information from the data buffer 450 and adds more bytes of data to create expanded entity location information with odd parity or even parity, then outputs it to the controller 490, allowing the master device 110 to determine if the expanded entity location information is correct. If the expanded entity location information is incorrect, the master device 110 can request the flash memory storage device to retransmit the entity location information corresponding to this logical location. Expansion circuits 410_8 to 410_10 are parity-type expansion circuits.

[0083] refer to Figure 10 The expansion circuit 410_8 may include a four-byte parity register 780 and a physical location register 730. The expansion circuit 410_8 may further include a parity generator 790, connected to the output of the direct memory access controller 430, to generate additional bytes of data (also called parity bytes) based on the original physical location information, and output the parity bytes to the parity register 780. For example, the parity generator 790 may include a comparator to determine the total number of bits with a value of 1 in the original physical location information. If the total number is odd, the parity generator 790 outputs a parity byte with an even number of bits with a value of 1 (e.g., 0x0000); if the total number is even, it outputs a parity byte with an odd number of bits with a value of 1 (e.g., 0x0001). The controller 490 obtains the parity byte of parity register 780 as the extended entity location information [0..3], obtains the entity location information of entity location register 730 as the extended entity location information [4..7], and combines and outputs the extended entity location information with odd parity to data link layer 320. The above can be referred to as pre-parity.

[0084] Similarly, the expansion circuit 410_9 may include a four-byte physical location register 730 and a parity register 780. The controller 490 obtains the physical location information from the physical location register 730 as the expanded physical location information [0..3], obtains the parity byte from the parity register 780 as the expanded physical location information [4..7], and combines and outputs the expanded physical location information with odd parity to the data link layer 320. The above can be referred to as post-parity.

[0085] In other embodiments, those skilled in the art can modify the parity generator 790 so that if the total number is odd, the parity generator 790 outputs a parity byte with an odd number of bits of value 1 (e.g., 0x0001), and if the total number is even, it outputs a parity byte with an even number of bits of value 1 (e.g., 0x0000), so that the expansion circuit 410_8 or 410_9 can output the expanded entity position information [0..7] with even-numbered bits.

[0086] In some other embodiments, when the lengths of the entity location information and the parity byte are the same, those skilled in the art may omit the parity generator 790. The parity register 780 is connected to the output of the direct memory access controller 430 and latches the original entity location information output by the direct memory access controller 430 as the parity byte. The controller 490 obtains the entity location information from the entity location register 730 as the extended entity location information [0..3], obtains the entity location information from the parity register 780 as the extended entity location information [4..7], and combines and outputs the even-numbered extended entity location information to the data link layer 320.

[0087] The expansion circuit 410_10 generates the expanded entity location information using an interleaved-parity method. The expansion circuit 410_3 may include two two-byte parity registers 780_1 and 780_2, and two two-byte entity location registers 730_1 and 730_2. The expansion circuit 410_10 may further include parity generators 790_1 and 790_2, connected to the output of the direct memory access controller 430. For example, the parity generator 790_1 may include a comparator that determines the total number of bits with a value of 1 in the entity block number of the original entity location information. If the total number is odd, the parity generator 790_1 outputs a parity byte with an even number of bits with a value of 1 (e.g., 0x00); if the total number is even, it outputs a parity byte with an odd number of bits with a value of 1 (e.g., 0x01) to the parity register 780_1. Parity generator 790_2 may include a comparator to determine the total number of bits with a value of 1 in the unit number of the original entity location information. If the total number is odd, parity generator 790_2 outputs a parity byte with an even number of bits with a value of 1 (e.g., 0x00); if the total number is even, it outputs a parity byte with an odd number of bits with a value of 1 (e.g., 0x01) to parity register 780_2. Controller 490 may read the values ​​of entity location register 730_1, parity register 780_1, entity location register 730_2, and parity register 780_2 as the extended entity location information [0..1], [2..3], [4..5], and [6..7] with odd bits, and combine them for output to data link layer 320. Those skilled in the art can replace the components in expansion circuit 410_10, for example, by using four single-byte parity registers and four single-byte physical location registers, or by changing the arrangement of the components in expansion circuit 410_10 to achieve a similar but different interleaving and filling method. Therefore, the present invention is not limited thereto.

[0088] In other embodiments, those skilled in the art can modify parity generators 790_1 and 790_2. If each of parity generators 790_1 and 790_2 detects an odd total, it outputs 0x0001 (i.e., the value 1) as a parity byte; if the total is even, it outputs 0x0000 (i.e., the value 0) as a parity byte, so that the expansion circuit 410_10 can output the expanded entity position information [0..7] with even-numbered bits.

[0089] In some other embodiments, when the lengths of the entity location information and the parity byte are the same, those skilled in the art may omit the parity generators 790_1 and 790_2. Parity registers 780_1 and 780_2 are connected to the output of the direct memory access controller 430 and respectively latch the entity block number and cell number of the original entity location information output by the direct memory access controller 430. The controller 490 obtains the contents of entity location registers 730_1, 780_1, 730_2, and 780_2 as the expanded entity location information [0..1], [2..3], [4..5], and [6..7], and combines and outputs the expanded entity location information with even-numbered bits to the data link layer 320.

[0090] Figure 10 The filling expansion circuit 410_8 shown can be further improved by adding a scrambler to encode the entity location information and prevent it from being used maliciously. Figure 12 The improved expansion circuits 410_11 and 410_12 are described. Expansion circuit 410_11 may include an eight-byte scrambling register 750_1 for latching scrambling codes [0..7]. Expansion circuit 410_4 may be further configured with a scrambler 770_1, connected to the outputs of scrambling register 750_1, parity register 780, and entity position register 730, as well as the input of controller 490. Scrambling register 770_1 uses the value in scrambling register 750_1 to perform scrambling operations on the expanded entity position information and outputs the scrambled expanded entity position information to controller 490.

[0091] Expanding circuit 410_12 may include a four-byte scrambling register 750_2 for latching scrambling codes [0..3]. Expanding circuit 410_5 may be further configured with a scrambler 770_2, connected to the input of scrambling register 750_1, physical location register 730, and the output of direct memory access controller 430. Scrambling register 770_2 uses the value in scrambling register 750_2 to scramble the original physical location information and outputs the scrambled physical location information to physical location register 730. Controller 490 obtains the parity byte of parity register 780 as the expanded physical location information [0..3], obtains the scrambled physical location information from physical location register 730 as the expanded physical location information [4..7], and combines and outputs them to data link layer 320 to reply to master device 110.

[0092] Figure 10The filling expansion circuit 410_9 shown can be further improved by adding a scrambler to encode the (expanded) entity position information, preventing malicious use. Those skilled in the art can infer the technical details of the modification of the filling expansion circuit 410_9 based on the content of the expansion circuit 410_8 described above; for the sake of brevity, these details will not be elaborated further.

[0093] Figure 11 The filling expansion circuit 410_10 shown can be further improved by adding a scrambler to encode the entity location information and prevent it from being used maliciously. Figure 13 The improved expansion circuit 410_13 can be further equipped with a scrambler 770_1, electrically connected to the outputs of scrambling register 750_1, parity registers 780_1 and 780_2, physical location registers 730_1 and 730_2, and the input of controller 490. Scrambler 770_1 uses the value in scrambling register 750_1 to scramble the expanded physical location information (combining the values ​​of physical location registers 730_1 and 730_2, and parity registers 780_1 and 780_2), and outputs the scrambled expanded physical location information to controller 490. Controller 490 then replies with this scrambled expanded physical location information to master device 110.

[0094] In other embodiments, Figure 11 The shown filler expansion circuit 410_10 can be further improved by adding a scrambler 770_2 between the physical location registers 730_1 and 730_2 and the output of the direct memory access controller 430, to encode the physical location information and prevent malicious use. Those skilled in the art can apply the above description... Figure 9 The technical details of the modification of the fill-type expansion circuit 410_10, which are inferred from the content of the expansion circuit 410_7, will not be elaborated here for the sake of brevity.

[0095] The method steps executed by the processing unit 470 can be implemented using a calculator program product composed of one or more functional modules. These functional modules are stored in a non-volatile storage device and can be loaded and executed by the processing unit 470 at a specific point in time. Figure 14This is a schematic diagram of the functional modules for generating a physical storage lookup table for a flash memory storage device according to an embodiment of the present invention. The processing unit 470 executes the read request parsing module 1410 to complete step S510, executes the physical location information read driver module 1430 to complete step S530, and executes the physical location information output driver module 1450 to complete step S550. The read request parsing module 1410 may include a driver program for the controller 490 and a parser to identify the type of the received request and obtain the logical location range from the request. The physical location information read driver module 1430 may include a driver program for the flash memory storage unit 390 and program code for the operation driver. The physical location information output driver module 1450 may include a driver program for the direct memory access controller 430 and program code for the operation driver.

[0096] All or part of the steps in the method described in this invention can be implemented in a calculator program, such as a computer operating system, a driver for specific hardware in the computer, or a software application. Furthermore, they can also be implemented in other types of programs as shown above. Those skilled in the art can write the methods of the embodiments of this invention into calculator programs, which will not be described further for the sake of brevity. Calculator programs implemented according to the methods of the embodiments of this invention can be stored on suitable computer-readable data carriers, such as DVDs, CD-ROMs, USB discs, and hard drives, or placed on a network server accessible via a network (e.g., the Internet, or other suitable carriers).

[0097] Although Figure 4 , 7 -13 includes the components described above, but the use of additional components to achieve better technical results without violating the spirit of the invention is not excluded. Furthermore, although Figure 5 The flowchart describes the steps in a specified order. However, those skilled in the art can modify the order of these steps to achieve the same effect without violating the spirit of the invention. Therefore, this invention is not limited to using only the order described above. Furthermore, those skilled in the art can integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and this invention is not limited thereto.

[0098] While the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. Rather, this invention encompasses modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest possible sense to include all obvious modifications and similar arrangements.

Claims

1. An entity storage map generation apparatus for generating an entity storage map of a flash memory storage device, the apparatus comprising: a map generation unit configured to generate the entity storage map of the flash memory storage device; and a map storage unit configured to store the entity storage map of the flash memory storage device. A direct memory access controller is configured to read the physical storage table from a data buffer to obtain first physical location information corresponding to a logical location, the first physical location information being represented by a first number of bytes, and the physical storage table recording information of where data of each logical location is actually stored in a flash memory unit; An extension circuit is coupled to the direct memory access controller and configured to obtain the first physical location information, extend the first physical location information to second physical location information represented by a second number of bytes, wherein the second number is greater than the first number; and A controller is coupled to the extension circuit and configured to return the second physical location information to a host device; The extension circuit adds padding data to the first physical location information to generate the second physical location information. The controller returns the second physical location information to the host device using a universal flash storage communication protocol. The first physical location information is read from the flash memory unit.

2. The physical storage table generation apparatus of Claim 1, wherein, A processing unit is coupled to a flash memory unit and configured to maintain content of the physical storage table in the flash memory unit.

3. The physical storage reference table generating apparatus according to any one of claims 1 to 2, wherein, The extension circuit includes:

4. The physical storage reference table generating apparatus according to any one of claims 1 to 2, wherein A padding register configured to store a dummy value; and A physical location register configured to store the first physical location information, 5. The physical storage table generation apparatus of Claim 1, wherein, The controller obtains the dummy value and the first physical location information, and combines the dummy value and the first physical location information to generate the second physical location information. The extension circuit generates a parity byte based on the first physical location information, and adds the parity byte to the first physical location information to generate the second physical location information with odd parity or even parity. The extension circuit includes: A parity generator configured to generate the parity byte based on the first physical location information; 6. The physical storage reference table generating apparatus according to any one of claims 1 to 2, wherein A parity register coupled to the parity generator and configured to store the parity byte; and 7. The physical storage table generation apparatus of Claim 6, wherein, A physical location register configured to store the first physical location information, The controller obtains the parity byte and the first physical location information, and combines the parity byte and the first physical location information to generate the second physical location information with odd parity or even parity. The extension circuit includes: A parity register configured to store the first physical location information as a parity byte; and A physical location register configured to store the first physical location information, 8. The physical storage table generation apparatus of Claim 6, wherein, The controller obtains the parity byte and the first physical location information, and combines the parity byte and the first physical location information to generate the second physical location information with even parity. The processing unit notifies the host device that the physical storage table needs to be reacquired in response to modification of the content of the physical storage table. ​ ​ 9. The physical storage table generation apparatus of Claim 4, wherein, ​

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