Data handling method and device, direct memory accessor and computer program product
By performing preprocessing operations on the data to be moved before data transfer, the problem of direct memory accessors being unable to handle data flexibly is solved, and more efficient data transfer is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-31
AI Technical Summary
Direct memory accessors cannot perform flexible preprocessing of the data to be moved before data is moved, which increases the CPU load and reduces data moving efficiency.
By obtaining the target configuration parameters of the data to be moved, preprocessing operations such as deleting invalid bytes and data bit order conversion are performed before the data is moved directly to the target storage unit.
This reduces the load on the central processing unit and improves data transfer efficiency.
Smart Images
Figure CN121764403A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of direct memory accessor technology, and particularly relates to a data transfer method, apparatus, direct memory accessor, and computer program product. Background Technology
[0002] Direct Memory Access (DMA) can directly control the bus and complete data transfer without interrupting the operation of the Central Processing Unit (CPU). Therefore, DMA can greatly reduce the load on the CPU, allowing its resources to be concentrated on complex calculations, thereby improving the system's parallel processing capability and response efficiency. As a result, DMA is now widely used in the field of computer technology.
[0003] However, direct memory accessors have certain limitations when moving data. For example, they cannot perform flexible preprocessing on the data to be moved before moving it. For instance, firstly, direct memory accessors can only perform simple padding on the data to be moved before moving it; secondly, they cannot delete invalid bytes in the data to be moved before moving it; and thirdly, they do not support data bit order conversion on the data to be moved.
[0004] This results in direct memory accessors being unable to flexibly preprocess data according to actual needs when moving data, thereby increasing the load on the central processing unit and reducing the efficiency of data movement. Summary of the Invention
[0005] In view of this, embodiments of this application provide a data transfer method, apparatus, direct memory accessor, and computer program product to solve the technical problem of low efficiency in data transfer in the prior art.
[0006] In a first aspect, embodiments of this application provide a data transfer method applied to a direct memory accessor, the method comprising: The data to be transferred is obtained according to the target configuration parameters of the direct memory accessor; According to the target configuration parameters, a preprocessing operation is performed on a portion of the data to be moved, and the preprocessed portion of the data is then moved to the target storage unit.
[0007] Optionally, the target configuration parameters include the length of the bytes to be moved, the number of bytes read and written each time, the source data base address, the destination data base address, the position of the first valid byte of the input data, the position of the second valid byte of the output data, a first parameter for determining whether the output data is in reverse byte order, a second parameter for determining whether the output address is in reverse address order, a third parameter for determining whether invalid bytes are filled in, and an invalid byte filling value; the step of performing a preprocessing operation on a portion of the data to be moved according to the target configuration parameters, and moving the preprocessed portion of the data to the target storage unit, includes: Based on the length of the bytes to be moved, the number of bytes read and written each time, the source data base address, and the position of the first valid byte, the valid byte data in the partial data is extracted and written into the cache; Based on the length of the bytes to be moved, the number of bytes read and written each time, the destination data base address, the position of the second valid byte, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, the valid byte data in the cache is subjected to specified processing to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit.
[0008] Optionally, extracting valid byte data from the partial data based on the length of the bytes to be moved, the number of bytes read / written each time, the source data base address, and the position of the first valid byte includes: The third valid byte position of the partial data is determined based on the length of the bytes to be transferred, the base address of the source data, and the position of the first valid byte. Based on the position of the third valid byte and the number of bytes read and written each time, extract the valid byte data from the partial data.
[0009] Optionally, the step of performing specified processing on the valid byte data in the cache according to the length of the byte to be moved, the number of bytes read and written each time, the destination data base address, the position of the second valid byte, the first parameter, the second parameter, the third parameter, and the invalid byte padding value to obtain the preprocessed partial data, and moving the preprocessed partial data to the target storage unit, includes: Based on the length of the bytes to be transported, the destination data base address, and the position of the second valid byte, determine the position of the fourth valid byte of the preprocessed data. Based on the fourth valid byte position, the number of bytes read and written each time, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, each valid byte data in the cache is subjected to specified processing to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit.
[0010] Optionally, after writing the valid byte data into the buffer, or after obtaining the preprocessed portion of the data, the method further includes: The number of first bytes of unmoved data in the cache is compared with the number of second bytes of valid bytes corresponding to the second valid byte position. The unmoved data is the data in the cache that is to be moved, excluding the aforementioned portion of data. If the number of the first byte is greater than or equal to the number of the second byte, then the valid byte data in the cache is subjected to specified processing to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit; If the number of the first byte is less than the number of the second byte, then extract the valid byte data from the partial data and write the valid byte data into the cache.
[0011] Optionally, after writing the valid byte data into the buffer, the method further includes: Based on the effective byte length of the data to be transferred, determine whether all the effective bytes have been written into the cache; If all the valid byte data is written into the cache, then it is determined whether all the valid byte data in the cache has completed the preprocessing operation; If all the valid bytes in the cache have completed the preprocessing operation, then it is determined that the partial data has completed the preprocessing operation.
[0012] Optionally, the target configuration parameters include a fourth parameter for determining whether the direct memory accessor has the function of sending an interrupt enable signal; the method further includes: After performing preprocessing operations on all data in the data to be transferred and transferring all preprocessed data to the target storage unit, if the direct memory accessor is determined to have the function of sending an interrupt enable signal according to the fourth parameter, an interrupt signal is sent to the central processing unit.
[0013] Secondly, embodiments of this application provide a data transfer apparatus applied to a direct memory accessor, the apparatus comprising: The data acquisition unit is used to acquire the data to be transferred according to the target configuration parameters of the direct memory accessor; The data processing and transport unit is used to perform preprocessing operations on a portion of the data to be transported according to the target configuration parameters, and then transport the preprocessed portion of the data to the target storage unit.
[0014] Thirdly, embodiments of this application provide a direct memory accessor, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the data transfer method as described in any of the first aspects above.
[0015] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the data transfer method as described in any of the first aspects above.
[0016] Fifthly, embodiments of this application provide a computer program product that, when run on a control device, causes the control device to perform the steps of the data transfer method as described in any of the first aspects above.
[0017] The data transfer method, apparatus, direct memory accessor, and computer program product provided in this application have the following beneficial effects: In the data transfer method provided in this application embodiment, the direct memory accessor (DMI) can first obtain the data to be transferred according to the DMI's target configuration parameters. Then, according to the DMI's target configuration parameters, it performs preprocessing operations on a portion of the data to be transferred and transfers the preprocessed portion to the target storage unit. Through the data transfer method provided in this application, the DMI can perform preprocessing operations on a portion of the data to be transferred according to its target configuration parameters. This allows the DMI to flexibly preprocess the data before transfer, such as deleting invalid bytes and performing data bit order conversion. This eliminates the need for the central processing unit (CPU) to participate in the preprocessing, thus reducing the CPU's load and ultimately improving data transfer efficiency. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart illustrating the implementation of the data transfer method provided in this application embodiment; Figure 2 An example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as provided in an embodiment of this application; Figure 3 An example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as provided in another embodiment of this application; Figure 4 An example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as provided in another embodiment of this application; Figure 5 An example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as provided in another embodiment of this application; Figure 6 An example diagram is provided for an embodiment of this application showing a preprocessing operation performed on a portion of the data to be transferred before transfer; Figure 7 This is a schematic diagram of the structure of a data transfer device provided in an embodiment of this application; Figure 8 This is a schematic diagram of a direct memory accessor provided in an embodiment of this application. Detailed Implementation
[0020] It should be noted that the terminology used in the embodiments of this application is only for explaining specific embodiments of this application and is not intended to limit this application. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, "at least one" or "one or more" means one, two or more. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
[0021] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0022] The execution entity of the data transfer method provided in this application embodiment can be a direct memory accessor (DMI). The data transfer method provided in this application embodiment can be applied to any scenario requiring data transfer via a DMI. For example, if flexible preprocessing of the data to be transferred is required before data transfer via the DMI, the user can first set the target configuration parameters of the DMI, and then execute the various steps of the data transfer method provided in this application embodiment through the DMI. This eliminates the need for the central processing unit (CPU) to participate in the preprocessing of the data to be transferred, reducing the CPU load and improving the efficiency of data transfer.
[0023] Please see Figure 1 , Figure 1 This is a flowchart illustrating the implementation of the data transfer method provided in this application embodiment. The data transfer method provided in this application embodiment can be applied to a direct memory accessor and may include steps S101 to S102, as detailed below: In S101, the data to be transferred is obtained according to the target configuration parameters of the direct memory accessor.
[0024] In this embodiment of the application, the direct memory accessor can obtain the data to be transferred from the initial storage unit storing the data to be transferred.
[0025] In one possible implementation, the target configuration parameters may include, but are not limited to, the length of the bytes to be moved and the base address of the source data. Based on this, the direct memory accessor can obtain the data to be moved from the initial storage unit according to the length of the bytes to be moved and the base address of the source data.
[0026] The length of the bytes to be moved describes the length of the data to be moved. For example, if the length of the bytes to be moved is 12, it means that the length of the data to be moved is 12 bytes.
[0027] The source data base address describes the starting address of the data to be moved in the initial storage unit and is the reference point for the starting position of the direct memory accessor when reading the data to be moved.
[0028] In S102, based on the target configuration parameters, a preprocessing operation is performed on a portion of the data to be moved, and the preprocessed portion of the data is then moved to the target storage unit.
[0029] In this embodiment, the user can pre-input the target configuration parameters into the direct memory accessor, so that the direct memory accessor can perform pre-processing operations on a portion of the data to be transferred according to the target configuration parameters of the direct memory accessor.
[0030] Optionally, in addition to the length of bytes to be moved and the source data base address, the target configuration parameters may include, but are not limited to, any one or more of the following: The parameters include the number of bytes read / written each time, the destination data base address, the position of the first valid byte of the input data, the position of the second valid byte of the output data, the first parameter used to determine whether the output data is in reverse byte order, the second parameter used to determine whether the output address is in reverse address order, the third parameter used to determine whether invalid bytes are filled in the output, and the invalid byte filling value.
[0031] The number of bytes read and written per operation describes the number of bytes corresponding to each read and write operation of the direct memory accessor. For example, if the number of bytes read and written per operation is 4, then each read and write operation of the direct memory accessor is performed in a fixed unit of 4 bytes.
[0032] The destination data base address describes the starting address of the data to be moved in the target storage unit and is the reference point for the starting position of the direct memory accessor when writing the data to be moved.
[0033] The position of the first valid byte of the input data is used to describe the position of valid data in each read. For example, if the number of bytes read and written each time can be 4, the position of the first valid byte of the input data can be configured by a 4-bit binary number ([3:0]), with each bit corresponding to whether the corresponding byte in the 4 bytes of input data is valid. For example, when configured as "0111", only the lower 3 bytes are valid data, and the direct memory accessor will automatically extract the lower 3 bytes and store them in the cache.
[0034] The position of the second valid byte in the output data describes the position of valid data in each written data. For example, if the number of bytes read and written each time can be 4, the position of the second valid byte in the output data can be configured by a 4-bit binary number ([3:0]), where each bit corresponds to whether the corresponding byte in the 4-byte input data is valid. For example, when configured as "1110", only the highest 3 bytes in each written data are valid data.
[0035] The first parameter is used to determine whether the output data is in reverse byte order. For example, if the first parameter is 1, the output data is in reverse byte order; if the first parameter is 0, the output data is not in reverse byte order. For instance, if the byte order of the data to be processed is "byte 03 - byte 02 - byte 01 - byte 00", if the first parameter is 1, the preprocessed data will become "byte 00 - byte 01 - byte 02 - byte 03"; if the first parameter is 0, the preprocessed data will still be "byte 03 - byte 02 - byte 01 - byte 00".
[0036] The second parameter determines whether the output addresses are in reverse order. For example, if the second parameter is 1, the output addresses are in reverse order; if the second parameter is 0, the output addresses are not in reverse order. For instance, if the second parameter is 0, the first word in the data to be transferred will be written to the least significant bit of the target address, and subsequent target addresses will increment sequentially. If the second parameter is 1, the first word in the data to be transferred will be written to the most significant bit of the target address, and subsequent target addresses will decrement sequentially.
[0037] The third parameter is used to determine whether invalid bytes should be padded. For example, if the third parameter is 1, invalid bytes are padded, meaning invalid data in each written data is padded. If the third parameter is 0, invalid bytes are not padded, meaning invalid data in each written data is not padded. For instance, if the number of bytes read / written each time can be 4, and the position of the second valid byte of the output data can be configured as "1110", only the highest 3 bytes of the data written each time are valid data, and the lowest byte is invalid data. If the third parameter is 1, the lowest byte can be padded; if the third parameter is 0, the lowest byte can be left unpadded.
[0038] The invalid byte padding value describes the padding value used when padding invalid bytes in the output. For example, if the invalid byte padding value is 1, and the number of bytes read / written each time can be 4, the position of the second valid byte of the output data can be configured as "1110", and the third parameter is 1, then the lowest byte can be padded with 1; if the invalid byte padding value is 0, and the number of bytes read / written each time can be 4, the position of the second valid byte of the output data can be configured as "1110", and the third parameter is 1, then the lowest byte can be padded with 0.
[0039] To illustrate S102 more clearly, this application provides five examples of performing preprocessing operations on portions of the data to be transported before transport. Please refer to... Figure 2 , Figure 2 This application provides an example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as part of an embodiment of the data to be transferred; please refer to... Figure 3 , Figure 3 An example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as provided in another embodiment of this application; please refer to... Figure 4 , Figure 4 An example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as provided in another embodiment of this application; please refer to... Figure 5 , Figure 5 This application provides an example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as part of another embodiment of the present application; please refer to [link to relevant documentation]. Figure 6 , Figure 6 This application also provides an example diagram illustrating a preprocessing operation performed on a portion of the data to be transferred, as part of an embodiment. The following will be combined with... Figure 2 and Figure 6 The various implementation methods of step S102 are explained in detail.
[0040] In one possible implementation, the direct memory accessor can perform preprocessing operations on a portion of the data to be moved through steps a and b, as detailed below: In step a, based on the length of the bytes to be moved, the number of bytes read and written each time, the source data base address, and the position of the first valid byte, the valid byte data is extracted from the partial data and written into the cache.
[0041] In this implementation, the direct memory accessor can first determine the position of the third valid byte of a portion of the data based on the length of the bytes to be moved, the base address of the source data, and the position of the first valid byte.
[0042] Please see Figure 2 , Figure 2The length of the bytes to be moved is 12, the base address of the source data is 0, and the position of the first valid byte is "1111". Therefore, the position of the third valid byte of some data can be the address where bytes 00~03 are located, the address where bytes 10~13 are located, and the address where bytes 20~23 are located.
[0043] Please see Figure 3 , Figure 3 The length of the bytes to be moved is 12, the base address of the source data is 0, and the position of the first valid byte is "0111". Therefore, the position of the third valid byte of some data can be the address where bytes 00~02 are located, the address where bytes 10~12 are located, the address where bytes 20~22 are located, and the address where bytes 30~32 are located.
[0044] Please see Figure 4 , Figure 4 The length of the bytes to be moved is 8, the base address of the source data is 0, and the position of the first valid byte is "1111". Therefore, the position of the third valid byte of some data can be the address where bytes 00 to 03 are located, or the address where bytes 10 to 13 are located.
[0045] Please see Figure 5 , Figure 5 The length of the bytes to be moved is 12, the base address of the source data is 0, and the position of the first valid byte is "1111". Therefore, the position of the third valid byte of some data can be the address where bytes 00~03 are located, the address where bytes 10~13 are located, and the address where bytes 20~23 are located. (Because...) Figure 5 and Figure 2 Each of them has the same length of bytes to be transferred, source data base address, and position of the first valid byte, therefore Figure 5 The position of the third valid byte determined in the middle is the same as Figure 2 (The position of the third valid byte obtained is the same as that of the first byte) Please see Figure 6 , Figure 6 The length of the bytes to be moved is 7, the base address of the source data is 1, and the position of the first valid byte is "1111". Therefore, the position of the third valid byte of some data can be the address where bytes 00~02 are located, or the address where bytes 10~13 are located (it should be noted that...). Figure 6 The lowest address in the value is the address where the invalid byte is located, therefore Figure 6 The address where the middle byte 00 is located and Figures 2 to 5 The addresses where the middle byte 00 is located are all different.
[0046] After determining the location of the third valid byte of the data, the direct memory accessor can extract the valid bytes from the data based on this location and the number of bytes read / written each time. For example, the number of bytes read / written each time could be 4. Based on this, in... Figure 2 In the process, the first extraction of valid byte data consists of bytes 00 to 03, the second extraction consists of bytes 10 to 13, and the third extraction consists of bytes 20 to 23. Figure 3 In the process, the first extraction of valid byte data consists of bytes 00 to 02, the second extraction consists of bytes 10 to 12, the third extraction consists of bytes 20 to 22, and the fourth extraction consists of bytes 30 to 32. Figure 4 In the first extraction, the valid byte data is bytes 00 to 03, and the valid byte data is bytes 10 to 13. Figure 5 In the process, the first extraction of valid byte data consists of bytes 00 to 03, the second extraction consists of bytes 10 to 13, and the third extraction consists of bytes 20 to 23. Figure 6 In the first extraction, the valid byte data is byte 00 to byte 02, and the valid byte data is byte 10 to byte 13.
[0047] In step b, the valid byte data in the cache is processed according to the length of the byte to be moved, the number of bytes read and written each time, the destination data base address, the position of the second valid byte, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit.
[0048] In this implementation, the direct memory accessor can first determine the position of the fourth valid byte of the preprocessed data based on the length of the byte to be moved, the base address of the destination data, and the position of the second valid byte.
[0049] Please see Figure 2 , Figure 2 The length of the bytes to be moved is 12, the base address of the destination data is 0, and the position of the second valid byte is "0111". Therefore, the position of the fourth valid byte of some data can be the address where bytes 00~02 are located, the address where bytes 03~11 are located, the address where bytes 12~20 are located, and the address where bytes 21~23 are located.
[0050] Please see Figure 3 , Figure 3The length of the bytes to be moved is 12, the base address of the destination data is 0, and the position of the second valid byte is "1111". Therefore, the position of the fourth valid byte of some data can be the address where bytes 00 to 10 are located, the address where bytes 11 to 21 are located, and the address where bytes 22 to 32 are located.
[0051] Please see Figure 4 , Figure 4 The length of the bytes to be moved is 8, the base address of the destination data is 0, and the position of the second valid byte is "0011". Therefore, the position of the fourth valid byte of some data can be the address where bytes 00~01 are located, the address where bytes 03~02 are located, the address where bytes 11~10 are located, and the address where bytes 13~12 are located.
[0052] Please see Figure 5 , Figure 5 The length of the bytes to be moved is 12, the destination data base address is 0, and the second valid byte position is "1111". Therefore, the fourth valid byte position of some data can be the address where bytes 23~20 are located, the address where bytes 13~10 are located, or the address where bytes 03~00 are located. (It should be noted that...) Figure 2 and Figure 5 Their respective lengths of bytes to be transported, destination data base addresses, and positions of the second valid byte are the same, therefore Figure 2 and Figure 5 The positions of the fourth valid byte are actually the same for each, but because Figure 5 The example performs "output address reverse order", therefore Figure 2 and Figure 5 There is a difference in how the fourth valid byte position is represented, that is, Figure 2 The location of the middle byte 00 and Figure 5 The positions of byte 23 are essentially the same; the only difference is in the position of the byte 23. Figure 2 The location where byte 00 is located stores byte 00. Figure 2 The location where byte 23 is located stores byte 23. Please see Figure 6 , Figure 4 The length of the bytes to be moved is 7, the base address of the destination data is 2, and the position of the first valid byte is "1111". Therefore, the position of the fourth valid byte of some data can be the address where bytes 00~01 are located, the address where bytes 02~12 are located, and the position where byte 13 is located (it should be noted that...). Figure 6The bytes corresponding to addresses 0 and 1 can be original bytes, meaning that the bytes corresponding to addresses 0 and 1 can remain unchanged. In addition, if the third parameter is 1, the bytes corresponding to addresses 1+1, 2+2, and 3+3 of byte 13 can all be filled with invalid bytes.
[0053] After determining the location of the fourth valid byte of the data, the direct memory accessor can perform specified processing on each valid byte of data in the cache according to the location of the fourth valid byte, the number of bytes read and written each time, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, to obtain the preprocessed partial data, and then move the preprocessed partial data to the target storage unit.
[0054] by Figure 2 For example, Figure 2 In the example, the number of bytes read / written each time is 4, the first parameter is 0, the second parameter is 0, and the third parameter is 1. Figure 2 In the process, the first time the valid byte data retrieved from the cache is bytes 00 to byte 03, based on Figure 2 The fourth valid byte position shown can be used to place bytes 00 to 02 respectively. Figure 2 The addresses of bytes 00 to 02 shown on the right are used to fill in the address of byte 02 plus 1. The remaining byte 03 can be combined with the valid byte data bytes 10 to 11 extracted in the second extraction and placed into the memory. Figure 2 The addresses of bytes 03 to 11 shown on the right can be filled by adding 1 to the address of byte 11. The remaining bytes 12 and 13 in the second batch of valid byte data can be combined with byte 20 in the third batch of valid byte data. Figure 2 The addresses of bytes 12 to 20 shown on the right can be filled by adding 1 to the address of byte 20. The remaining bytes 21 to 23 from the third extraction of valid byte data can be placed into... Figure 2 The addresses of bytes 21 to 23 are shown on the right, and the address of byte 23 plus 1 can be filled.
[0055] by Figure 3 For example, Figure 3 In the example, the number of bytes read / written each time is 4, the first parameter is 0, the second parameter is 0, and the third parameter is not needed. Figure 3 In the process, the first time the valid byte data retrieved from the cache is byte 00~byte 02, based on Figure 3 The fourth valid byte position shown can be used to place bytes 00 to 02 respectively. Figure 3The addresses shown on the right contain bytes 00 to 02. The second time, the valid bytes retrieved from the cache are bytes 10 to 12. Bytes 10 to 12 can be placed into... Figure 3 The addresses where bytes 10 to 12 are shown on the right. The third time, the valid bytes retrieved from the cache are bytes 20 to 22. Bytes 20 to 22 can be placed into... Figure 3 The addresses where bytes 20-22 are shown on the right indicate that the valid bytes retrieved from the cache on the fourth attempt are bytes 30-32. Bytes 30-32 can then be placed into... Figure 3 The addresses of bytes 30 to 32 shown on the right.
[0056] by Figure 4 For example, Figure 4 In the example, the number of bytes read / written each time is 4, the first parameter is 1, the second parameter is 0, and the third parameter is 1. Figure 4 In the process, the first batch of valid bytes retrieved from the cache consists of bytes 00 to 03. Since the output data needs to be in reverse byte order, byte 00 is placed in the cache. Figure 4 Place byte 01 into the position where byte 00 is shown on the right. Figure 4 The right side shows the location of byte 01, and it can fill the addresses of byte 00 (address + 1) and byte 00 (address + 2) to place byte 02. Figure 4 Place byte 03 into the position where byte 02 is located, as shown on the right. Figure 4 The right side shows the location of byte 03, and it can fill in the addresses of byte 02 (address +1) and byte 02 (address +2). It should be noted that since the first parameter is 1, the output data needs to be in reverse byte order. Figure 4 The location of the middle byte 00 and Figure 2 and Figure 3 The position of byte 00 is different, and the same applies to bytes 01 to 03. The second time, the valid byte data retrieved from the cache is bytes 10 to 13. Following the method of bytes 00 to 03, bytes 10 to 13 can be arranged as follows... Figure 4 As shown on the right, it can be placed, and the addresses of byte 10 + 1 and byte 10 + 2 can be filled, and the addresses of byte 12 + 1 and byte 12 + 2 can also be filled.
[0057] by Figure 5 For example, Figure 5 In the example, the number of bytes read / written each time is 4, the first parameter is 0, the second parameter is 1, and the third parameter is not needed. Figure 5In the process, the first batch of valid byte data retrieved from the cache consists of bytes 00 to 03. Since the output address needs to be in reverse address order, byte 00 is placed in... Figure 4 Place byte 01 into the position where byte 00 is shown on the right. Figure 4 Place byte 02 into the position where byte 01 is shown on the right. Figure 4 Place byte 03 into the position where byte 02 is located, as shown on the right. Figure 4 The location of byte 03 is shown on the right. The second time, the valid byte data retrieved from the cache consists of bytes 10 to 13. Since the output address needs to be in reverse address order, byte 10 is placed in... Figure 4 Place byte 11 at the location of byte 10 shown on the right. Figure 4 Place byte 12 at the position shown on the right where byte 11 is located. Figure 4 Place byte 13 into the position shown on the right where byte 12 is located. Figure 4 The location of byte 13 is shown on the right. The third time, the valid byte data retrieved from the cache consists of bytes 20 to 23. Since the output address needs to be in reverse address order, byte 20 is placed in... Figure 4 Place byte 21 at the location of byte 20 shown on the right. Figure 4 Place byte 22 at the location of byte 21 shown on the right. Figure 4 Place byte 23 at the location of byte 22 shown on the right. Figure 4 The location of byte 23 shown on the right.
[0058] by Figure 6 For example, Figure 6 In the example, the number of bytes read / written each time is 4, the first parameter is 0, the second parameter is 0, and the third parameter is 1. Figure 6 In the process, the first time the valid byte data retrieved from the cache is byte 00~byte 02, based on Figure 6 The fourth valid byte position shown can be used to place bytes 00 to 01 respectively. Figure 6 The addresses shown on the right contain bytes 00 to 01. The valid bytes retrieved from the cache the second time are bytes 10 to 13. Therefore, bytes 02 to 12 can be inserted the second time. Figure 6 The addresses of bytes 02 to 12 shown on the right can be used to insert byte 13 on the third insertion. Figure 6 The address of byte 13 is shown on the right, and the addresses of byte 13 + 1, byte 13 + 2, and byte 13 + 3 are filled.
[0059] In one possible implementation, after writing valid bytes of data into the buffer, or after receiving partial data after preprocessing, the direct memory accessor can perform the following steps: The number of the first byte of unmoved data in the cache is compared with the number of the second byte of valid data corresponding to the second valid byte position. The unmoved data is the data to be moved stored in the cache, excluding some data. If the number of the first byte is greater than or equal to the number of the second byte, the valid byte data in the cache is subjected to specified processing to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit. If the number of the first byte is less than the number of the second byte, the valid byte data in the partial data is extracted and written into the cache.
[0060] by Figure 2 For example, as shown in the example, due to Figure 2 The second valid byte position is "0111", therefore the number of second bytes corresponding to the second valid byte position is 3. The first time the valid byte data is extracted from the cache is bytes 00 to byte 03. Therefore, after the first extraction of valid byte data into the cache, the number of first bytes of unmoved data in the cache is 4, which is greater than the number of second bytes. Therefore, step b is performed to perform specified processing on the valid byte data in the cache to obtain the preprocessed partial data, and then the preprocessed partial data is moved to the target storage unit, thereby placing bytes 00 to byte 02 into the cache. Figure 2 The addresses of bytes 00 to 02 shown on the right can be filled by adding 1 to the address of byte 02. At this point, the number of unmoved first bytes in the cache is 1, which is less than the number of second bytes. Therefore, step a is executed to extract valid bytes from the partial data and write them into the cache. The second extraction of valid bytes is bytes 10 to 13. After the second extraction of valid bytes into the cache, the number of unmoved first bytes in the cache is 5, which is greater than the number of second bytes. Therefore, step b is executed to perform specified processing on the valid bytes in the cache to obtain the preprocessed partial data, and then move the preprocessed partial data to the target storage unit, thereby placing bytes 03 to 11 into the cache. Figure 2 The addresses of bytes 03 to 11 are shown on the right, and the address of byte 11 plus 1 can be filled. At this time, the number of the first byte of unmoved data in the cache is 1. The number of the first byte is less than the number of the second byte. Therefore, step a is executed to extract the valid byte data from the partial data and write the valid byte data into the cache, and so on.
[0061] In one possible implementation, the target configuration parameters may also include a fourth parameter for determining whether the direct memory accessor has the function of sending an interrupt enable signal. After all data to be transferred has undergone preprocessing operations before transfer, and after all preprocessed data has been transferred to the target storage unit, the direct memory accessor may also perform the following steps: If the fourth parameter determines that the direct memory accessor has the function of sending an interrupt enable signal, then an interrupt signal is sent to the central processing unit.
[0062] For example, a fourth parameter of 1 indicates that the direct memory accessor has the function of sending an interrupt enable signal. If the fourth parameter is 1, and all data to be transferred has undergone preprocessing operations before being transferred, and all data after preprocessing operations has been transferred to the target storage unit, the direct memory accessor can send an interrupt signal to the central processing unit.
[0063] As can be seen from the above, in the data transfer method provided in this application embodiment, the direct memory accessor (DMI) can first obtain the data to be transferred according to the DMI's target configuration parameters, and then perform preprocessing operations on a portion of the data to be transferred according to the DMI's target configuration parameters, and then transfer the preprocessed portion of the data to the target storage unit. Through the data transfer method provided in this application, the DMI can perform preprocessing operations on a portion of the data to be transferred according to the DMI's target configuration parameters, allowing the DMI to flexibly preprocess the data before transfer. For example, it can delete invalid bytes in the data to be transferred before transfer, and it can perform data bit order conversion, etc., so that the central processing unit (CPU) does not need to participate in the preprocessing of the data to be transferred, thus reducing the CPU's load and ultimately improving the efficiency of data transfer.
[0064] Based on the data transfer method provided in the above embodiments, this application further provides a data transfer apparatus for implementing the above method embodiments. Please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram of a data transfer device provided in an embodiment of this application. Figure 7 As shown, the data transfer device 70 may include: a data acquisition unit 71 and a data processing and transfer unit 72. Wherein: The data acquisition unit 71 is used to acquire the data to be transferred according to the target configuration parameters of the direct memory accessor.
[0065] The data processing and transport unit 72 is used to perform preprocessing operations on a portion of the data to be transported according to the target configuration parameters, and then transport the preprocessed portion of the data to the target storage unit.
[0066] Optionally, the target configuration parameters include the length of the bytes to be moved, the number of bytes read / written each time, the source data base address, the destination data base address, the position of the first valid byte of the input data, the position of the second valid byte of the output data, a first parameter for determining whether the output data is in reverse byte order, a second parameter for determining whether the output address is in reverse address order, a third parameter for determining whether invalid bytes are padded, and the invalid byte padding value. The data processing and moving unit 72 is specifically used for: Based on the length of the bytes to be moved, the number of bytes read and written each time, the source data base address, and the position of the first valid byte, extract the valid byte data from the partial data and write the valid byte data into the cache; Based on the length of the bytes to be moved, the number of bytes read and written each time, the destination data base address, the position of the second valid byte, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, the valid byte data in the cache is processed in a specified manner to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit.
[0067] Optionally, the data processing and transport unit 72 is specifically used for: Based on the length of the bytes to be transferred, the base address of the source data, and the position of the first valid byte, determine the position of the third valid byte of the partial data; Based on the position of the third valid byte and the number of bytes read and written each time, extract the valid byte data from the partial data.
[0068] Optionally, the data processing and transport unit 72 is specifically used for: Based on the length of the bytes to be transferred, the destination data base address, and the position of the second valid byte, determine the position of the fourth valid byte of the preprocessed data. Based on the position of the fourth valid byte, the number of bytes read and written each time, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, the data of each valid byte in the cache is processed in a specified manner to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit.
[0069] Optionally, the data processing and transport unit 72 is specifically used for: Compare the number of the first byte of the unmoved data in the cache with the number of the second byte of the valid bytes corresponding to the second valid byte position. The unmoved data is the data in the cache that is to be moved, excluding some of the data. If the number of the first byte is greater than or equal to the number of the second byte, then the valid byte data in the cache is subjected to specified processing to obtain the preprocessed partial data, and the preprocessed partial data is moved to the target storage unit. If the number of the first byte is less than the number of the second byte, then extract the valid byte data from the partial data and write the valid byte data into the cache.
[0070] Optionally, the data processing and transport unit 72 is specifically used for: Based on the effective byte length of the data to be transferred, determine whether all effective bytes have been written into the cache; If all valid bytes of data have been written to the cache, then determine whether all valid bytes of data in the cache have been preprocessed. If all valid bytes in the cache have been preprocessed, then it is determined that some data has been preprocessed.
[0071] Optionally, the target configuration parameters include a fourth parameter used to determine whether the direct memory accessor has the function of sending an interrupt enable signal; the data processing and transport unit 72 is specifically used for: After all the data to be moved has undergone preprocessing before being moved, and all the data after preprocessing has been moved to the target storage unit, if the fourth parameter determines that the direct memory accessor has the function of sending an interrupt enable signal, then an interrupt signal is sent to the central processing unit.
[0072] It should be noted that the information interaction and execution process between the above-mentioned units are based on the same concept as the method embodiments of this application. Their specific functions and technical effects can be referred to the method embodiments section, and will not be repeated here.
[0073] Please see Figure 8 , Figure 8 This is a schematic diagram of a direct memory accessor provided in an embodiment of this application. Figure 8 As shown, the direct memory accessor 8 provided in this embodiment may include: a processor 80, a memory 81, and a computer program 82 stored in the memory 81 and executable on the processor 80, such as a program for a data transfer method. When the processor 80 executes the computer program 82, it implements the steps described above in the data transfer method embodiment, for example... Figure 1 S101~S102 are shown. Alternatively, when the processor 80 executes the computer program 82, it implements the functions of each module / unit in the above-described data handling device embodiment, for example... Figure 7 The functions of units 71-72 shown.
[0074] For example, computer program 82 can be divided into one or more modules / units, one or more of which are stored in memory 81 and executed by processor 80 to complete this application. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of computer program 82 in direct memory accessor 8. For example, computer program 82 can be divided into a data acquisition unit 71 and a data processing and transport unit 72; please refer to the specific functions of each unit. Figure 7 The relevant descriptions in the corresponding embodiments are not repeated here.
[0075] Those skilled in the art will understand that Figure 8 This is merely an example of direct memory accessor 8 and does not constitute a limitation on direct memory accessor 8. It may include more or fewer components than illustrated, or combine certain components, or use different components.
[0076] The processor 80 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.
[0077] The memory 81 can be an internal storage unit of the direct memory accessor 8, such as a hard disk or memory within the direct memory accessor 8. The memory 81 can also be an external storage device of the direct memory accessor 8, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, or flash card equipped on the direct memory accessor 8. Furthermore, the memory 81 can include both internal storage units of the direct memory accessor 8 and external storage devices. The memory 81 is used to store computer programs and other programs and data required by the direct memory accessor. The memory 81 can also be used to temporarily store data that has been output or will be output.
[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the data transfer device can be divided into different functional units to complete all or part of the functions described above. The functional units in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0079] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the various method embodiments described above.
[0080] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments above.
[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0082] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0083] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A data movement method, characterized by, The method is applied to a direct memory accessor, and comprises the following steps: According to target configuration parameters of the direct memory accessor, obtaining data to be moved; According to the target configuration parameters, performing a preprocessing operation on part of the data to be moved, and moving the part of the data after the preprocessing operation to a target storage unit.
2. The method of claim 1, wherein, The target configuration parameters include a byte length to be moved, a number of bytes to be read and written each time, a source data base address, a target data base address, a first valid byte position of input data, a second valid byte position of output data, a first parameter for judging whether output data is in reverse order in byte sequence, a second parameter for judging whether an output address is in reverse order in address sequence, a third parameter for judging whether an invalid byte of output is filled, and an invalid byte filling value; the preprocessing operation on the part of the data to be moved according to the target configuration parameters, and the moving of the part of the data after the preprocessing operation to the target storage unit, comprise the following steps: According to the byte length to be moved, the number of bytes to be read and written each time, the source data base address, and the first valid byte position, extracting valid byte data in the part of the data, and writing the valid byte data into a cache; According to the byte length to be moved, the number of bytes to be read and written each time, the target data base address, the second valid byte position, the first parameter, the second parameter, the third parameter, and the invalid byte filling value, performing a specified processing on the valid byte data in the cache, obtaining the part of the data after the preprocessing operation, and moving the part of the data after the preprocessing operation to the target storage unit.
3. The method of claim 2, wherein, The extracting of the valid byte data in the part of the data according to the byte length to be moved, the number of bytes to be read and written each time, the source data base address, and the first valid byte position, comprises the following steps: According to the byte length to be moved, the source data base address, and the first valid byte position, determining a third valid byte position of the part of the data; According to the third valid byte position and the number of bytes to be read and written each time, extracting the valid byte data in the part of the data.
4. The method of claim 2, wherein, The specified processing on the valid byte data in the cache according to the byte length to be moved, the number of bytes to be read and written each time, the target data base address, the second valid byte position, the first parameter, the second parameter, the third parameter, and the invalid byte filling value, obtaining the part of the data after the preprocessing operation, and moving the part of the data after the preprocessing operation to the target storage unit, comprise the following steps: According to the byte length to be moved, the target data base address, and the second valid byte position, determining a fourth valid byte position of the part of the data after the preprocessing operation; According to the fourth valid byte position, the number of bytes read and written each time, the first parameter, the second parameter, the third parameter, and the invalid byte padding value, the valid byte data in the cache is specified to obtain the part of data after the preprocessing operation, and the part of data after the preprocessing operation is carried to the target storage unit.
5. The method of claim 2, wherein, After the valid byte data is written into the cache, or after the part of data after the preprocessing operation is obtained, the method further comprises: comparing the first number of bytes of the uncarried data in the cache with the second number of bytes of the valid byte corresponding to the second valid byte position, the uncarried data being the data in the to-be-carried data saved in the cache except the part of data; if the first number of bytes is greater than or equal to the second number of bytes, the valid byte data in the cache is specified to obtain the part of data after the preprocessing operation, and the part of data after the preprocessing operation is carried to the target storage unit; if the first number of bytes is less than the second number of bytes, the valid byte data in the part of data is extracted, and the valid byte data is written into the cache.
6. The method of claim 2, wherein, After the valid byte data is written into the cache, the method further comprises: determining whether the valid byte data is all written into the cache according to the valid byte length of the to-be-carried data; if the valid byte data is all written into the cache, determining whether the valid byte data in the cache has completed the preprocessing operation; if the valid byte data in the cache has completed the preprocessing operation, it is determined that the part of data has completed the preprocessing operation.
7. The method according to any one of claims 1 to 6, characterized in that, The target configuration parameter includes a fourth parameter for determining whether the direct memory accessor has the function of sending an interrupt enable signal; the method further comprises: after the preprocessing operation before the carrying of all the data in the to-be-carried data is completed, and all the data after the preprocessing operation is carried to the target storage unit, if it is determined according to the fourth parameter that the direct memory accessor has the function of sending the interrupt enable signal, an interrupt signal is sent to the central processing unit.
8. A data handling device, characterized by The device is applied to a direct memory accessor, and the device comprises: a data acquisition unit configured to acquire to-be-carried data according to target configuration parameters of the direct memory accessor; a data processing and carrying unit configured to perform preprocessing operation on part of the to-be-carried data before carrying and carry the part of data after the preprocessing operation to a target storage unit according to the target configuration parameters.
9. A direct memory accessor comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to realize each step in the data carrying method according to any one of claims 1 to 7.
10. A computer program product, characterised in that, The computer program product is executed by the processor to realize each step in the data carrying method according to any one of claims 1 to 7.