Driving circuit, driving method, display substrate and display device

Abstract

The present invention provides a driving circuit, a driving method, a display substrate and a display device. The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit and an output circuit; the first node control circuit controls the potential of the first node; the second node control circuit controls the potential of the second node; the third node control circuit controls the connection or disconnection between the first node and the third node under the control of an on-off control signal; the output circuit controls the output of a driving signal through a driving signal terminal under the control of the potential of the second node and the potential of the third node. The present invention avoids the problem that the high potential of the third node cannot be maintained when the touch stage lasts too long, thereby causing a problem that the display cannot be displayed normally after the touch stage ends.

Description

Technical Field

[0001] The present invention relates to the field of touch display technology, and in particular to a driving circuit, a driving method, a display substrate and a display device. Background Art

[0002] The current development trend of electronic products is to be thinner and lighter with diversified functions, which poses an increasing challenge to the design of display products. With the increasing popularity of active pen applications in display products, embedded touch technology is widely used.

[0003] In the existing driving circuit applied to touch display products, during the LHB (Long Horizontal Blank, intra-frame touch detection) period, the first node is in a floating state. Since the transistor electrically connected to the first electrode or the second electrode and the first node has leakage (especially when the driving circuit adopts a-Si (amorphous silicon) transistor, when the gate-source voltage of the a-Si transistor is 0, the leakage current is large), the potential of the first node will be lower than the potential of the first node of the normal row after the pit (that is, the touch stage ends), resulting in reduced gate driving capability after the pit and insufficient pixel charging capability, resulting in LHB horizontal stripes, and failure to display normally after the touch stage ends. Summary of the invention

[0004] The main purpose of the present invention is to provide a driving circuit, a driving method, a display substrate and a display device to solve the problem in the prior art that when the touch stage lasts too long, the high potential of the third node cannot be maintained, resulting in failure to display normally after the touch stage ends.

[0005] An embodiment of the present invention provides a driving circuit, comprising a first node control circuit, a second node control circuit, a third node control circuit and an output circuit;

[0006] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0007] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0008] The third node control circuit is electrically connected to the on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the on-off control signal provided by the on-off control line;

[0009] The output circuit is electrically connected to the second node, the third node and the drive signal terminal respectively, and is used to control the output of the drive signal through the drive signal terminal under the control of the potential of the second node and the potential of the third node.

[0010] Optionally, the third node control circuit includes a first transistor;

[0011] A gate of the first transistor is electrically connected to the on / off control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the third node.

[0012] Optionally, the on-off control line includes a first on-off control line and a second on-off control line; the third node control circuit includes a first control subcircuit and a second control subcircuit;

[0013] The first control subcircuit is electrically connected to the first on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first on-off control signal provided by the first on-off control line;

[0014] The second control subcircuit is electrically connected to the second on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of a second on-off control signal provided by the second on-off control line.

[0015] Optionally, the first control subcircuit includes a first transistor, and the second control subcircuit includes a second transistor;

[0016] The gate of the first transistor is electrically connected to the first on / off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node;

[0017] A gate of the second transistor is electrically connected to the second on / off control line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

[0018] Optionally, the output circuit includes a third transistor, a fourth transistor and a storage capacitor;

[0019] The gate of the third transistor is electrically connected to the third node, the second electrode of the third transistor is electrically connected to the clock signal line, and the first electrode of the third transistor is electrically connected to the driving signal terminal;

[0020] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the driving signal terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage line;

[0021] The first plate of the storage capacitor is electrically connected to the third node, and the second plate of the storage capacitor is electrically connected to the driving signal terminal.

[0022] Optionally, the output circuit further includes a fifth transistor;

[0023] A gate electrode of the fifth transistor is electrically connected to a frame reset line, a second electrode of the fifth transistor is electrically connected to the driving signal terminal, and a first electrode of the fifth transistor is electrically connected to the first voltage line.

[0024] Optionally, the second node control circuit includes a fourth node control subcircuit and a second node control subcircuit;

[0025] The fourth node control subcircuit is electrically connected to the second voltage line, the fourth node and the first voltage line respectively, and is also electrically connected to the first node or the third node, and is used to control the fourth node to be connected to the second voltage line under the control of the second voltage signal provided by the second voltage line, and to control the fourth node to be connected to the first voltage line under the control of the potential of the first node or the potential of the third node;

[0026] The second node control subcircuit is electrically connected to the fourth node, the second voltage line, the second node and the first voltage line respectively, and the second node control subcircuit is also electrically connected to the first node or the third node, and is used to control the connection between the second node and the second voltage line under the control of the potential of the fourth node, and to control the connection between the second node and the first voltage line under the control of the potential of the first node or the potential of the third node.

[0027] Optionally, the fourth node control subcircuit includes a sixth transistor and a seventh transistor;

[0028] The gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0029] The gate of the seventh transistor is electrically connected to the first node or the third node, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first voltage line;

[0030] The second node control subcircuit includes an eighth transistor and a ninth transistor;

[0031] The gate of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the second node;

[0032] A gate of the ninth transistor is electrically connected to the first node or the third node, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the first voltage line.

[0033] Optionally, the first node control circuit is electrically connected to the input terminal, the reset terminal, the frame reset line, the second node, the first node and the first voltage line, respectively, and is used to control the connection between the input terminal and the first node under the control of the input signal provided by the input terminal, control the connection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal, control the connection between the first node and the first voltage line under the control of the potential of the second node, and control the connection between the first node and the first voltage line under the control of the frame reset signal provided by the frame reset line.

[0034] Optionally, the first node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0035] The gate of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first node;

[0036] The gate of the eleventh transistor is electrically connected to the reset terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the first voltage line;

[0037] The gate of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the first voltage line;

[0038] A gate of the thirteenth transistor is electrically connected to the frame reset line, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the first voltage line.

[0039] An embodiment of the present invention further provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0040] In the display stage, the third node control circuit controls the connection between the first node and the third node under the control of the on-off control signal;

[0041] In the touch control stage, the third node control circuit controls the first node and the third node to be disconnected under the control of the on-off control signal.

[0042] Optionally, the on-off control line includes a first on-off control line and a second on-off control line, and the third node control circuit includes a first control subcircuit and a second control subcircuit;

[0043] The step of controlling the disconnection between the first node and the third node by the third node control circuit under the control of the on-off control signal comprises:

[0044] The first control subcircuit controls the first node and the third node to be disconnected under the control of a first on-off control signal, and the second control subcircuit controls the first node and the third node to be disconnected under the control of a second on-off control signal.

[0045] An embodiment of the present invention further provides a display substrate, comprising a display area disposed on a substrate and a driving module disposed in a peripheral area on the substrate, wherein the driving module comprises a plurality of levels of the above-mentioned driving circuits;

[0046] The third node control circuit is arranged at a side of the output circuit away from the display area, and the on-off control line is arranged at a side of the third node control circuit away from the output circuit.

[0047] Optionally, the third node control circuit includes a first transistor;

[0048] The first transistor includes a first electrode and a second electrode which are arranged in the same layer and are respectively comb-shaped;

[0049] The first electrode of the first transistor includes a plurality of first comb-tooth electrode portions and a first comb-handle electrode portion connecting the plurality of first comb-tooth electrode portions;

[0050] The second electrode of the first transistor includes a plurality of second comb-tooth electrode portions and a second comb-handle electrode portion connected to the plurality of second comb-tooth electrode portions;

[0051] The first comb-teeth electrode portion and the second comb-teeth electrode portion are arranged at intervals.

[0052] Optionally, the on-off control line extends along a first direction; the first transistor further includes a gate, and the gate and the on-off control line are arranged on the same layer; the display substrate further includes a first conductive connecting portion, a second conductive connecting portion, a first conductive transition portion, and a second conductive transition portion;

[0053] The first conductive connection portion and the gate of the first transistor are located in the same layer and are electrically connected to each other, the second conductive connection portion and the first electrode of the first transistor are located in the same layer, the first conductive transition portion and the second conductive transition portion are arranged in the same layer, and the first conductive transition portion and the first conductive connection portion and the second conductive connection portion are located in different layers;

[0054] The on-off control line is electrically connected to the first conductive transition portion through a first via, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via, so that the gate of the first transistor is electrically connected to the on-off control line.

[0055] Optionally, the driving circuit further includes a fourth transistor and a twelfth transistor;

[0056] The first transistor and the fourth transistor are arranged along a first direction, or the first transistor and the twelfth transistor are arranged along the first direction.

[0057] Optionally, the third node control circuit further includes a second transistor; the second transistor includes a first electrode and a second electrode respectively in a comb shape; the first electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor are arranged in the same layer;

[0058] The first electrode of the second transistor includes a plurality of third comb-tooth electrode portions and a third comb-handle electrode portion connected to the plurality of third comb-tooth electrode portions;

[0059] The second electrode of the second transistor includes a plurality of fourth comb-tooth electrode portions and a fourth comb-handle electrode portion connected to the plurality of fourth comb-tooth electrode portions;

[0060] The third comb-tooth electrode portion and the fourth comb-tooth electrode portion are arranged at intervals;

[0061] The third comb handle electrode portion is electrically connected to the first comb handle electrode portion, and the fourth comb handle electrode portion is electrically connected to the second comb handle portion.

[0062] Optionally, the first transistor and the second transistor are arranged along a second direction;

[0063] The second direction intersects the first direction.

[0064] Optionally, the on-off control line includes a first on-off control line and a second on-off control line arranged in the same layer; the first on-off control line extends along a first direction, and the second on-off control line extends along the first direction;

[0065] The first transistor and the second transistor further include a gate, respectively, and the gate and the first on-off control line are arranged on the same layer; the display substrate further includes a first conductive connection portion, a second conductive connection portion, a first conductive transition portion, a second conductive transition portion, a third conductive connection portion, a fourth conductive connection portion, a third conductive transition portion and a fourth conductive transition portion; the first conductive transition portion, the second conductive transition portion, the third conductive transition portion and the fourth conductive transition portion are arranged on the same layer;

[0066] The first conductive connection portion and the gate of the first transistor are located in the same layer and are electrically connected to each other, the second conductive connection portion and the first electrode of the first transistor are located in the same layer, and the first conductive transition portion and the first conductive connection portion and the second conductive connection portion are located in different layers;

[0067] The first on-off control line is electrically connected to the first conductive transition portion through a first via hole, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via hole, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via hole, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via hole, so that the gate of the first transistor is electrically connected to the first on-off control line.

[0068] The third conductive connection portion and the gate of the second transistor are located in the same layer and are electrically connected to each other, the fourth conductive connection portion and the first electrode of the second transistor are located in the same layer, and the third conductive transition portion and the third conductive connection portion and the fourth conductive connection portion are located in different layers;

[0069] The second on-off control line is electrically connected to the third conductive transition portion through a fifth via, the third conductive transition portion is electrically connected to the fourth conductive connection portion through a sixth via, the fourth conductive connection portion is electrically connected to the fourth conductive transition portion through a seventh via, and the fourth conductive transition portion is electrically connected to the third conductive connection portion through an eighth via, so that the gate of the second transistor is electrically connected to the second on-off control line.

[0070] Optionally, the driving circuit further includes a fourth transistor and a twelfth transistor;

[0071] The first transistor and the fourth transistor are arranged along a first direction, and the second transistor and the twelfth transistor are arranged along the first direction; or,

[0072] The first transistor and the twelfth transistor are arranged along a first direction, and the second transistor and the fourth transistor are arranged along the first direction.

[0073] An embodiment of the present invention further provides a display device, comprising the above-mentioned driving circuit or the above-mentioned display substrate.

[0074] The driving circuit, driving method, display substrate and display device described in the embodiments of the present invention avoid the problem that the high potential of the third node cannot be maintained when the touch stage lasts too long, thereby causing failure to display normally after the touch stage ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0076] Figure 2 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0077] Figure 3 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0078] Figure 4 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0079] Figure 5 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0080] Figure 6 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0081] Figure 7 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0082] Figure 8 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0083] Fig. 9 yes Figure 8 The working timing diagram of the embodiment of the driving circuit shown;

[0084] Fig.10 Yes Figure 8 The waveform diagram of the potential of P3 obtained after simulation of the embodiment of the driving circuit shown;

[0085] Fig.11 is a circuit diagram of a driving circuit according to an embodiment of the present invention;

[0086] Fig.12 is a circuit diagram of a driving circuit according to an embodiment of the present invention;

[0087] Fig.13 is a circuit diagram of a driving circuit according to an embodiment of the present invention;

[0088] Fig.14is a structural diagram of an embodiment of a first electrode and a second electrode of a first transistor in a driving circuit in a display substrate according to the present invention;

[0089] Fig.15 is a structural diagram of an embodiment of a first electrode and a second electrode of a second transistor in a driving circuit in a display substrate according to the present invention;

[0090] Fig.16 yes Fig. 20 A layout diagram of the gate metal layer in FIG.

[0091] Fig.17 yes Fig. 20 Layout diagram of source and drain metal layers in FIG.

[0092] Fig.18 yes Fig. 20 A layout diagram of the conductive layer in FIG.

[0093] Fig.19 yes Fig. 20 A layout diagram of the gate metal layer and the source and drain metal layer after being superimposed;

[0094] Fig. 20 yes Fig.13 The layout diagram corresponding to the embodiment of the driving circuit shown in FIG. Fig. 20 , showing a gate metal layer, a source-drain metal layer, a conductive layer and a via);

[0095] Fig.21 This is the layout diagram of the active layer. DETAILED DESCRIPTION

[0096] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0097] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0098] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the gate may be a gate, the first electrode may be a source, and the second electrode may be a drain.

[0099] like Figure 1As shown, the driving circuit according to the embodiment of the present invention includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13 and an output circuit 10;

[0100] The first node control circuit 11 is electrically connected to the first node P1 and is used to control the potential of the first node P1;

[0101] The second node control circuit 12 is electrically connected to the second node P2, and is used to control the potential of the second node P2;

[0102] The third node control circuit 13 is electrically connected to the on-off control line SW, the first node P1 and the third node P3 respectively, and is used to control the connection or disconnection between the first node P1 and the third node P3 under the control of the on-off control signal provided by the on-off control line SW;

[0103] The output circuit 10 is electrically connected to the second node P2, the third node P3 and the driving signal terminal O1 respectively, and is used to control the output of the driving signal through the driving signal terminal O1 under the control of the potential of the second node P2 and the potential of the third node P3.

[0104] The present invention Figure 1 When the embodiment of the driving circuit shown is working, in the touch stage, the third node control circuit 13 controls the disconnection between the first node P1 and the third node P3 under the control of the on-off control signal, closes the leakage path of the third node P3, and can always maintain the potential of the third node P3 in the touch stage; in the display stage, the third node control circuit 13 controls the connection between the first node P1 and the third node P3 under the control of the on-off control signal, so as to perform normal display driving.

[0105] The embodiment of the present invention can avoid the problem that the high potential of the third node P3 cannot be maintained when the touch stage lasts too long, thereby causing the display to fail to function properly after the touch stage ends. The embodiment of the present invention can meet the touch time requirements of different active pen protocols, has wide applicability, and improves the competitiveness of touch display products.

[0106] The embodiment of the present invention cuts off the leakage path of P3, so that after the touch stage of the touch display product, especially the touch display product supporting the active pen, the potential of the third node can be maintained at a high voltage, so that the drive signal can be output normally. The embodiment of the present invention can solve the horizontal stripe problem in the LHB (Long Horizontal Blank, intra-frame touch detection) mode, and can be applied to mobile terminals, laptop computers and other products, but is not limited thereto.

[0107] Optionally, the third node control circuit includes a first transistor;

[0108] A gate of the first transistor is electrically connected to the on / off control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the third node.

[0109] like Figure 2 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the third node control circuit 13 includes a first transistor M1;

[0110] The gate of M1 is electrically connected to the on / off control line SW, the first electrode of M1 is electrically connected to the first node P1, and the second electrode of M1 is electrically connected to the third node P3;

[0111] M1 is an n-type transistor.

[0112] Figure 2 When the embodiment of the driving circuit shown is working, in the display stage, SW outputs a high voltage signal and M1 is turned on; in the touch stage, SW outputs a low voltage signal and M1 is turned off.

[0113] exist Figure 2 In at least one embodiment of the driving circuit shown, M1 can be an a-Si TFT (amorphous silicon thin film transistor). Since the a-Si TFT is in a positive bias state for a long time, its characteristic curve will shift to the right, causing the turn-on current Ion to decrease. When the ratio of the duration of the display phase to the duration of the touch phase is greater than 1, M1 will be in a positive bias state. Under long-term operation or reliability conditions, the characteristic curve of M1 may shift to the right, causing Ion to decrease, resulting in insufficient output of the driving signal. To avoid the above problems, at least one embodiment of the present invention includes two control sub-circuits through a third node control circuit to work alternately in the display phase to avoid the transistor included in the control sub-circuit being in a positive bias state for a long time.

[0114] In at least one embodiment of the present invention, the on-off control line may include a first on-off control line and a second on-off control line; the third node control circuit may include a first control subcircuit and a second control subcircuit;

[0115] The first control subcircuit is electrically connected to the first on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first on-off control signal provided by the first on-off control line;

[0116] The second control subcircuit is electrically connected to the second on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of a second on-off control signal provided by the second on-off control line.

[0117] In a preferred case, two on-off control lines can be used, and the third node control circuit can include two control sub-circuits. In the display stage, the two control sub-circuits work alternately (they can be switched once in each frame or every 2 seconds) to avoid the transistors included in the control sub-circuit being in a positive bias state for a long time, thereby ensuring the service life of the product.

[0118] like Figure 3 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the on-off control line may include a first on-off control line SW1 and a second on-off control line SW2;

[0119] The third node control circuit includes a first control subcircuit 31 and a second control subcircuit 32;

[0120] The first control subcircuit 31 is electrically connected to the first on-off control line SW1, the first node P1 and the third node P3 respectively, and is used to control the connection or disconnection between the first node P1 and the third node P3 under the control of the first on-off control signal provided by the first on-off control line SW1;

[0121] The second control subcircuit 32 is electrically connected to the second on-off control line SW2, the first node P1 and the third node P3, respectively, and is used to control the connection or disconnection between the first node P1 and the third node P3 under the control of a second on-off control signal provided by the second on-off control line SW2.

[0122] The present invention Figure 3 When at least one embodiment of the driving circuit shown is in operation, in the touch control stage, the first control subcircuit 31 controls the first node P1 and the third node P3 to be disconnected under the control of the first on-off control signal, and the second control subcircuit 32 controls the first node P1 and the third node P3 to be disconnected under the control of the second on-off control signal;

[0123] In the display stage, the first control subcircuit 31 and the second control subcircuit work alternately every one frame time or 2 seconds to control the connection between the first node P1 and the third node P3.

[0124] Optionally, the first control subcircuit includes a first transistor, and the second control subcircuit includes a second transistor;

[0125] The gate of the first transistor is electrically connected to the first on / off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node;

[0126] A gate of the second transistor is electrically connected to the second on / off control line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

[0127] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the first control subcircuit 31 includes a first transistor M1, and the second control subcircuit 32 includes a second transistor M2;

[0128] The gate of the first transistor M1 is electrically connected to the first on / off control line SW1, the first electrode of the first transistor M1 is electrically connected to the first node P1, and the second electrode of the first transistor M1 is electrically connected to the third node P3;

[0129] A gate of the second transistor M2 is electrically connected to the second on / off control line SW2 , a first electrode of the second transistor M2 is electrically connected to the first node P1 , and a second electrode of the second transistor M2 is electrically connected to the third node P3 .

[0130] exist Figure 4 In at least one embodiment shown, both M1 and M2 may be n-type transistors.

[0131] The present invention Figure 4 In at least one embodiment shown, when in operation, in the touch control stage, both SW1 and SW2 output low voltage signals, and M1 and M2 are turned off;

[0132] The display phase may include multiple display time periods, each display time period including a first display time period and a second display time period which are sequentially arranged;

[0133] In the first display period, SW1 outputs a high voltage signal, SW2 outputs a low voltage signal, M1 is turned on, and M2 is turned off, so as to control the connection between P1 and P3; in the second display period, SW1 outputs a low voltage signal, SW2 outputs a high voltage signal, M1 is turned off, and M2 is turned on, so as to control the connection between P1 and P3; or,

[0134] In the first display time period, SW2 outputs a high voltage signal, SW1 outputs a low voltage signal, M2 is turned on, and M1 is turned off to control the connection between P1 and P3; in the second display time period, SW2 outputs a low voltage signal, SW1 outputs a high voltage signal, M2 is turned off, and M1 is turned on to control the connection between P1 and P3.

[0135] Optionally, the output circuit includes a third transistor, a fourth transistor and a storage capacitor;

[0136] The gate of the third transistor is electrically connected to the third node, the second electrode of the third transistor is electrically connected to the clock signal line, and the first electrode of the third transistor is electrically connected to the driving signal terminal;

[0137] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the driving signal terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage line;

[0138] The first plate of the storage capacitor is electrically connected to the third node, and the second plate of the storage capacitor is electrically connected to the driving signal terminal.

[0139] Optionally, the output circuit further includes a fifth transistor;

[0140] A gate electrode of the fifth transistor is electrically connected to a frame reset line, a second electrode of the fifth transistor is electrically connected to the driving signal terminal, and a first electrode of the fifth transistor is electrically connected to the first voltage line.

[0141] In a specific implementation, the second node control circuit may include a fourth node control subcircuit and a second node control subcircuit;

[0142] The fourth node control subcircuit is electrically connected to the second voltage line, the fourth node and the first voltage line respectively, and is also electrically connected to the first node or the third node, and is used to control the fourth node to be connected to the second voltage line under the control of the second voltage signal provided by the second voltage line, and to control the fourth node to be connected to the first voltage line under the control of the potential of the first node or the potential of the third node;

[0143] The second node control subcircuit is electrically connected to the fourth node, the second voltage line, the second node and the first voltage line respectively, and the second node control subcircuit is also electrically connected to the first node or the third node, and is used to control the connection between the second node and the second voltage line under the control of the potential of the fourth node, and to control the connection between the second node and the first voltage line under the control of the potential of the first node or the potential of the third node.

[0144] like Figure 5 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the second node control circuit may include a fourth node control subcircuit 51 and a second node control subcircuit 52;

[0145] The fourth node control subcircuit 51 is electrically connected to the second voltage line V2, the fourth node P4, the third node P3 and the first voltage line V1 respectively, and is used to control the fourth node P4 to be connected to the second voltage line V2 under the control of the second voltage signal provided by the second voltage line V2, and to control the fourth node P4 to be connected to the first voltage line V1 under the control of the potential of the third node P3;

[0146] The second node control subcircuit 52 is electrically connected to the fourth node P4, the second voltage line V2, the second node P2, the third node P3 and the first voltage line V1, respectively, and is used to control the connection between the second node P2 and the second voltage line V2 under the control of the potential of the fourth node P4, and to control the connection between the second node P2 and the first voltage line V1 under the control of the potential of the third node P3.

[0147] In at least one embodiment of the present invention, the second voltage line may be a high voltage line, and the first voltage line may be a low voltage line, but the present invention is not limited thereto.

[0148] The present invention Figure 5 When at least one embodiment of the driving circuit shown is in operation, the fourth node control subcircuit 51 controls the potential of the fourth node P4, and the second node control subcircuit 52 controls the potential of the second node P2.

[0149] like Figure 6 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the second node control circuit may include a fourth node control subcircuit 51 and a second node control subcircuit 52;

[0150] The fourth node control subcircuit 51 is electrically connected to the second voltage line V2, the fourth node P4, the first node P1 and the first voltage line V1, respectively, and is used to control the fourth node P4 to be connected to the second voltage line V2 under the control of the second voltage signal provided by the second voltage line V2, and to control the fourth node P4 to be connected to the first voltage line V1 under the control of the potential of the first node P1;

[0151] The second node control subcircuit 52 is electrically connected to the fourth node P4, the second voltage line V2, the second node P2, the first node P1 and the first voltage line V1, respectively, and is used to control the connection between the second node P2 and the second voltage line V2 under the control of the potential of the fourth node P4, and to control the connection between the second node P2 and the first voltage line V1 under the control of the potential of the first node P1.

[0152] In at least one embodiment of the present invention, the second voltage line may be a high voltage line, and the first voltage line may be a low voltage line, but the present invention is not limited thereto.

[0153] The present invention Figure 6 When at least one embodiment of the driving circuit shown is in operation, the fourth node control subcircuit 51 controls the potential of the fourth node P4, and the second node control subcircuit 52 controls the potential of the second node P2.

[0154] Optionally, the fourth node control subcircuit includes a sixth transistor and a seventh transistor;

[0155] The gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0156] The gate of the seventh transistor is electrically connected to the first node or the third node, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first voltage line;

[0157] The second node control subcircuit includes an eighth transistor and a ninth transistor;

[0158] The gate of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the second node;

[0159] A gate of the ninth transistor is electrically connected to the first node or the third node, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the first voltage line.

[0160] In at least one embodiment of the present invention, the first node control circuit is electrically connected to the input terminal, the reset terminal, the frame reset line, the second node, the first node and the first voltage line, respectively, and is used to control the connection between the input terminal and the first node under the control of the input signal provided by the input terminal, control the connection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal, control the connection between the first node and the first voltage line under the control of the potential of the second node, and control the connection between the first node and the first voltage line under the control of the frame reset signal provided by the frame reset line.

[0161] like Figure 7 As shown, in Figure 5On the basis of at least one embodiment of the driving circuit shown, the first node control circuit 11 is electrically connected to the input terminal INPUT, the reset terminal RESET, the frame reset line TRST, the second node P2, the first node P1 and the first voltage line V1, respectively, and is used to control the connection between the input terminal INPUT and the first node P1 under the control of the input signal provided by the input terminal INPUT, control the connection between the first node P1 and the first voltage line V1 under the control of the reset signal provided by the reset terminal RESET, control the connection between the first node P1 and the first voltage line V1 under the control of the potential of the second node P2, and control the connection between the first node and the first voltage line V1 under the control of the frame reset signal provided by the frame reset line TRST.

[0162] Optionally, the first node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0163] The gate of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first node;

[0164] The gate of the eleventh transistor is electrically connected to the reset terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the first voltage line;

[0165] The gate of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the first voltage line;

[0166] A gate of the thirteenth transistor is electrically connected to the frame reset line, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the first voltage line.

[0167] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the third node control circuit 13 includes a first transistor M1; the output circuit includes a third transistor M3, a fourth transistor M4 and a storage capacitor C1;

[0168] The gate of M1 is electrically connected to the on / off control line SW, the first electrode of M1 is electrically connected to the first node P1, and the second electrode of M1 is electrically connected to the third node P3;

[0169] The gate of the third transistor M3 is electrically connected to the third node P3, the second electrode of the third transistor M3 is electrically connected to the clock signal line CLK, and the first electrode of the third transistor M3 is electrically connected to the driving signal terminal OUTPUT;

[0170] The gate of the fourth transistor M4 is electrically connected to the second node P2, the first electrode of the fourth transistor M4 is electrically connected to the driving signal terminal OUTPUT, and the second electrode of the fourth transistor M4 is electrically connected to the low voltage line VGL; the low voltage line VGL is used to provide a low voltage signal;

[0171] The first electrode plate of the storage capacitor C1 is electrically connected to the third node P3, and the second electrode plate of the storage capacitor C1 is electrically connected to the driving signal terminal OUTPUT;

[0172] The output circuit 10 further includes a fifth transistor M5;

[0173] The gate of the fifth transistor M5 is electrically connected to the frame reset line TRST, the second electrode of the fifth transistor M5 is electrically connected to the drive signal terminal OUTPUT, and the first electrode of the fifth transistor M5 is electrically connected to the low voltage line VGL;

[0174] The fourth node control subcircuit 51 includes a sixth transistor M6 and a seventh transistor M7;

[0175] The gate of the sixth transistor M6 and the first electrode of the sixth transistor M6 are electrically connected to a high voltage line VGH, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node P4; the high voltage line VGH is used to provide a high voltage signal;

[0176] A gate of the seventh transistor M7 is electrically connected to the third node P3, a first electrode of the seventh transistor M7 is electrically connected to the fourth node P4, and a second electrode of the seventh transistor M7 is electrically connected to the low voltage line VGL;

[0177] The second node control subcircuit 52 includes an eighth transistor M8 and a ninth transistor M9;

[0178] The gate of the eighth transistor M8 is electrically connected to the fourth node P4, the first electrode of the eighth transistor M8 is electrically connected to the high voltage line VGH, and the second electrode of the eighth transistor M8 is electrically connected to the second node P2;

[0179] The gate of the ninth transistor M9 is electrically connected to the third node P3, the first electrode of the ninth transistor M9 is electrically connected to the second node P2, and the second electrode of the ninth transistor M9 is electrically connected to the low voltage line VGL;

[0180] The first node control circuit 11 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13;

[0181] The gate electrode of the tenth transistor M10 and the first electrode of the tenth transistor M10 are both electrically connected to the input terminal INPUT, and the second electrode of the tenth transistor M10 is electrically connected to the first node P1;

[0182] The gate of the eleventh transistor M11 is electrically connected to the reset terminal RESET, the first electrode of the eleventh transistor M11 is electrically connected to the first node P1, and the second electrode of the eleventh transistor M11 is electrically connected to the low voltage line VGL;

[0183] A gate of the twelfth transistor M12 is electrically connected to the second node P2, a first electrode of the twelfth transistor M12 is electrically connected to the first node P1, and a second electrode of the twelfth transistor M12 is electrically connected to the low voltage line VGL;

[0184] A gate of the thirteenth transistor M13 is electrically connected to the frame reset line TRST, a first electrode of the thirteenth transistor M13 is electrically connected to the first node P1, and a second electrode of the thirteenth transistor M13 is electrically connected to the low voltage line VGL.

[0185] exist Figure 8 In the embodiment shown, all transistors are n-type transistors.

[0186] In at least one embodiment of the present invention, the gate of M7 and the gate of M9 are preferably both electrically connected to the first node P1, so that in the touch stage, M7 and M9 are turned on, so that the potential of P2 is a low voltage, thereby ensuring that M4 is turned off, preventing the potential of P3 from dropping due to leakage of M4 in the touch stage.

[0187] Figure 8 When the embodiment of the driving circuit shown is in operation, in the display stage, SW outputs a high voltage signal, and M1 is turned on, so that P1 and P3 are connected;

[0188] like Fig. 9 As shown, in the first time period S1, INPUT outputs a high voltage signal, M10 is turned on, P1 is pre-charged through M10, the potential of P1 changes from a low voltage to a high voltage, and at the same time SW outputs a high voltage signal, M1 is turned on, P1 is connected to P3, and C1 is charged normally;

[0189] In the touch control stage S0, INPUT outputs a low voltage signal, SW outputs a low voltage signal, P1 is disconnected from P3, and the potential of P3 is maintained at a high voltage because the leakage path between P3 and M10, M11, M13 and M12 is cut off;

[0190] In the second time period S2, the potential of the clock signal provided by the clock signal line CLK changes from a low voltage to a high voltage, SW outputs a high voltage signal, P1 and P3 are connected, the potential of P3 is bootstrapped by C1, M3 is still turned on, and OUTPUT outputs normally;

[0191] In the third time period S3, RESET provides a high voltage signal, SW provides a high voltage signal, the potentials of P1 and P3 are pulled low, and the driving circuit enters a normal display working state.

[0192] Fig.10 Yes Figure 8 The waveform diagram of the potential of P3 obtained after simulation of the embodiment of the driving circuit shown in FIG. Fig.10 In the example, the phase labeled S0 is the touch control phase. Fig.10 It can be seen that in the touch stage S0 , the potential of P3 can be maintained at a high voltage.

[0193] Fig.11 The embodiment of the driving circuit shown is similar to Figure 8 The illustrated embodiment of the driving circuit differs as follows: the gate of M7 and the gate of M9 are both electrically connected to the first node P1.

[0194] Fig.12 The embodiment of the driving circuit shown is similar to Figure 8 The difference between the embodiment of the driving circuit shown is that: the on-off control line may include a first on-off control line SW1 and a second on-off control line SW2; the third node control circuit includes a first control subcircuit 31 and a second control subcircuit 32; the first control subcircuit 31 includes a first transistor M1, and the second control subcircuit 32 includes a second transistor M2;

[0195] The gate of the first transistor M1 is electrically connected to the first on / off control line SW1, the first electrode of the first transistor M1 is electrically connected to the first node P1, and the second electrode of the first transistor M1 is electrically connected to the third node P3;

[0196] A gate of the second transistor M2 is electrically connected to the second on / off control line SW2 , a first electrode of the second transistor M2 is electrically connected to the first node P1 , and a second electrode of the second transistor M2 is electrically connected to the third node P3 .

[0197] exist Fig.12In the illustrated embodiment, all transistors may be n-type transistors.

[0198] Fig.13 The embodiment of the driving circuit shown is similar to Fig.12 The illustrated embodiment of the driving circuit differs as follows: the gate of M7 and the gate of M9 are both electrically connected to the first node P1.

[0199] The driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:

[0200] In the display stage, the third node control circuit controls the connection between the first node and the third node under the control of the on-off control signal;

[0201] In the touch control stage, the third node control circuit controls the first node and the third node to be disconnected under the control of the on-off control signal.

[0202] In the driving method described in the embodiment of the present invention, in the touch stage, the third node control circuit controls the disconnection between the first node and the third node under the control of the on-off control signal, closes the leakage path of the third node, and can maintain the potential of the third node during the touch stage; in the display stage, the third node control circuit controls the connection between the first node and the third node under the control of the on-off control signal to enable normal display driving.

[0203] In a specific implementation, the on-off control line may include a first on-off control line and a second on-off control line, the third node control circuit may include a first control subcircuit and a second control subcircuit; the display stage includes a plurality of display time periods, the display time period includes a first display time period and a second display time period which are sequentially arranged; the driving method includes:

[0204] In the first display time period, the first control subcircuit controls the first node and the third node to be connected under the control of the first on-off control signal; in the second display time period, the second control subcircuit controls the first node and the third node to be connected under the control of the second on-off control signal; or,

[0205] During the first display time period, the second control subcircuit controls the connection between the first node and the third node under the control of the second on-off control signal; during the second display time period, the first control subcircuit controls the connection between the first node and the third node under the control of the first on-off control signal.

[0206] In a preferred case, two on-off control lines can be used, and the third node control circuit can include two control sub-circuits. In the display stage, the two control sub-circuits work alternately (they can be switched once in each frame or every 2 seconds) to avoid the transistors included in the control sub-circuit being in a positive bias state for a long time, thereby ensuring the service life of the product.

[0207] In at least one embodiment of the present invention, the step of controlling the disconnection between the first node and the third node by the third node control circuit under the control of the on-off control signal may include:

[0208] The first control subcircuit controls the first node and the third node to be disconnected under the control of a first on-off control signal, and the second control subcircuit controls the first node and the third node to be disconnected under the control of a second on-off control signal.

[0209] The display substrate described in the embodiment of the present invention comprises a display area arranged on the substrate and a driving module arranged in the peripheral area of ​​the substrate, wherein the driving module comprises a plurality of levels of the above-mentioned driving circuits;

[0210] The third node control circuit is arranged at a side of the output circuit away from the display area, and the on-off control line is arranged at a side of the third node control circuit away from the output circuit.

[0211] In the display substrate described in the embodiment of the present invention, the pixel circuit is arranged in the display area on the substrate, the driving module is arranged in the peripheral area on the substrate, and the output circuit, the third node control circuit and the on-off control line can be arranged in sequence along the direction away from the display area.

[0212] In the driving module, the input terminal of the driving circuit is electrically connected to the driving signal terminal of the adjacent previous-stage driving circuit, and the reset terminal of the driving circuit is electrically connected to the driving signal terminal of the adjacent next-stage driving circuit.

[0213] Optionally, the third node control circuit includes a first transistor;

[0214] The first transistor includes a first electrode and a second electrode which are arranged in the same layer and are respectively comb-shaped;

[0215] The first electrode of the first transistor includes a plurality of first comb-tooth electrode portions and a first comb-handle electrode portion connecting the plurality of first comb-tooth electrode portions;

[0216] The second electrode of the first transistor includes a plurality of second comb-tooth electrode portions and a second comb-handle electrode portion connected to the plurality of second comb-tooth electrode portions;

[0217] The first comb-teeth electrode portion and the second comb-teeth electrode portion are arranged at intervals.

[0218] In at least one embodiment of the present invention, the first transistor may include a first electrode and a second electrode, each of which is in a comb shape;

[0219] like Fig.14 As shown, the first electrode of the first transistor includes a first first comb-tooth electrode portion 111, a second first comb-tooth electrode portion 112, a third first comb-tooth electrode portion 113 and a first comb-handle electrode portion 110 which are electrically connected to each other;

[0220] The second electrode of the first transistor includes a first second comb-tooth electrode portion 121, a second second comb-tooth electrode portion 122, a third second comb-tooth electrode portion 123, a fourth second comb-tooth electrode portion 124 and a second comb-handle electrode portion 120 which are electrically connected to each other;

[0221] The first second comb-tooth electrode portion 121, the first first comb-tooth electrode portion 111, the second second comb-tooth electrode portion 122, the second first comb-tooth electrode portion 112, the third second comb-tooth electrode portion 123, the third first comb-tooth electrode portion 113 and the fourth second comb-tooth electrode portion 124 are arranged in sequence along the second direction.

[0222] exist Fig.14 In the illustrated embodiment, the second direction is a lateral direction, and a gate line is arranged in the display area, and the gate line includes a portion extending in the lateral direction.

[0223] Fig.14 The structure shown is only an embodiment of the structure of the first transistor and is not used to limit the structure of the first transistor.

[0224] In a specific implementation, the on-off control line may extend along a first direction; the first transistor further includes a gate, and the gate and the on-off control line are arranged on the same layer; the display substrate further includes a first conductive connection portion, a second conductive connection portion, a first conductive transition portion, and a second conductive transition portion;

[0225] The first conductive connection portion and the gate of the first transistor are located in the same layer and are electrically connected to each other, the second conductive connection portion and the first electrode of the first transistor are located in the same layer, the first conductive transition portion and the second conductive transition portion are arranged in the same layer, and the first conductive transition portion and the first conductive connection portion and the second conductive connection portion are located in different layers;

[0226] The on-off control line is electrically connected to the first conductive transition portion through a first via, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via, so that the gate of the first transistor is electrically connected to the on-off control line.

[0227] In an embodiment of the present invention, the first conductive connection portion, the on-off control line and the gate of the first transistor are located in the same layer, the second conductive connection portion, the first electrode of the first transistor and the second electrode of the first transistor are located in the same layer, and the first conductive transition portion and the second conductive transition portion are located in the same layer;

[0228] The on-off control line and the gate of the first transistor are electrically connected to each other through a first conductive transition portion and a second conductive transition portion.

[0229] Optionally, the display substrate may include an active layer, a first insulating layer, a gate metal layer, a second insulating layer, a source-drain metal layer, a third insulating layer and a conductive layer sequentially arranged on the base; the gate metal layer is patterned to form a gate, a clock signal line, a high voltage line, a low voltage line, an on-off control line and a first conductive connection portion of a transistor in a driving circuit, the source-drain metal layer is patterned to form a first electrode of the transistor in the driving circuit, a second electrode of the transistor in the driving circuit and a second conductive connection portion, and the conductive layer is patterned to form a first conductive transition portion and a second conductive transition portion;

[0230] The on-off control line is electrically connected to the first conductive transition part through a first via hole penetrating the second insulating layer and the third insulating layer, the first conductive transition part is electrically connected to the second conductive connection part through a second via hole penetrating the third insulating layer, the second conductive connection part is electrically connected to the second conductive transition part through a third via hole penetrating the third insulating layer, and the second conductive transition part is electrically connected to the first conductive connection part through a fourth via hole penetrating the second insulating layer and the third insulating layer, so that the on-off control line is electrically connected to the gate of the first transistor.

[0231] In at least one embodiment of the present invention, the conductive layer may be made of ITO (indium tin oxide).

[0232] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0233] Optionally, the driving circuit further includes a fourth transistor and a twelfth transistor;

[0234] The first transistor and the fourth transistor are arranged along a first direction, or the first transistor and the twelfth transistor are arranged along the first direction.

[0235] In a specific implementation, the first transistor and the fourth transistor included in the driving circuit are arranged along the first direction, or the first transistor and the twelfth transistor included in the driving circuit are arranged along the first direction to narrow the width of the peripheral area along the second direction, thereby facilitating the realization of a narrow frame.

[0236] In at least one embodiment of the present invention, the first direction intersects with the second direction, and multiple rows of gate lines and multiple columns of data lines are arranged in the display area; the first direction can be a direction roughly the same as the extension direction of the data lines, and the second direction can be a direction roughly the same as the extension direction of the gate lines.

[0237] In a specific implementation, the third node control circuit may further include a second transistor; the second transistor includes a first electrode and a second electrode in a comb shape; the first electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor are arranged in the same layer;

[0238] The first electrode of the second transistor includes a plurality of third comb-tooth electrode portions and a third comb-handle electrode portion connected to the plurality of third comb-tooth electrode portions;

[0239] The second electrode of the second transistor includes a plurality of fourth comb-tooth electrode portions and a fourth comb-handle electrode portion connected to the plurality of fourth comb-tooth electrode portions;

[0240] The third comb-tooth electrode portion and the fourth comb-tooth electrode portion are arranged at intervals;

[0241] The third comb handle electrode portion is electrically connected to the first comb handle electrode portion, and the fourth comb handle electrode portion is electrically connected to the second comb handle portion.

[0242] like Fig.15As shown, the first electrode of the second transistor includes a first third comb-tooth electrode portion 131, a second third comb-tooth electrode portion 132, a third third comb-tooth electrode portion 133 and a third comb handle electrode portion 130 which are electrically connected to each other;

[0243] The second electrode of the second transistor includes a first fourth comb-tooth electrode portion 141, a second fourth comb-tooth electrode portion 142, a fourth second comb-tooth electrode portion 143, a fourth fourth comb-tooth electrode portion 144 and a fourth comb-handle electrode portion 140 which are electrically connected to each other;

[0244] The first fourth comb-tooth electrode portion 141, the first third comb-tooth electrode portion 131, the second fourth comb-tooth electrode portion 142, the second third comb-tooth electrode portion 132, the third fourth comb-tooth electrode portion 143, the third third comb-tooth electrode portion 133 and the fourth fourth comb-tooth electrode portion 144 are arranged in sequence along the second direction.

[0245] In an embodiment of the present invention, the first transistor and the second transistor may be arranged along a second direction;

[0246] The second direction intersects the first direction.

[0247] Optionally, the on-off control line includes a first on-off control line and a second on-off control line arranged in the same layer; the first on-off control line extends along a first direction, and the second on-off control line extends along the first direction;

[0248] The first transistor and the second transistor further include a gate, respectively, and the gate and the first on-off control line are arranged on the same layer; the display substrate further includes a first conductive connection portion, a second conductive connection portion, a first conductive transition portion, a second conductive transition portion, a third conductive connection portion, a fourth conductive connection portion, a third conductive transition portion and a fourth conductive transition portion; the first conductive transition portion, the second conductive transition portion, the third conductive transition portion and the fourth conductive transition portion are arranged on the same layer;

[0249] The first conductive connection portion and the gate of the first transistor are located in the same layer and are electrically connected to each other, the second conductive connection portion and the first electrode of the first transistor are located in the same layer, and the first conductive transition portion and the first conductive connection portion and the second conductive connection portion are located in different layers;

[0250] The first on-off control line is electrically connected to the first conductive transition portion through a first via hole, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via hole, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via hole, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via hole, so that the gate of the first transistor is electrically connected to the first on-off control line;

[0251] The third conductive connection portion and the gate of the second transistor are located in the same layer and are electrically connected to each other, the fourth conductive connection portion and the first electrode of the second transistor are located in the same layer, and the third conductive transition portion and the third conductive connection portion and the fourth conductive connection portion are located in different layers;

[0252] The second on-off control line is electrically connected to the third conductive transition portion through a fifth via, the third conductive transition portion is electrically connected to the fourth conductive connection portion through a sixth via, the fourth conductive connection portion is electrically connected to the fourth conductive transition portion through a seventh via, and the fourth conductive transition portion is electrically connected to the third conductive connection portion through an eighth via, so that the gate of the second transistor is electrically connected to the second on-off control line.

[0253] Optionally, the display substrate may include an active layer, a first insulating layer, a gate metal layer, a second insulating layer, a source-drain metal layer, a third insulating layer and a conductive layer sequentially arranged on the base;

[0254] The gate metal layer is patterned to form a gate, a clock signal line, a high voltage line, a low voltage line, a first on / off control line, a second on / off control line, a first conductive connection portion, and a third conductive connection portion of a transistor in a driving circuit; the source / drain metal layer is patterned to form a first electrode of the transistor in the driving circuit, a second electrode of the transistor in the driving circuit, a second conductive connection portion, and a fourth conductive connection portion; the conductive layer is patterned to form a first conductive transition portion, a second conductive transition portion, a third conductive connection portion, and a fourth conductive connection portion;

[0255] The first on-off control line is electrically connected to the first conductive transition portion through a first via hole penetrating the second insulating layer and the third insulating layer, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via hole penetrating the third insulating layer, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via hole penetrating the third insulating layer, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via hole penetrating the second insulating layer and the third insulating layer, so that the first on-off control line is electrically connected to the gate of the first transistor;

[0256] The second on-off control line is electrically connected to the third conductive transition part through a fifth via penetrating the second insulating layer and the third insulating layer, the third conductive transition part is electrically connected to the fourth conductive connection part through a sixth via penetrating the third insulating layer, the fourth conductive connection part is electrically connected to the fourth conductive transition part through a seventh via penetrating the third insulating layer, and the fourth conductive transition part is electrically connected to the third conductive connection part through an eighth via penetrating the second insulating layer and the third insulating layer, so that the second on-off control line is electrically connected to the gate of the second transistor.

[0257] In a specific implementation, the driving circuit may further include a fourth transistor and a twelfth transistor;

[0258] The first transistor and the fourth transistor are arranged along a first direction, and the second transistor and the twelfth transistor are arranged along the first direction; or,

[0259] The first transistor and the twelfth transistor are arranged along a first direction, and the second transistor and the fourth transistor are arranged along the first direction;

[0260] The width of the peripheral area along the second direction is narrowed, which is conducive to achieving a narrow frame.

[0261] Fig. 20 yes Fig.13 The layout diagram corresponding to the embodiment of the driving circuit shown in FIG. Fig. 20 , showing a gate metal layer, a source and drain metal layer, a conductive layer and a via), Fig.16 yes Fig. 20 The layout diagram of the gate metal layer in FIG. 17 is Fig. 20 Layout diagram of source and drain metal layers in Fig.18 yes Fig. 20 The layout diagram of the conductive layer in Fig.19 yes Fig. 20 Layout diagram after the gate metal layer and the source and drain metal layer are superimposed. Fig.21 This is the layout diagram of the active layer.

[0262] exist Fig.16 In the figure, G1 is the gate of the first transistor, L1 is the first conductive connection part, G2 is the gate of the second transistor, L3 is the third conductive connection part, SW1 is the first on-off control line, SW2 is the second on-off control line, VGL is the low voltage line, and VGH is the high voltage line.

[0263] exist Fig.17 In the figure, the second conductive connection portion is labeled L2, the fourth conductive connection portion is labeled L4, the electrode unit is labeled 181 and the electrode unit 181 includes Fig.13 The first electrode of T1 and the second electrode of T1, the electrode unit labeled 182 is included in T2, and the electrode unit 182 of T2 includes Fig.13 The first electrode of T2 and the second electrode of T2.

[0264] exist Fig.18 In the figure, the one labeled Z1 is the first conductive transition portion, the one labeled Z2 is the second conductive transition portion, the one labeled Z3 is the third conductive transition portion, and the one labeled Z4 is the fourth conductive transition portion.

[0265] exist Fig. 20 , the via hole labeled H1 is the first via hole, the via hole labeled H2 is the second via hole, the via hole labeled H3 is the third via hole, the via hole labeled H4 is the fourth via hole, the via hole labeled H5 is the fifth via hole, the via hole labeled H6 is the sixth via hole, the via hole labeled H7 is the seventh via hole, and the via hole labeled H8 is the eighth via hole.

[0266] like Fig. 20 As shown, the first on-off control line SW1 is electrically connected to the first conductive transition portion Z1 through the first via hole H1, the first conductive transition portion Z1 is electrically connected to the second conductive connection portion L2 through the second via hole H2, the second conductive connection portion L2 is electrically connected to the second conductive transition portion Z2 through the third via hole H3, and the second conductive transition portion Z2 is electrically connected to the first conductive connection portion L1 through the fourth via hole H4, so that the gate G1 of the first transistor is electrically connected to the first on-off control line SW1;

[0267] The second on-off control line SW2 is electrically connected to the third conductive transition part Z3 through the fifth via H5, the third conductive transition part Z3 is electrically connected to the fourth conductive connection part L4 through the sixth via H6, the fourth conductive connection part L4 is electrically connected to the fourth conductive transition part Z4 through the seventh via H7, and the fourth conductive transition part Z4 is electrically connected to the third conductive connection part L3 through the eighth via H8, so that the gate G2 of the second transistor is electrically connected to the second on-off control line SW2.

[0268] like Fig.17 As shown, the first electrode of the transistor in the driving circuit and the second electrode of the transistor in the driving circuit are both comb-shaped electrodes.

[0269] exist Fig.17 , the electrode unit 181 included in M1 includes a first electrode of M1 and a second electrode of M1;

[0270] The electrode unit 182 is included in M2, and the electrode unit 182 included in M2 includes a first electrode of M2 and a second electrode of M2;

[0271] The electrode unit 183 included in M3 includes a first electrode of M3 and a second electrode of M3;

[0272] The electrode unit 184 included in M4 includes a first electrode of M4 and a second electrode of M4;

[0273] The electrode unit 185 included in M5 includes a first electrode of M5 and a second electrode of M5;

[0274] The electrode unit 186 included in M6 includes a first electrode of M6 and a second electrode of M6;

[0275] The electrode unit 187 is included in M7, and the electrode unit 187 included in M7 includes a first electrode of M7 and a second electrode of M7;

[0276] The electrode unit 188 is included in M8, and the electrode unit 188 included in M8 includes a first electrode of M8 and a second electrode of M8;

[0277] The electrode unit 189 is included in M9, and the electrode unit 189 includes a first electrode of M9 and a second electrode of M9;

[0278] The electrode unit 1810 is included in M10, and the electrode unit 1810 included in M10 includes a first electrode of M10 and a second electrode of M10;

[0279] The electrode unit 1811 is included in M11, and the electrode unit 1811 included in M11 includes a first electrode of M11 and a second electrode of M11;

[0280] The electrode unit labeled 1812 is included in M12, and the electrode unit 1812 included in M12 includes a first electrode of M12 and a second electrode of M12;

[0281] The electrode unit labeled 1813 is included in M13, and the electrode unit 1813 included in M13 includes a first electrode of M13 and a second electrode of M13.

[0282] exist Fig.17 In the figure, the one labeled C1b is the second electrode plate of C1, and the one labeled OUTPUT is the driving signal terminal.

[0283] exist Fig.17 In the figure, the sixth conductive connection portion is labeled L6, and the sixth conductive connection portion L6 is used to electrically connect the clock signal line CLK and the second electrode of M3.

[0284] exist Fig.16 , the gate labeled G3 is M3, the gate labeled G4 is M4, the gate labeled G5 is M5, the gate labeled G7 is M7, the gate labeled G8 is M8, the gate labeled G9 is M9, the gate labeled G10 is M10, the gate labeled G11 is M11, the gate labeled G12 is M12, and the gate labeled G13 is M13.

[0285] like Fig.16 As shown, the high voltage line VGH is multiplexed as the gate of M6, and the frame reset line is multiplexed as the gate G13 of M13 and the gate G5 of M5.

[0286] like Fig.16 As shown, the gate G3 of M3 is electrically connected to the first electrode plate C1a of C1, the gate G11 of M11 is electrically connected to the reset terminal RESET, and the gate G10 of M10 is electrically connected to the input terminal INPUT.

[0287] exist Fig.16 In the embodiment, the fifth conductive connection portion is labeled L5; L5 is used to electrically connect the first electrode of the fifth transistor and the second electrode of the thirteenth transistor.

[0288] like Fig.16 As shown, the gate of M1 and the gate of M12 are arranged along the first direction, and the gate of M2 and the gate of M4 are arranged along the first direction;

[0289] like Fig.17 As shown, the electrode unit 181 of M1 and the electrode unit 1812 of M12 are arranged along the first direction, and the electrode unit 182 of M2 and the electrode unit 184 of M4 are arranged along the first direction;

[0290] So that M1 and M12 are arranged along the first direction, and M2 and M4 are arranged along the first direction, so as to shorten the width of the peripheral area along the second direction, which is conducive to achieving a narrow frame.

[0291] like Fig.17 As shown, the second electrode plate C1b of C1 is electrically connected to the first electrode of M3 in the electrode unit 183 of M3, and the second electrode plate C1b of C1 is electrically connected to the driving signal terminal OUTPUT.

[0292] like Fig.17 As shown, the first electrode of M1, the first electrode of M2, the first electrode of M13 and the second electrode of M10 are all electrically connected to the third node P3;

[0293] The second electrode of M1, the second electrode of M2, the first electrode of M12 and the first electrode of M11 are all electrically connected to the first node P1;

[0294] The second electrode of M8 and the first electrode of M9 are electrically connected to the second node P2, respectively.

[0295] exist Fig.21 , the active layer pattern labeled 221 is M1, the active layer pattern labeled 222 is M2, the active layer pattern labeled 223 is M3, the active layer pattern labeled 224 is M4, the active layer pattern labeled 225 is M5, the active layer pattern labeled 226 is M6, the active layer pattern labeled 227 is M7, the active layer pattern labeled 228 is M8, the active layer pattern labeled 229 is M9, the active layer pattern labeled 210 is M10, the active layer pattern labeled 211 is M11, the active layer pattern labeled 212 is M12, and the active layer pattern labeled 213 is M13.

[0296] A display device according to at least one embodiment of the present invention includes the above-mentioned driving circuit, or a display device according to at least one embodiment of the present invention includes the above-mentioned display substrate.

[0297] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0298] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: including a first node control circuit, a second node control circuit, a third node control circuit and an output circuit; The first node control circuit is electrically connected to the input terminal, the reset terminal, the second node and the first node respectively, and is used to control the potential of the first node under the control of the input signal provided by the input terminal, the reset signal provided by the reset terminal and the potential of the second node; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The third node control circuit is electrically connected to the on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the on-off control signal provided by the on-off control line; The output circuit is electrically connected to the second node, the third node and the drive signal terminal respectively, and is used to control the output of the drive signal through the drive signal terminal under the control of the potential of the second node and the potential of the third node; The second node control circuit includes a fourth node control subcircuit and a second node control subcircuit; The fourth node control subcircuit is electrically connected to the second voltage line, the fourth node and the first voltage line respectively, and is also electrically connected to the first node or the third node, and is used to control the fourth node to be connected to the second voltage line under the control of the second voltage signal provided by the second voltage line, and to control the fourth node to be connected to the first voltage line under the control of the potential of the first node or the potential of the third node; The second node control subcircuit is electrically connected to the fourth node, the second voltage line, the second node and the first voltage line respectively, and the second node control subcircuit is also electrically connected to the first node or the third node, and is used to control the connection between the second node and the second voltage line under the control of the potential of the fourth node, and to control the connection between the second node and the first voltage line under the control of the potential of the first node or the potential of the third node.

2. The driving circuit according to claim 1, characterized in that: The third node control circuit includes a first transistor; A gate of the first transistor is electrically connected to the on / off control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the third node.

3. The driving circuit according to claim 1, wherein: The on-off control line includes a first on-off control line and a second on-off control line; the third node control circuit includes a first control subcircuit and a second control subcircuit; The first control subcircuit is electrically connected to the first on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first on-off control signal provided by the first on-off control line; The second control subcircuit is electrically connected to the second on-off control line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of a second on-off control signal provided by the second on-off control line.

4. The driving circuit according to claim 3, characterized in that: The first control subcircuit includes a first transistor, and the second control subcircuit includes a second transistor; The gate of the first transistor is electrically connected to the first on / off control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; A gate of the second transistor is electrically connected to the second on / off control line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

5. The driving circuit according to any one of claims 1 to 4, characterized in that: The output circuit includes a third transistor, a fourth transistor and a storage capacitor; The gate of the third transistor is electrically connected to the third node, the second electrode of the third transistor is electrically connected to the clock signal line, and the first electrode of the third transistor is electrically connected to the driving signal terminal; The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the driving signal terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage line; The first plate of the storage capacitor is electrically connected to the third node, and the second plate of the storage capacitor is electrically connected to the driving signal terminal.

6. The driving circuit according to claim 5, characterized in that: The output circuit further includes a fifth transistor; A gate electrode of the fifth transistor is electrically connected to a frame reset line, a second electrode of the fifth transistor is electrically connected to the driving signal terminal, and a first electrode of the fifth transistor is electrically connected to the first voltage line.

7. The driving circuit according to claim 1, characterized in that: The fourth node control subcircuit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the fourth node; The gate of the seventh transistor is electrically connected to the first node or the third node, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first voltage line; The second node control subcircuit includes an eighth transistor and a ninth transistor; The gate of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the second voltage line, and the second electrode of the eighth transistor is electrically connected to the second node; A gate of the ninth transistor is electrically connected to the first node or the third node, a first electrode of the ninth transistor is electrically connected to the second node, and a second electrode of the ninth transistor is electrically connected to the first voltage line.

8. The driving circuit according to any one of claims 1 to 4, characterized in that: The first node control circuit is also electrically connected to the frame reset line and the first voltage line, and is used to control the connection between the input terminal and the first node under the control of the input signal provided by the input terminal, control the connection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal, control the connection between the first node and the first voltage line under the control of the potential of the second node, and control the connection between the first node and the first voltage line under the control of the frame reset signal provided by the frame reset line.

9. The driving circuit according to claim 8, characterized in that: The first node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The gate of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first node; The gate of the eleventh transistor is electrically connected to the reset terminal, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the first voltage line; The gate of the twelfth transistor is electrically connected to the second node, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the first voltage line; A gate of the thirteenth transistor is electrically connected to the frame reset line, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the first voltage line.

10. A driving method, applied to the driving circuit according to any one of claims 1 to 9, characterized in that: The driving method comprises: In the display stage, the third node control circuit controls the connection between the first node and the third node under the control of the on-off control signal; In the touch control stage, the third node control circuit controls the first node and the third node to be disconnected under the control of the on-off control signal.

11. The driving method according to claim 10, characterized in that: The on-off control line includes a first on-off control line and a second on-off control line, and the third node control circuit includes a first control subcircuit and a second control subcircuit; The step of controlling the disconnection between the first node and the third node by the third node control circuit under the control of the on-off control signal comprises: The first control subcircuit controls the first node and the third node to be disconnected under the control of a first on-off control signal, and the second control subcircuit controls the first node and the third node to be disconnected under the control of a second on-off control signal.

12. A display substrate, characterized in that: A driving module comprising a display area disposed on a substrate and a peripheral area disposed on the substrate, wherein the driving module comprises a plurality of driving circuits according to any one of claims 1 to 9; The third node control circuit is arranged at a side of the output circuit away from the display area, and the on-off control line is arranged at a side of the third node control circuit away from the output circuit.

13. The display substrate according to claim 12, wherein: The third node control circuit includes a first transistor; The first transistor includes a first electrode and a second electrode which are arranged in the same layer and are respectively comb-shaped; The first electrode of the first transistor includes a plurality of first comb-tooth electrode portions and a first comb-handle electrode portion connecting the plurality of first comb-tooth electrode portions; The second electrode of the first transistor includes a plurality of second comb-tooth electrode portions and a second comb-handle electrode portion connected to the plurality of second comb-tooth electrode portions; The first comb-teeth electrode portion and the second comb-teeth electrode portion are arranged at intervals.

14. The display substrate according to claim 13, wherein: The on-off control line extends along a first direction; the first transistor further includes a gate, and the gate and the on-off control line are arranged on the same layer; the display substrate further includes a first conductive connecting portion, a second conductive connecting portion, a first conductive transition portion, and a second conductive transition portion; The first conductive connection portion and the gate of the first transistor are located in the same layer and are electrically connected to each other, the second conductive connection portion and the first electrode of the first transistor are located in the same layer, the first conductive transition portion and the second conductive transition portion are arranged in the same layer, and the first conductive transition portion and the first conductive connection portion and the second conductive connection portion are located in different layers; The on-off control line is electrically connected to the first conductive transition portion through a first via, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via, so that the gate of the first transistor is electrically connected to the on-off control line.

15. The display substrate according to claim 14, wherein: The driving circuit further includes a fourth transistor and a twelfth transistor; The first transistor and the fourth transistor are arranged along a first direction, or the first transistor and the twelfth transistor are arranged along the first direction.

16. The display substrate according to claim 13, wherein: The third node control circuit further includes a second transistor; the second transistor includes a first electrode and a second electrode in a comb shape; the first electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the second transistor are arranged in the same layer; The first electrode of the second transistor includes a plurality of third comb-tooth electrode portions and a third comb-handle electrode portion connected to the plurality of third comb-tooth electrode portions; The second electrode of the second transistor includes a plurality of fourth comb-tooth electrode portions and a fourth comb-handle electrode portion connected to the plurality of fourth comb-tooth electrode portions; The third comb-tooth electrode portion and the fourth comb-tooth electrode portion are arranged at intervals; The third comb handle electrode portion is electrically connected to the first comb handle electrode portion, and the fourth comb handle electrode portion is electrically connected to the second comb handle electrode portion.

17. The display substrate according to claim 16, wherein: The first transistor and the second transistor are arranged along a second direction; The second direction intersects the first direction.

18. The display substrate according to claim 16, wherein: The on-off control line includes a first on-off control line and a second on-off control line arranged in the same layer; the first on-off control line extends along a first direction, and the second on-off control line extends along the first direction; The first transistor and the second transistor further include a gate, respectively, and the gate and the first on-off control line are arranged on the same layer; the display substrate further includes a first conductive connection portion, a second conductive connection portion, a first conductive transition portion, a second conductive transition portion, a third conductive connection portion, a fourth conductive connection portion, a third conductive transition portion and a fourth conductive transition portion; the first conductive transition portion, the second conductive transition portion, the third conductive transition portion and the fourth conductive transition portion are arranged on the same layer; The first conductive connection portion and the gate of the first transistor are located in the same layer and are electrically connected to each other, the second conductive connection portion and the first electrode of the first transistor are located in the same layer, and the first conductive transition portion and the first conductive connection portion and the second conductive connection portion are located in different layers; The first on-off control line is electrically connected to the first conductive transition portion through a first via hole, the first conductive transition portion is electrically connected to the second conductive connection portion through a second via hole, the second conductive connection portion is electrically connected to the second conductive transition portion through a third via hole, and the second conductive transition portion is electrically connected to the first conductive connection portion through a fourth via hole, so that the gate of the first transistor is electrically connected to the first on-off control line. The third conductive connection portion and the gate of the second transistor are located in the same layer and are electrically connected to each other, the fourth conductive connection portion and the first electrode of the second transistor are located in the same layer, and the third conductive transition portion and the third conductive connection portion and the fourth conductive connection portion are located in different layers; The second on-off control line is electrically connected to the third conductive transition portion through a fifth via, the third conductive transition portion is electrically connected to the fourth conductive connection portion through a sixth via, the fourth conductive connection portion is electrically connected to the fourth conductive transition portion through a seventh via, and the fourth conductive transition portion is electrically connected to the third conductive connection portion through an eighth via, so that the gate of the second transistor is electrically connected to the second on-off control line.

19. The display substrate according to claim 18, wherein: The driving circuit further includes a fourth transistor and a twelfth transistor; The first transistor and the fourth transistor are arranged along a first direction, and the second transistor and the twelfth transistor are arranged along the first direction; or, The first transistor and the twelfth transistor are arranged along a first direction, and the second transistor and the fourth transistor are arranged along the first direction.

20. A display device, characterized in that: The device comprises a driving circuit as claimed in any one of claims 1 to 9 or a display substrate as claimed in any one of claims 12 to 19.

Images