Semiconductor structure preparation method and semiconductor structure

Abstract

The present application provides a method for fabricating a semiconductor structure, comprising: forming a trench in a semiconductor substrate; forming an oxide layer on the surface of the semiconductor substrate and on the bottom and sidewalls of the trench; partially etching the oxide layer through dry etching to form an oxide region, wherein the oxide region has a stepped structure; and partially etching the oxide region to expose the surface of the edge of the semiconductor substrate, whereby the oxide region serves as an oxide isolation structure after etching. The oxide isolation structure fabricated by the semiconductor structure fabrication method can be used as an isolation structure for nanoelectronic components without affecting the operation of the nanoelectronic components and reducing the active area.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure preparation method and a semiconductor structure. Background Art

[0002] The Local Oxidation of Silicon (LOCOS) structure is a commonly used isolation structure in semiconductor device manufacturing. It is often used to protect the gate from current breakdown, prevent electrons from transferring into the gate, and prevent short circuits between adjacent electronic components (such as field-effect transistors or bipolar transistors). Existing LOCOS structures are mostly bird's beak-shaped. While this LOCOS structure effectively prevents gate breakdown, due to the nanoscale nature of today's electronic components, the bird's beak-shaped LOCOS structure is too large for nanoelectronic components and affects their threshold voltage. Improving the bird's beak-shaped LOCOS structure has become a key issue. Summary of the Invention

[0003] Based on the above, the present application provides a semiconductor structure preparation method and a semiconductor structure, which can solve the problem that the bird's beak-shaped LOCOS structure is too large for nano-electronic components.

[0004] Based on the above-mentioned purpose, the present application provides a method for preparing a semiconductor structure, including: forming a trench in a semiconductor substrate; forming an oxide layer on the surface of the semiconductor substrate and the bottom and sidewalls of the trench; partially etching the oxide layer through dry etching to form an oxide region, wherein the oxide region has a stepped structure; partially etching the oxide region to expose the surface of the edge of the semiconductor substrate, and after etching, the oxide region serves as an oxide isolation structure.

[0005] In an embodiment of the present application, the step of dry-etching a portion of the oxide layer to form an oxide region includes dry-etching a portion of the oxide layer to form multiple oxide sub-layers, and using the multiple oxide sub-layers as the oxide region.

[0006] In an embodiment of the present application, partially etching the oxide region to expose the surface of the edge of the semiconductor substrate includes: partially etching the multilayer oxide sublayer through dry etching to smooth the multilayer oxide sublayer and thin the oxide sublayer in the multilayer oxide sublayer close to the surface of the semiconductor substrate; and partially etching the oxide sublayer in the multilayer oxide sublayer close to the surface of the semiconductor substrate through wet etching to expose the surface of the edge of the semiconductor substrate.

[0007] In an embodiment of the present application, multiple widths of the multi-layer oxide sub-layer projected onto the semiconductor substrate are different from each other, and multiple distances between the multi-layer oxide sub-layer and the surface of the semiconductor substrate are different from each other.

[0008] In an embodiment of the present application, the step of forming the oxidation region by partially etching the oxide layer by dry etching includes: forming a first mask layer on the oxide layer; using the first mask layer as a reference, partially etching the oxide layer to divide the oxide layer into a first oxide sub-layer and a second oxide sub-layer and removing the first mask layer, wherein the second oxide sub-layer is located on the surface of the semiconductor substrate and the first oxide sub-layer is located on the second oxide sub-layer; forming a second mask layer on the first oxide sub-layer and partially on the second oxide sub-layer, wherein the width of the second mask layer projected on the semiconductor substrate is greater than the width of the first mask layer projected on the semiconductor substrate; using the second mask layer as a reference, partially etching the second oxide sub-layer to form a third oxide sub-layer and removing the second mask layer, wherein the second oxide sub-layer is located on the third oxide sub-layer, and the first oxide sub-layer, the second oxide sub-layer and the third oxide sub-layer together constitute the oxidation region.

[0009] In an embodiment of the present application, the distance between the surface of the first oxide sublayer and the surface of the semiconductor substrate is greater than the distance between the surface of the second oxide sublayer and the surface of the semiconductor substrate, and the distance between the surface of the second oxide sublayer and the surface of the semiconductor substrate is greater than the distance between the surface of the third oxide sublayer and the surface of the semiconductor substrate.

[0010] In an embodiment of the present application, the width of the first oxide sublayer projected on the semiconductor substrate is smaller than the width of the second oxide sublayer projected on the semiconductor substrate, and the width of the second oxide sublayer projected on the semiconductor substrate is smaller than the width of the third oxide sublayer projected on the semiconductor substrate.

[0011] In an embodiment of the present application, the step of partially etching the oxide region to expose the surface of the edge of the semiconductor substrate includes: partially etching the first oxide sub-layer, the second oxide sub-layer and the third oxide sub-layer by dry etching to smooth the first oxide sub-layer and the second oxide sub-layer and thin the third oxide sub-layer; and partially etching the third oxide sub-layer by wet etching to expose the surface of the edge of the semiconductor substrate.

[0012] To achieve the above objectives, the present application provides a semiconductor structure comprising a semiconductor substrate, a trench, and an oxide isolation structure. The trench is disposed in the semiconductor substrate. The oxide isolation structure is disposed on a portion of the surface of the semiconductor substrate and on the bottom and sidewalls of the trench and comprises multiple oxide sublayers, wherein the multiple oxide sublayers have different widths projected onto the semiconductor substrate and have different distances from the surface of the semiconductor substrate.

[0013] In an embodiment of the present application, the multilayer oxide sublayer includes a first oxide sublayer and a second oxide sublayer, the first oxide sublayer is located on the second oxide sublayer, the distance between the surface of the first oxide sublayer and the surface of the semiconductor substrate is greater than the distance between the surface of the second oxide sublayer and the surface of the semiconductor substrate, and the width of the first oxide sublayer projected on the semiconductor substrate is less than the width of the second oxide sublayer projected on the semiconductor substrate.

[0014] In an embodiment of the present application, the oxidation isolation structure is a multi-layer platform structure.

[0015] In summary, the semiconductor structure fabrication method of the present application forms a stepped oxide region and etches the region to obtain an oxide isolation structure. The size of this oxide isolation structure is adjustable and can be tailored to accommodate the isolation structure of a nanoelectronic component without affecting the operation of the nanoelectronic component or reducing the active area. The semiconductor structure of the present application, equipped with the aforementioned oxide isolation structure, can be used to isolate adjacent nanoelectronic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present application.

[0017] Figure 2 The flowchart of the method for preparing a semiconductor structure according to one embodiment of the present application is shown.

[0018] Figures 3A to 3J The figures are cross-sectional views of various stages of a method for fabricating a semiconductor structure according to an embodiment of the present application.

[0019] Description of reference numerals:

[0020] 10: Semiconductor substrate

[0021] 20: Oxidation isolation structure

[0022] 30: First mask layer

[0023] 40: Second mask layer

[0024] S11~S14:Steps

[0025] T1: Groove

[0026] OL1: Oxide layer

[0027] OR1: Oxidation zone

[0028] OSL1: first oxide sublayer

[0029] OSL2: Second oxide sublayer

[0030] OSL3: third oxide sublayer DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0032] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in combination with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus.

[0034] See also Figure 1 , which is a cross-sectional view of a semiconductor structure according to an embodiment of the present application. Figure 1 As shown, the semiconductor structure of the present application includes a semiconductor substrate 10, a trench T1, and an oxide isolation structure 20. Trench T1 is disposed in semiconductor substrate 10. Oxide isolation structure 20 is disposed on a portion of the surface of semiconductor substrate 10 and the bottom and sidewalls of trench T1 and includes multiple oxide sublayers. The multiple oxide sublayers have different widths projected onto semiconductor substrate 10 and different distances from the surface of semiconductor substrate 10.

[0035] For example, the oxide isolation structure 20 is a multi-layer mesa structure and includes two oxide sub-layers, namely a first oxide sub-layer OSL1 and a second oxide sub-layer OSL2. The first oxide sub-layer OSL1 is disposed on the second oxide sub-layer OSL2, and the second oxide sub-layer OSL2 is disposed on the semiconductor substrate 10. The distance between the surface of the first oxide sub-layer OSL1 and the surface of the semiconductor substrate 10 is greater than the distance between the surface of the second oxide sub-layer OSL2 and the surface of the semiconductor substrate 10. The width of the first oxide sub-layer OSL1 projected on the semiconductor substrate 10 is smaller than the width of the second oxide sub-layer OSL2 projected on the semiconductor substrate 10. In other words, an edge of the second oxide sub-layer OSL2 protrudes relative to an edge of the first oxide layer OSL1, and the distance between an edge of the second oxide layer OSL2 and an edge of the semiconductor substrate 10 is smaller than the distance between an edge of the first oxide layer OSL1 and an edge of the semiconductor substrate 10. The number of the aforementioned multi-layer oxide sub-layers is merely an example and may be adjusted accordingly according to actual conditions. The number of the aforementioned multi-layer oxide sub-layers may be greater than 2 and is not limited to the range listed in this application.

[0036] See also Figure 2 , which is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present application. Figure 2 As shown, the semiconductor structure preparation method includes steps S11 to S14. Figure 2 The semiconductor structure preparation method shown can be used to manufacture Figure 1 The semiconductor structure shown in FIG. 1 is not limited thereto. The following example illustrates the use of Figure 2 The semiconductor structure preparation method shown is as follows Figure 1 The semiconductor structure shown.

[0037] Step S11: forming a trench T1 in the semiconductor substrate 10. Figure 3A As shown, the trench T1 extends from the surface of the semiconductor substrate 10 to the interior of the semiconductor substrate 10 and terminates in the semiconductor substrate 10; wherein the material of the semiconductor substrate 10 can be silicon, the depth of the trench T1 can range from 200nm to 400nm, and the depth of the trench T1 can be, for example, 300nm.

[0038] In one embodiment, laser etching can be used to etch through the patterned photoresist layer from the surface of the semiconductor substrate 10 to the interior of the semiconductor substrate 10, thereby forming a trench T1 in the semiconductor substrate 10. For example, the depth and opening width of the trench T1 can be controlled by adjusting the laser energy, spot size, and etching time.

[0039] In another embodiment, a dielectric layer is formed on the semiconductor substrate 10, and then a patterned photoresist layer is formed on the dielectric layer. The etching is carried out from the opening of the photoresist layer to the dielectric layer and stops at the surface of the semiconductor substrate 10, thereby forming a through opening in the dielectric layer. The material of the dielectric layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlO x ), hafnium dioxide (HfO2), or a combination thereof. A dielectric layer having an opening is used as a hard mask to etch from the surface of the semiconductor substrate 10 to the interior of the semiconductor substrate 10 to form a trench T1 in the semiconductor substrate 10. The etching may be performed by inductively coupled plasma reactive-ion etching (ICP-RIE) or wet etching, and the depth and opening width of the trench T1 may be controlled by adjusting the concentration of the etching solution and the etching time.

[0040] Step S12: forming an oxide layer OL1 on the surface of the semiconductor substrate 10 and the bottom and sidewalls of the trench T1. Figure 3B As shown, an oxide layer OL1 is formed to fill the trench T1 and cover the surface of the semiconductor substrate 10. The material of the oxide layer OL1 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlOx), hafnium dioxide (HfO2), or a combination thereof. The oxide layer OL1 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or thermal oxidation.

[0041] Step S13: Dry-etching the oxide layer OL1 to form an oxide region, wherein the oxide region has a stepped structure. Specifically, dry-etching the oxide layer to form multiple oxide sub-layers, which serve as the oxide region.

[0042] The number of oxide sub-layers is set to 3 below, and the formation of the oxide region is described below using 3 oxide sub-layers. Figure 3C As shown, a first mask layer 30 is formed on the oxide layer OL1. Figure 3DAs shown, with the pattern of the first mask layer 30 as a reference, the oxide layer OL1 is partially etched using ICP-RIE, and the portions of the oxide layer OL1 located on both sides of the first mask layer 30 are partially etched, so that the oxide layer OL1 is divided into a first oxide sub-layer OSL1 and a second oxide sub-layer OSL2, the second oxide sub-layer OSL2 being located on the surface of the semiconductor substrate 10, and the first oxide sub-layer OSL1 being located on the second oxide sub-layer OSL2; wherein the distance between the surface of the first oxide sub-layer OSL1 and the surface of the semiconductor substrate 10 is greater than the distance between the surface of the second oxide sub-layer OSL2 and the surface of the semiconductor substrate 10, and the width of the first oxide sub-layer OSL1 projected on the semiconductor substrate 10 is smaller than the width of the second oxide sub-layer OSL2 projected on the semiconductor substrate 10. In other words, one edge of the second oxide sub-layer OSL2 is closer to the edge of the semiconductor substrate 10 than one edge of the first oxide sub-layer OSL1. As shown Figure 3E As shown, the first mask layer 30 is removed.

[0043] Then, if Figure 3F As shown, a second mask layer 40 is formed on the first oxide sub-layer OSL1 and a portion of the second oxide sub-layer OSL2, exposing both side edges of the second oxide sub-layer OSL2; wherein the width of the second mask layer 40 projected on the semiconductor substrate 10 is greater than the width of the first mask layer 30 projected on the semiconductor substrate 10. Figure 3G As shown, with the second mask layer 40 as a reference, ICP-RIE is used to partially etch the two side edges of the second oxide sub-layer OSL2 to form a third oxide sub-layer OSL3, and the second oxide sub-layer OSL2 is located on the third oxide sub-layer OSL3; wherein the distance between the surface of the second oxide sub-layer OSL2 and the surface of the semiconductor substrate 10 is greater than the distance between the surface of the third oxide sub-layer OSL3 and the surface of the semiconductor substrate 10, and the width of the second oxide sub-layer OSL2 projected on the semiconductor substrate 10 is smaller than the width of the third oxide sub-layer OSL3 projected on the semiconductor substrate 10. In other words, one edge of the third oxide sub-layer OSL3 is protruding relative to one edge of the second oxide sub-layer OSL2, and one edge of the third oxide sub-layer OSL3 is closer to the edge of the semiconductor substrate 10 than one edge of the second oxide layer OSL2. As shown in FIG. Figure 3H As shown, the second mask layer 40 is removed, and the first oxide sub-layer OSL1 , the second oxide sub-layer OSL2 and the third oxide sub-layer OSL3 serve as oxidation regions; wherein the distance between the surface of the first oxide layer OSL1 and the surface of the semiconductor substrate 10 may be, for example, greater than 120 nm.

[0044] Due to the two etching steps and the fact that the width of the second mask layer 40 is greater than the width of the first mask layer 30, the distances between the surface of the first oxide sub-layer OSL1 and the surface of the semiconductor substrate 10, the distances between the surface of the second oxide sub-layer OSL2 and the surface of the semiconductor substrate 10, and the distances between the surface of the third oxide sub-layer OSL3 and the surface of the semiconductor substrate 10 are different from each other, thereby forming a stepped structure in the oxidized region. Furthermore, because the widths of the first mask layer 30 and the second mask layer 40 are adjustable, and the gas ratio (e.g., the ratio of a high carbon-to-fluorine ratio gas) and the output power of the ICP-RIE are adjustable, the thicknesses of the first oxide sub-layer OSL1, the second oxide sub-layer OSL2, and the third oxide sub-layer OSL3 are adjustable.

[0045] In another embodiment, the oxide layer OL1 is partially etched by laser etching, thereby dividing the oxide layer OL1 into a first oxide sub-layer OSL1, a second oxide sub-layer OSL2, and a third oxide sub-layer OSL3. The first oxide layer OSL1 is disposed on the second oxide sub-layer OSL2, and the second oxide layer OSL2 is disposed on the third oxide sub-layer OSL3. The distance between the surface of the first oxide sub-layer OSL1 and the surface of the semiconductor substrate 10 is greater than the distance between the surface of the second oxide sub-layer OSL2 and the surface of the semiconductor substrate 10, and the distance between the surface of the second oxide sub-layer OSL2 and the surface of the semiconductor substrate 10 is greater than the distance between the surface of the third oxide sub-layer OSL3 and the surface of the semiconductor substrate 10. The width of the first oxide sub-layer OSL1 projected on the semiconductor substrate 10 is smaller than the width of the second oxide sub-layer OSL2 projected on the semiconductor substrate 10, and the width of the second oxide sub-layer OSL2 projected on the semiconductor substrate 10 is smaller than the width of the third oxide sub-layer OSL3 projected on the semiconductor substrate 10.

[0046] Step S14: Partially etching the oxide region to expose the edge surface of the semiconductor substrate 10. After etching, the oxide region serves as an oxide isolation structure. Specifically, dry etching is performed to partially etch the multi-layer oxide sub-layer to smooth the multi-layer oxide sub-layer and thin the oxide sub-layer near the surface of the semiconductor substrate 10. Subsequently, wet etching is performed to partially etch the multi-layer oxide sub-layer near the surface of the semiconductor substrate 10 to expose the edge surface of the semiconductor substrate 10.

[0047] Similarly, this step is described using three oxide sub-layers as an example. Figure 3IAs shown, the first oxide sublayer OSL1, the second oxide sublayer OSL2, and the third oxide sublayer OSL3 are partially etched by ICP-RIE to smooth the first oxide sublayer OSL1 and the second oxide sublayer OSL2 and to thin the third oxide sublayer OSL3. Although the thickness of the third oxide sublayer OSL3 is thinner, the third oxide sublayer OSL3 can still prevent ICP-RIE from damaging the semiconductor substrate 10. At this time, the distance between the surface of the first oxide sublayer OSL1 and the surface of the semiconductor substrate 10 can be, for example, greater than 100 nm. Figure 3J As shown, the third oxide sub-layer OSL3 is partially etched by wet etching to remove the third oxide sub-layer OSL3 so that the edge surface of the semiconductor substrate 10 is exposed. After the wet etching, the first oxide sub-layer OSL1 and the second oxide sub-layer OSL2 serve as the oxide isolation structure 20.

[0048] In summary, the semiconductor structure fabrication method of the present application forms a stepped oxide region and etches the region to obtain an oxide isolation structure. The size of this oxide isolation structure is adjustable and can be tailored to accommodate the isolation structure of a nanoelectronic component without affecting the operation of the nanoelectronic component or reducing the active area. The semiconductor structure of the present application, equipped with the aforementioned oxide isolation structure, can be used to isolate adjacent nanoelectronic components.

Claims

1. A method for preparing a semiconductor structure, characterized in that: Including steps: forming a trench (T1) in a semiconductor substrate (10); forming an oxide layer (OL1) on the surface of the semiconductor substrate (10) and on the bottom and sidewalls of the trench (T1); Partially etching the oxide layer (OL1) by dry etching to form a multi-layer oxide sub-layer, and using the multi-layer oxide sub-layer as an oxide region (OR1), wherein the oxide region (OR1) has a stepped structure; and Partially etching the multilayer oxide sublayer by dry etching to round off the multilayer oxide sublayer and thin the oxide sublayer close to the surface of the semiconductor substrate (10); as well as The oxide sublayers in the multilayer oxide sublayers close to the surface of the semiconductor substrate (10) are partially etched by wet etching to expose the surface of the edge of the semiconductor substrate (10); after etching, the oxide region (OR1) serves as an oxide isolation structure (20).

2. The method for preparing a semiconductor structure according to claim 1, wherein: The multiple widths of the multi-layer oxide sub-layer projected on the semiconductor substrate (10) are different from each other, and the multiple distances between the multi-layer oxide sub-layer and the surface of the semiconductor substrate (10) are different from each other.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The step of partially etching the oxide layer (OL1) by dry etching to form the oxide region (OR1) comprises: forming a first mask layer (30) on the oxide layer (OL1); Taking the first mask layer (30) as a reference, partially etching the oxide layer (OL1) so that the oxide layer (OL1) is divided into a first oxide sublayer (OSL1) and a second oxide sublayer (OSL2), and removing the first mask layer (30), wherein the second oxide sublayer (OSL2) is located on the surface of the semiconductor substrate (10), and the first oxide sublayer (OSL1) is located on the second oxide sublayer (OSL2); forming a second mask layer (40) on the first oxide sublayer (OSL1) and a portion of the second oxide sublayer (OSL2), wherein a width of the second mask layer (40) projected on the semiconductor substrate (10) is greater than a width of the first mask layer (30) projected on the semiconductor substrate (10); and Taking the second mask layer (40) as a reference, the second oxide sublayer (OSL2) is partially etched to form a third oxide sublayer (OSL3) and the second mask layer (40) is removed, wherein the second oxide sublayer (OSL2) is located on the third oxide sublayer (OSL3), and the first oxide sublayer (OSL1), the second oxide sublayer (OSL2) and the third oxide sublayer (OSL3) together constitute the oxide region (OR1).

4. The method for preparing a semiconductor structure according to claim 3, wherein: The distance between the surface of the first oxide sublayer (OSL1) and the surface of the semiconductor substrate (10) is greater than the distance between the surface of the second oxide sublayer (OSL2) and the surface of the semiconductor substrate (10), and the distance between the surface of the second oxide sublayer (OSL2) and the surface of the semiconductor substrate (10) is greater than the distance between the surface of the third oxide sublayer (OSL3) and the surface of the semiconductor substrate (10).

5. The method for preparing a semiconductor structure according to claim 3, wherein: The width of the first oxide sublayer (OSL1) projected on the semiconductor substrate (10) is smaller than the width of the second oxide sublayer (OSL2) projected on the semiconductor substrate (10), and the width of the second oxide sublayer (OSL2) projected on the semiconductor substrate (10) is smaller than the width of the third oxide sublayer (OSL3) projected on the semiconductor substrate (10).

6. The method for preparing a semiconductor structure according to claim 3, wherein: The step of partially etching the oxidized region to expose the surface of the edge of the semiconductor substrate comprises: Partially etching the first oxide sublayer (OSL1), the second oxide sublayer (OSL2), and the third oxide sublayer (OSL3) by dry etching to round the first oxide sublayer (OSL1) and the second oxide sublayer (OSL2) and thin the third oxide sublayer (OSL3); and The third oxide sublayer (OSL3) is partially etched by wet etching to expose the surface of the edge of the semiconductor substrate (10).

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