Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same include: a substrate comprising a base and a device structure located on the substrate; a first dielectric layer located on the substrate, the first dielectric layer having a plurality of first openings therein, the first openings exposing a portion of the surface of the device structure; a conductive structure located within the first openings, the conductive structure comprising a barrier layer located on the sidewalls and bottom surfaces of the first openings and a conductive layer located on the surface of the barrier layer, the conductive structure being electrically connected to the device structure; a stop layer located on the first dielectric layer and the conductive structure; a second dielectric layer located on the stop layer; second openings located within the second dielectric layer and within the stop layer, the second openings exposing the top surface of the conductive layer and portions of the sidewalls of the barrier layer; a reinforcement layer located on the exposed surface of the barrier layer; and an electrical connection layer located within the second openings. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Metal interconnects are essential structures in semiconductor devices, used to interconnect active areas, transistors, or metal lines on different layers, enabling signal transmission and control. Therefore, during semiconductor manufacturing, the formation of metal interconnects significantly impacts semiconductor device performance and manufacturing costs. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between individual semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Typically, during the back-end interconnection process of semiconductor device manufacturing, a first conductive layer (M1) needs to be electrically connected to the underlying active device structures (including source / drain regions and gate structure regions). Therefore, before forming the first conductive layer, a local interconnect structure (Local Interconnect) for the semiconductor device is typically pre-formed. This local interconnect structure includes a zeroth conductive layer (M0) electrically connected to the underlying source / drain regions, and a zeroth gate conductive layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of the semiconductor structure with the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a base and a device structure located on the substrate; a first dielectric layer located on the substrate, the first dielectric layer having a plurality of first openings therein, the first openings exposing a portion of the surface of the device structure; a conductive structure located in the first openings, the conductive structure comprising a barrier layer located on the sidewall surface and bottom surface of the first opening and a conductive layer located on the surface of the barrier layer, the conductive structure being electrically connected to the device structure; a stop layer located on the first dielectric layer and the conductive structure; a second dielectric layer located on the stop layer; second openings located in the second dielectric layer and in the stop layer, the second openings exposing the top surface of the conductive layer and a portion of the sidewall surface of the barrier layer; a reinforcement layer located on the exposed surface of the barrier layer; and an electrical connection layer located in the second openings, the electrical connection layer being located on the surface of the conductive layer and the surface of the reinforcement layer.

[0007] Optionally, it also includes: a reducing layer located on the surface of the barrier layer.

[0008] Optionally, the material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride or tantalum nitride; the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the barrier layer material.

[0009] Optionally, the material of the reduction layer includes titanium-rich titanium nitride or tantalum-rich tantalum nitride.

[0010] Optionally, the ratio of the thickness of the reducing layer to the thickness of the barrier layer is greater than 2:3.

[0011] Optionally, the material of the enhancement layer includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0012] Optionally, the ratio of the thickness of the reinforcement layer to the thickness of the barrier layer is greater than 2:3.

[0013] Optionally, the material of the electrical connection layer includes metal, and the metal includes tungsten.

[0014] Optionally, the material of the stop layer is different from the material of the second dielectric layer.

[0015] Optionally, the material of the stop layer includes silicon nitride.

[0016] Optionally, the substrate further includes: a third dielectric layer located on the base, and the device structure is located in the third dielectric layer; the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0017] Optionally, the substrate further has a fin structure.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base and a device structure located on the base; forming a first dielectric layer on the substrate, the first dielectric layer having a plurality of first openings therein, the first openings exposing a portion of the surface of the device structure; forming a conductive structure in the first opening, the conductive structure comprising a barrier layer located on the sidewall surface and the bottom surface of the first opening and a conductive layer located on the surface of the barrier layer, the conductive structure being electrically connected to the device structure; forming a stop layer on the first dielectric layer and the conductive structure; forming a second dielectric layer on the stop layer; forming second openings in the second dielectric layer and in the stop layer, the second openings exposing the top surface of the conductive layer and a portion of the sidewall surface of the barrier layer; forming an enhancement layer on the exposed surface of the barrier layer; after forming the enhancement layer, forming an electrical connection layer in the second opening using a selective deposition process, the growth rate of the electrical connection layer on the enhancement layer being greater than the growth rate on the barrier layer.

[0019] Optionally, it is characterized in that before the enhancement layer is formed on the exposed surface of the barrier layer, the method further comprises: performing a reduction treatment on the surface of the barrier layer to form a reduction layer.

[0020] Optionally, the process of performing reduction treatment on the surface of the barrier layer includes a gas reduction process, and the gas of the gas reduction process includes hydrogen.

[0021] Optionally, the ratio of the thickness of the reducing layer to the thickness of the barrier layer is greater than 2:3.

[0022] Optionally, the process of forming the second opening in the second dielectric layer further includes: forming an oxide layer on the surface of the conductive layer; and performing a reduction treatment on the surface of the barrier layer while also performing a reduction treatment on the oxide layer on the surface of the conductive layer.

[0023] Optionally, the material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride or tantalum nitride; the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the barrier layer material.

[0024] Optionally, the material of the reduction layer includes titanium-rich titanium nitride or tantalum-rich tantalum nitride.

[0025] Optionally, the material of the conductive layer includes metal, and the metal includes cobalt.

[0026] Optionally, the material of the enhancement layer includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0027] Optionally, the process of forming the enhancement layer includes a selective deposition process.

[0028] Optionally, the ratio of the thickness of the reinforcement layer to the thickness of the barrier layer is greater than 2:3.

[0029] Optionally, the material of the electrical connection layer includes metal, and the metal includes tungsten.

[0030] Optionally, process parameters of the selective deposition process for forming the electrical connection layer include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0031] Optionally, the method for forming a second opening in the second dielectric layer includes: forming a mask layer on the second dielectric layer, wherein the mask layer exposes the surface of the second dielectric layer on the conductive structure; etching the second dielectric layer and the stop layer using the mask layer as a mask until a portion of the sidewall surface of the blocking layer is exposed to form the second opening.

[0032] Optionally, the process of etching the second dielectric layer includes a dry etching process, and the gas used in the dry etching process includes carbon fluorine gas.

[0033] Optionally, the substrate further includes: a third dielectric layer located on the base, and the device structure is located in the third dielectric layer; the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0034] Optionally, the substrate further has a fin structure.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] The formation method of the technical solution of the present invention forms an enhancement layer on the exposed surface of the barrier layer, thereby forming an electrical connection layer within the second opening using a selective deposition process. On the one hand, the enhancement layer can protect the barrier layer, preventing the gas forming the electrical connection layer from reacting with the barrier layer. On the other hand, the growth rate of the electrical connection layer on the enhancement layer is greater than that on the barrier layer, resulting in a smaller difference in the growth rate of the electrical connection layer formed on the enhancement layer and the conductive layer, resulting in a denser electrical connection layer structure.

[0037] Furthermore, before forming the enhancement layer on the exposed surface of the barrier layer, the method further includes: performing a reduction treatment on the surface of the barrier layer to form a reduction layer. The reduction layer comprises a metal nitride, and the atomic percentage concentration of the metal element in the reduction layer material is greater than the atomic percentage concentration of the metal element in the barrier layer material. This reduces the contact resistance between the enhancement layer and the barrier layer, thereby improving the performance of the semiconductor structure.

[0038] Furthermore, while the surface of the barrier layer is being reduced, the surface of the conductive layer is also reduced, thereby reducing the contact resistance between the electrical connection layer and the conductive layer and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1 to 3 is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment;

[0040] Figures 4 to 9 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in this embodiment. DETAILED DESCRIPTION

[0041] As described in the background art, the manufacturing process of a semiconductor structure with a local interconnect structure in the prior art is complex, and the performance of the formed semiconductor structure needs to be further improved.

[0042] Figures 1 to 3 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0043] Please refer to Figure 1 , providing a substrate 100; forming a first dielectric layer 101 and a conductive structure located in the first dielectric layer 101 on the substrate 100, wherein the conductive structure includes a barrier layer 103 and a conductive layer 102 located on the barrier layer 103; forming a stop layer 104 on the first dielectric layer 101 and the conductive structure; and forming a second dielectric layer 105 on the stop layer 104.

[0044] Please refer to Figure 2 , an opening 106 is formed in the second dielectric layer 105 , the projection of the conductive structure on the substrate is located within the range of the projection of the opening 106 on the substrate 100 , and the opening 106 exposes the top surface of the conductive layer 102 and part of the sidewall surface of the barrier layer 103 .

[0045] Please refer to Figure 3 , an electrical connection layer 107 is formed in the opening 106 .

[0046] During the formation of the semiconductor structure, the projected area of ​​the opening 106 on the substrate 100 is larger than the projected area of ​​the conductive structure on the substrate, and a portion of the sidewall surface of the barrier layer 103 is exposed. This is because a selective deposition process is used when subsequently forming the electrical connection layer 107. The electrical connection layer structure formed by the selective deposition process is relatively dense and suitable for growth in small-scale structures. However, the electrical connection layer 107 formed by the selective deposition process has strong directionality during the growth process, resulting in a gap between the electrical connection layer 107 and the second dielectric layer 105. During the subsequent chemical mechanical polishing, the polishing liquid will flow along the gap to the surface of the conductive structure, causing damage to the conductive structure. Therefore, the opening 106 is generally formed by over-etching, so that the projected area of ​​the opening 106 on the substrate 100 is larger than the projected area of ​​the conductive structure on the substrate, and a portion of the sidewall surface of the barrier layer 103 is exposed.

[0047] The opening 106 exposes a portion of the side wall surface of the barrier layer 103. The material of the barrier layer 103 includes titanium nitride, and the material of the electrical connection layer 107 includes tungsten. The gas used to form the electrical connection layer 107 is WF6. The WF6 gas will react with titanium nitride to form reactants remaining on the surface of the conductive layer 102. The reactants inhibit the growth of tungsten on the conductive layer 102, resulting in defects such as holes in the structure of the formed electrical connection layer 107, which increases the resistance of the electrical connection layer 107 and affects the performance of the electrical connection layer 107.

[0048] To address the aforementioned issues, the present invention provides a semiconductor structure and a method for forming the same. By forming a reinforcement layer on the exposed surface of the barrier layer, an electrical connection layer is formed within the second opening using a selective deposition process. The reinforcement layer protects the barrier layer, preventing the gas forming the electrical connection layer from reacting with the barrier layer. Furthermore, the electrical connection layer grows at a higher rate on the reinforcement layer than on the barrier layer, minimizing the difference in growth rate between the reinforcement layer and the conductive layer, resulting in a denser electrical connection layer structure.

[0049] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] Figures 4 to 9 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in this embodiment.

[0051] Please refer to Figure 4 , providing a substrate 200.

[0052] In this embodiment, the substrate 200 includes: a base (not shown); a device layer (not shown) located on the base, the device layer includes a third dielectric layer and a device structure located in the third dielectric layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0053] In this embodiment, the substrate is made of silicon.

[0054] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0055] In this embodiment, the substrate is a planar substrate.

[0056] In other embodiments, the substrate further has a fin structure.

[0057] Please refer to Figure 5 A first dielectric layer 201 is formed on a substrate 200 . The first dielectric layer 201 has a plurality of first openings (not shown) therein. The first openings expose a portion of the surface of the device structure in the substrate 200 .

[0058] The material of the first dielectric layer 201 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first dielectric layer 201 includes silicon oxide.

[0059] Please continue to refer to Figure 5 A conductive structure is formed in the first opening, the conductive structure including a barrier layer 202 located on the sidewall surface and the bottom surface of the first opening and a conductive layer 203 located on the surface of the barrier layer 202, and the conductive structure is electrically connected to the device structure.

[0060] The material of the barrier layer 202 includes metal nitride, the material of the conductive layer 203 includes metal or metal nitride, the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0061] In this embodiment, the material of the barrier layer 202 includes titanium nitride, and the material of the conductive layer 203 includes cobalt.

[0062] Please refer to Figure 6 , forming a stop layer 204 on the first dielectric layer 201 and the conductive structure.

[0063] The stop layer 204 is used as an etching stop layer for subsequently etching the second dielectric layer.

[0064] The stop layer 204 is made of a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride.

[0065] In this embodiment, the material of the stop layer 204 includes silicon nitride, silicon oxynitride, or silicon carbide.

[0066] In other embodiments, the stop layer may not be formed.

[0067] Please continue to refer to Figure 6 , a second dielectric layer 205 is formed on the stop layer 204 .

[0068] The material of the stop layer 204 is different from that of the second dielectric layer 205. Therefore, when etching the second dielectric layer 205, the etching process can stop on the stop layer 204, thereby adjusting the process accuracy of forming the opening.

[0069] The material of the second dielectric layer 205 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0070] In this embodiment, the material of the second dielectric layer 205 includes silicon oxide.

[0071] Please refer to Figure 7 A second opening 206 is formed in the second dielectric layer 205 and the stop layer 204 , and the second opening 206 exposes the top surface of the conductive layer 203 and a portion of the sidewall surface of the barrier layer 202 .

[0072] The method for forming the second opening 206 in the second dielectric layer 205 includes: forming a mask layer (not shown) on the second dielectric layer 205, wherein the mask layer exposes the surface of the second dielectric layer 205 on the conductive structure; and etching the second dielectric layer 205 and the stop layer 204 using the mask layer as a mask until a portion of the sidewall surface of the blocking layer 202 is exposed, thereby forming the second opening 206.

[0073] The process of etching the second dielectric layer 205 includes a dry etching process, and the gas used in the dry etching process includes carbon fluorine gas.

[0074] The process of etching the second dielectric layer 205 to form the second opening 206 also includes forming an oxide layer (not shown) on the surface of the conductive layer 203 .

[0075] The second opening 206 exposes the top surface of the conductive layer 203 and a portion of the sidewall surface of the barrier layer 202 , thereby ensuring that the electrical connection layer subsequently formed in the second opening 206 has a larger contact area with the conductive structure, thereby reducing the contact resistance.

[0076] The figure shows the situation in this embodiment where the projection of the conductive structure on the substrate 200 is located within the projection range of the second opening 206 on the substrate 200, and the second opening 206 completely exposes the conductive layer 203 and partially exposes the blocking layer 202 on the side wall of the conductive layer 203.

[0077] Please continue to refer to Figure 7 , the surface of the barrier layer 202 is reduced to form a reduction layer (not shown).

[0078] The process of performing reduction treatment on the surface of the barrier layer 202 includes a gas reduction process, and the gas used in the gas reduction process includes hydrogen.

[0079] The material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the barrier layer 202. This reduces the contact resistance between the subsequently formed enhancement layer and the barrier layer 202, thereby improving the performance of the semiconductor structure.

[0080] The material of the reduction layer includes titanium-rich titanium nitride or tantalum-rich tantalum nitride.

[0081] On the one hand, the hydrogen treatment can make the atomic percentage concentration of the metal element of the reduction layer material greater than the atomic percentage concentration of the metal element of the barrier layer material; on the other hand, the hydrogen treatment can remove the ions of the conductive layer 203 material on the surface of the barrier layer 202, thereby avoiding the situation where the ions of the conductive layer 203 material on the surface of the barrier layer 202 react with the gas forming the electrical connection layer when the electrical connection layer is subsequently formed, and the formed reactants affect the quality of the electrical connection layer.

[0082] The ratio of the thickness of the reduction layer to the thickness of the barrier layer 202 is greater than 2:3. If the thickness of the reduction layer is too thin, the uniformity of the coverage of the barrier layer 202 by the reduction layer is poor, which affects the growth rate of the enhancement layer subsequently formed on the reduction layer. If the thickness of the reduction layer is too thick, the hydrogen treatment time is prolonged. On the one hand, the prolonged hydrogen treatment time may affect the morphology of the second opening 206, and on the other hand, it may result in process waste.

[0083] In this embodiment, while reducing the surface of the barrier layer 202, the oxide layer on the surface of the conductive layer 203 is also reduced, thereby reducing the contact resistance between the subsequently formed electrical connection layer and the conductive layer 203 and improving the performance of the device.

[0084] Please refer to Figure 8 , forming a reinforcement layer 207 on the exposed surface of the barrier layer 202 .

[0085] The material of the enhancement layer 207 includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0086] In this embodiment, the material of the reinforcement layer 207 includes a rare metal, and the rare metal material includes cobalt. The rare metal material has strong surface activity and can increase the growth rate of the electrical connection layer grown on the surface of the reinforcement layer 207, thereby minimizing the difference in growth rate of the electrical connection layer on the surface of the conductive layer 203 and the surface of the reinforcement layer 207.

[0087] The process for forming the enhancement layer 207 includes a selective deposition process, which allows the enhancement layer 207 to be formed only on the surface of the barrier layer 202 and the surface of the conductive layer 203, thereby saving process flow and reducing the number of removal steps.

[0088] The ratio of the thickness of the reinforcement layer 207 to the thickness of the barrier layer 202 is greater than 2:3. If the reinforcement layer 207 is thicker, the process of forming the reinforcement layer 207 takes a longer time. As a result, the process of forming the reinforcement layer 207 will modify and consume the surface of the second dielectric layer 205 to a certain extent, causing the reinforcement layer 207 to grow on the surface of the second dielectric layer 205. The subsequent growth of the electrical connection layer on the second dielectric layer 205 will also affect the insulation properties of the second dielectric layer 205 and thus the performance of the semiconductor structure. If the reinforcement layer 207 is thinner, the subsequent growth rate of the electrical connection layer on the reinforcement layer 207 will not be significantly improved.

[0089] Please refer to Figure 9 After the enhancement layer 207 is formed, an electrical connection layer 208 is formed in the second opening 206 by a selective deposition process. The growth rate of the electrical connection layer 208 on the enhancement layer 207 is greater than the growth rate on the barrier layer 202 .

[0090] The material of the electrical connection layer 208 includes metal, and the metal includes tungsten.

[0091] The process parameters of the selective deposition process for forming the electrical connection layer 208 include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0092] On the one hand, the reinforcement layer 207 can protect the barrier layer 202 and prevent the tungsten hexafluoride gas forming the electrical connection layer 208 from reacting with the barrier layer 202; on the other hand, the material of the reinforcement layer 207 includes rare metals, and the growth rate of the electrical connection layer 208 on the reinforcement layer 207 is greater than the growth rate on the barrier layer 202, so that the growth rate difference between the formed electrical connection layer 208 on the reinforcement layer 207 and on the conductive layer 203 is small, and the formed electrical connection layer 209 has a denser structure.

[0093] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 9 ,include:

[0094] A substrate 200, comprising a base and a device structure located on the base;

[0095] A first dielectric layer 201 located on the substrate 200 , wherein the first dielectric layer 201 has a plurality of first openings therein, and the first openings expose a portion of the surface of the device structure;

[0096] A conductive structure located in the first opening, the conductive structure comprising a barrier layer 202 located on the sidewall surface and the bottom surface of the first opening and a conductive layer 203 located on the surface of the barrier layer 202, the conductive structure being electrically connected to the device structure;

[0097] a stop layer 204 located on the first dielectric layer 201 and the conductive structure;

[0098] a second dielectric layer 205 located on the stop layer 204;

[0099] a second opening located in the second dielectric layer 205 and the stop layer 204 , wherein the second opening exposes a surface of the top 203 of the conductive layer and a portion of a sidewall surface of the barrier layer 202 ;

[0100] a reinforcing layer 207 located on the exposed surface of the barrier layer 202;

[0101] The electrical connection layer 208 is located in the second opening, and the electrical connection layer 208 is located on the surface of the conductive layer 203 and the surface of the reinforcement layer 207 .

[0102] In this embodiment, the present invention further includes a reducing layer (not shown) located on the surface of the barrier layer 202 .

[0103] In this embodiment, the material of the barrier layer 202 includes metal nitride, and the metal nitride includes titanium nitride or tantalum nitride; the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the barrier layer material.

[0104] In this embodiment, the material of the reduction layer includes titanium-rich titanium nitride or tantalum-rich tantalum nitride.

[0105] In this embodiment, the ratio of the thickness of the reduction layer to the thickness of the barrier layer 202 is greater than 2:3.

[0106] In this embodiment, the material of the enhancement layer 207 includes rare metals, and the rare metals include one or more of cobalt, cesium, ruthenium, rubidium, and molybdenum.

[0107] In this embodiment, the ratio of the thickness of the reinforcement layer 207 to the thickness of the barrier layer 202 is greater than 2:3.

[0108] In this embodiment, the material of the electrical connection layer 208 includes metal, and the metal includes tungsten.

[0109] In this embodiment, the material of the stop layer 204 is different from the material of the second dielectric layer 205 .

[0110] In this embodiment, the material of the stop layer 204 includes silicon nitride.

[0111] In this embodiment, the substrate 200 further includes: a third dielectric layer located on the base, and the device structure is located in the third dielectric layer; the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0112] In other embodiments, the substrate further has a fin structure.

[0113] In the semiconductor structure, on the one hand, the enhancement layer 207 can protect the barrier layer 202 and prevent the gas forming the electrical connection layer 208 from reacting with the barrier layer 202; on the other hand, the material of the enhancement layer 207 includes rare metals, and the growth rate of the electrical connection layer 208 on the enhancement layer 207 is greater than the growth rate on the barrier layer 202, so that the growth rate difference between the formed electrical connection layer 208 on the enhancement layer 207 and the conductive layer 203 is small, and the structure of the formed electrical connection layer 208 is denser.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, comprising a base and a device structure located on the base; a first dielectric layer located on the substrate, wherein the first dielectric layer has a plurality of first openings therein, and the first openings expose a portion of the surface of the device structure; a conductive structure located in the first opening, the conductive structure comprising a barrier layer located on the sidewall surface and the bottom surface of the first opening and a conductive layer located on the surface of the barrier layer, the conductive structure being electrically connected to the device structure; a stop layer located on the first dielectric layer; a second dielectric layer located on the stop layer; a second opening located in the second dielectric layer and the stop layer, wherein the second opening exposes the top surface of the conductive layer and a portion of the sidewall surface of the barrier layer, the bottom surface of the second opening is lower than the top surface of the barrier layer, and the top surface of the conductive layer is lower than the top surface of the barrier layer; a reinforcement layer positioned on the exposed surface of the barrier layer; An electrical connection layer is located in the second opening, and the electrical connection layer is located on the surface of the conductive layer and the surface of the reinforcement layer.

2. The semiconductor structure according to claim 1, wherein Also includes: A reducing layer located on the surface of the barrier layer.

3. The semiconductor structure according to claim 2, wherein: The material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride or tantalum nitride; the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the barrier layer material.

4. The semiconductor structure according to claim 3, wherein: The material of the reduction layer includes titanium-rich titanium nitride or tantalum-rich tantalum nitride.

5. The semiconductor structure according to claim 2, wherein: The ratio of the thickness of the reducing layer to the thickness of the barrier layer is greater than 2:

3.

6. The semiconductor structure according to claim 1, wherein The material of the enhancement layer includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

7. The semiconductor structure according to claim 1, wherein: The ratio of the thickness of the reinforcement layer to the thickness of the barrier layer is greater than 2:

3.

8. The semiconductor structure according to claim 1, wherein: The material of the electrical connection layer includes metal, and the metal includes tungsten.

9. The semiconductor structure according to claim 1, wherein: The material of the stop layer is different from that of the second dielectric layer.

10. The semiconductor structure according to claim 9, wherein: The material of the stop layer includes silicon nitride.

11. The semiconductor structure according to claim 1, wherein: The substrate further comprises: a third dielectric layer located on the base, and the device structure is located in the third dielectric layer; the device structure comprises a diode, a triode, a capacitor or an inductor.

12. The semiconductor structure according to claim 11, wherein The substrate also has a fin structure.

13. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base and a device structure located on the base; forming a first dielectric layer on a substrate, wherein the first dielectric layer has a plurality of first openings therein, and the first openings expose a portion of the surface of the device structure; forming a conductive structure in the first opening, the conductive structure comprising a barrier layer located on a sidewall surface and a bottom surface of the first opening and a conductive layer located on a surface of the barrier layer, the conductive structure being electrically connected to the device structure; forming a stop layer on the first dielectric layer and the conductive structure; forming a second dielectric layer on the stop layer; forming a second opening in the second dielectric layer and the stop layer, wherein the second opening exposes the top surface of the conductive layer and a portion of the sidewall surface of the barrier layer, the bottom surface of the second opening is lower than the top surface of the barrier layer, and the top surface of the conductive layer is lower than the top surface of the barrier layer; forming a reinforcement layer on the exposed surface of the barrier layer; After the enhancement layer is formed, an electrical connection layer is formed in the second opening by using a selective deposition process. The growth rate of the electrical connection layer on the enhancement layer is greater than the growth rate on the barrier layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the reinforcement layer on the exposed surface of the barrier layer, the method further includes: performing a reduction treatment on the surface of the barrier layer to form a reduction layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The process of performing reduction treatment on the surface of the barrier layer includes a gas reduction process, and the gas in the gas reduction process includes hydrogen.

16. The method for forming a semiconductor structure according to claim 15, wherein: The ratio of the thickness of the reducing layer to the thickness of the barrier layer is greater than 2:

3.

17. The method for forming a semiconductor structure according to claim 14, wherein: The process of forming the second opening in the second dielectric layer also includes: forming an oxide layer on the surface of the conductive layer; and performing a reduction treatment on the surface of the barrier layer while also performing a reduction treatment on the oxide layer on the surface of the conductive layer.

18. The method for forming a semiconductor structure according to claim 14, wherein: The material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride or tantalum nitride; the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the barrier layer material.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the reduction layer includes titanium-rich titanium nitride or tantalum-rich tantalum nitride.

20. The method for forming a semiconductor structure according to claim 13, wherein: The conductive layer is made of metal, and the metal includes cobalt.

21. The method for forming a semiconductor structure according to claim 13, wherein: The material of the enhancement layer includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

22. The method for forming a semiconductor structure according to claim 21, wherein: The process of forming the enhancement layer includes a selective deposition process.

23. The method for forming a semiconductor structure according to claim 13, wherein: The ratio of the thickness of the reinforcement layer to the thickness of the barrier layer is greater than 2:

3.

24. The method for forming a semiconductor structure according to claim 13, wherein: The material of the electrical connection layer includes metal, and the metal includes tungsten.

25. The method for forming a semiconductor structure according to claim 24, wherein: The process parameters of the selective deposition process for forming the electrical connection layer include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

26. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming a second opening in the second dielectric layer includes: forming a mask layer on the second dielectric layer, wherein the mask layer exposes the surface of the second dielectric layer on the conductive structure; etching the second dielectric layer and the stop layer using the mask layer as a mask until a portion of the sidewall surface of the blocking layer is exposed to form the second opening.

27. The method for forming a semiconductor structure according to claim 26, wherein: The process of etching the second dielectric layer includes a dry etching process, and the gas used in the dry etching process includes a carbon fluorine gas.

28. The method for forming a semiconductor structure according to claim 13, wherein: The substrate further comprises: a third dielectric layer located on the base, and the device structure is located in the third dielectric layer; the device structure comprises a diode, a triode, a capacitor or an inductor.

29. The method for forming a semiconductor structure according to claim 28, wherein: The substrate also has a fin structure.

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