Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure include: a substrate comprising a first region and a second region, a first dielectric layer and a first conductive layer disposed on the substrate, the first conductive layer being located within the first dielectric layer on the first region; a stop layer disposed on the first dielectric layer and the first conductive layer; a second conductive layer disposed on the second region, the material of the second conductive layer being different from that of the first conductive layer, the second conductive layer being disposed on the stop layer; a second dielectric layer disposed on the first dielectric layer and the second conductive layer, the second dielectric layer having a first opening and a second opening disposed therein, the first opening exposing a portion of the top surface of the first conductive layer and a sidewall surface of the stop layer, the second opening exposing a portion of the top surface of the second conductive layer; a reinforcement layer disposed on the bottom surface of the second opening; and an electrical connection layer disposed within the first opening and the second opening. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Metal interconnects are essential structures in semiconductor devices, used to interconnect active areas, transistors, or metal lines on different layers, enabling signal transmission and control. Therefore, during semiconductor manufacturing, the formation of metal interconnects significantly impacts semiconductor device performance and manufacturing costs. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between individual semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Typically, during the back-end interconnection process of semiconductor device manufacturing, a first conductive layer (M1) needs to be electrically connected to the underlying active device structures (including source / drain regions and gate structure regions). Therefore, before forming the first conductive layer, a local interconnect structure (Local Interconnect) for the semiconductor device is typically pre-formed. This local interconnect structure includes a zeroth conductive layer (M0) electrically connected to the underlying source / drain regions, and a zeroth gate conductive layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of the semiconductor structure with the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region, the substrate having a first dielectric layer and a first conductive layer, the first conductive layer being located within the first dielectric layer on the first region; a stop layer located on the first dielectric layer and the first conductive layer; a second conductive layer located on the second region, the material of the second conductive layer being different from that of the first conductive layer, the second conductive layer being located on the stop layer; a second dielectric layer located on the first dielectric layer and the second conductive layer, the second dielectric layer having a first opening and a second opening therein, the first opening exposing a portion of the top surface of the first conductive layer and the sidewall surface of the stop layer, the second opening exposing a portion of the top surface of the second conductive layer; a reinforcement layer located on the bottom surface of the second opening; and an electrical connection layer located within the first opening and the second opening.

[0007] Optionally, the material of the enhancement layer includes rare metals, and the rare metals include one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0008] Optionally, the ratio of the thickness of the reinforcement layer to the thickness of the second conductive layer is in a range of 1:3 to 1:2.

[0009] Optionally, the material of the second conductive layer includes metal nitride, and the metal nitride includes a combination of one or more of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

[0010] Optionally, it also includes: a groove located in the first conductive layer, the first dielectric layer exposes the top of the groove, the first opening is connected to the groove, and the projection range of the first opening on the substrate is located within the projection range of the groove on the substrate; the electrical connection layer is also located in the groove.

[0011] Optionally, it also includes: a reduction layer located at the bottom of the groove, the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the second conductive layer material; the enhancement layer is located on the reduction layer.

[0012] Optionally, the material of the reduction layer includes titanium-rich material.

[0013] Optionally, the ratio of the thickness of the reduction layer to the thickness of the second conductive layer is in the range of 1:3 to 1:2.

[0014] Optionally, the material of the electrical connection layer includes metal, and the metal includes tungsten.

[0015] Optionally, the first dielectric layer further has a third opening, and the semiconductor structure further includes: a barrier layer located on the sidewall surface and the bottom surface of the third opening; and the first conductive layer is located on the barrier layer.

[0016] Optionally, the material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride; the material of the first conductive layer includes metal or metal nitride, and the material of the first conductive layer includes cobalt.

[0017] Optionally, the substrate includes: a base; a device layer located on the base, the device layer includes a third dielectric layer and a device structure located in the third dielectric layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0018] Optionally, the substrate further has a fin structure.

[0019] Optionally, the material of the stop layer includes silicon nitride.

[0020] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, the substrate having a first dielectric layer and a first conductive layer, the first conductive layer being located in the first dielectric layer on the first region; forming a stop layer on the first conductive layer and the first dielectric layer; forming a second conductive layer on the second region, the material of the second conductive layer being different from the material of the first conductive layer, the second conductive layer being located on the stop layer; forming a second dielectric layer on the first dielectric layer and the second conductive layer; etching the second dielectric layer to form a first opening and a second opening in the second dielectric layer, the first opening exposing a portion of the top surface of the first conductive layer and the sidewall surface of the stop layer, and the second opening exposing a portion of the top surface of the second conductive layer; forming an enhancement layer on the bottom surface of the second opening; after forming the enhancement layer, forming an electrical connection layer in the first opening and the second opening using a selective deposition process, the growth rate of the electrical connection layer on the enhancement layer being greater than the growth rate on the second conductive layer.

[0021] Optionally, the material of the enhancement layer includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0022] Optionally, the process of forming the enhancement layer includes a selective deposition process.

[0023] Optionally, the ratio of the thickness of the reinforcement layer to the thickness of the second conductive layer is in a range of 1:3 to 1:2.

[0024] Optionally, the material of the second conductive layer includes metal nitride, and the metal nitride includes a combination of one or more of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

[0025] Optionally, before forming the enhancement layer on the bottom surface of the second opening, the method further includes: performing surface treatment on the surface of the second conductive layer to form a reduction layer at the bottom of the second opening, wherein the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the second conductive layer material.

[0026] Optionally, the material of the reduction layer includes titanium-rich material.

[0027] Optionally, the process of performing surface treatment on the surface of the second conductive layer includes a gas treatment process, and the gas of the gas treatment process includes hydrogen.

[0028] Optionally, the ratio of the thickness of the reduction layer to the thickness of the second conductive layer is in the range of 1:3 to 1:2.

[0029] Optionally, the process of forming the first opening and the second opening in the second dielectric layer further includes: forming an oxide layer on the exposed surface of the first conductive layer.

[0030] Optionally, the process of forming the first opening and the second opening in the second dielectric layer further includes: removing a portion of the first conductive layer to form a groove in the first conductive layer, the first opening being connected to the groove, the projection range of the first opening on the substrate being within the projection range of the groove on the substrate; and the oxide layer being located on the bottom surface of the groove.

[0031] Optionally, the gas treatment process further performs a reduction treatment on the oxide layer at the bottom of the groove.

[0032] Optionally, the material of the electrical connection layer includes metal, and the metal includes tungsten.

[0033] Optionally, the process parameters of the selective deposition process include: a temperature range of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0034] Optionally, the first dielectric layer further has a third opening therein, and further comprises: a barrier layer located on the sidewall surface and the bottom surface of the third opening; and the first conductive layer is located on the barrier layer.

[0035] Optionally, the material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride; the material of the first conductive layer includes metal or metal nitride, and the material of the first conductive layer includes cobalt.

[0036] Optionally, the method for forming the first conductive layer and the barrier layer includes: forming a third opening in the first dielectric layer; forming a barrier layer on the sidewall surface and the bottom surface of the third opening; and forming the first conductive layer on the barrier layer.

[0037] Optionally, the substrate includes: a base; a device layer located on the base, the device layer including a third dielectric layer and a device structure located in the third dielectric layer, the device structure including a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; the first conductive layer is electrically connected to the device structure.

[0038] Optionally, the substrate further has a fin structure.

[0039] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0040] The method for forming a semiconductor structure according to the technical solution of the present invention forms a reinforcement layer on a second conductive layer, and then forms an electrical connection layer within a first opening and a second opening using a selective deposition process. The growth rate of the electrical connection layer on the reinforcement layer is greater than the growth rate on the second conductive layer. The material of the second conductive layer is different from that of the first conductive layer, and the growth rate of the electrical connection layer on the reinforcement layer is greater than the growth rate on the second conductive layer, thereby reducing the difference between the growth rate of the electrical connection layer on the reinforcement layer and the growth rate on the first conductive layer. As a result, when the electrical connection layer is formed within the first opening and the second opening, the electrical connection layer can grow synchronously within the first opening and the second opening. The process has good uniformity, resulting in a dense electrical connection layer structure with good resistance uniformity.

[0041] Furthermore, before forming the enhancement layer on the bottom surface of the second opening, the method further includes: performing surface treatment on the surface of the second conductive layer to form a reduction layer at the bottom of the second opening, wherein the material of the reduction layer includes a metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the second conductive layer material. The atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the second conductive layer material, thereby reducing the contact resistance between the enhancement layer and the second conductive layer, thereby reducing the difference between the resistance of the second conductive layer and the designed value, and making the performance of the semiconductor structure controllable.

[0042] Furthermore, the gas treatment process also performs a reduction treatment on the oxide layer on the surface of the first conductive layer at the bottom of the first opening, thereby reducing the contact resistance between the electrical connection layer and the first conductive layer and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 and Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0044] Figure 3 and Figure 4 is a schematic cross-sectional structural diagram of a semiconductor structure forming process according to another embodiment;

[0045] Figures 5 to 10 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] As described in the background art, the manufacturing process of a semiconductor structure with a local interconnect structure in the prior art is complex, and the performance of the formed semiconductor structure needs to be further improved.

[0047] Figure 1 and Figure 2 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0048] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II; forming a first dielectric layer 101 on the substrate 100; forming a first conductive layer 102 in the first dielectric layer 101 on the first region I; forming a barrier layer (not shown) on the first conductive layer 102 and the first dielectric layer 101; forming a second conductive layer 103 on the barrier layer in the second region II; forming a second dielectric layer 104 on the barrier layer and the second conductive layer 103; forming a first opening 106 and a second opening 105 in the second dielectric layer 104, the first opening 106 exposing a portion of the surface of the barrier layer on the first region I, and the second opening 105 exposing a portion of the surface of the second conductive layer 103 on the second region II.

[0049] Please refer to Figure 2 A first electrical connection layer 108 is formed in the first opening 106 , and a second electrical connection layer 107 is formed in the second opening 105 .

[0050] In the semiconductor structure, the first region I is the device region, and the second region II is the peripheral region. In order to adjust the electrical performance of the semiconductor structure in the device region, a high-resistance second conductive layer 103 is formed on the peripheral region, and then the second conductive layer 103 on the second region II is connected to the device on the first region I through a back-end connection process to achieve the purpose of adjusting the electrical performance of the semiconductor structure.

[0051] During the formation of the semiconductor structure, the first conductive layer 102 is made of cobalt, the second conductive layer 103 is made of titanium nitride, and the first electrical connection layer 108 and the second electrical connection layer 107 are formed simultaneously using a selective deposition process and are made of tungsten. The growth rate of the first electrical connection layer 108 on the first conductive layer 102 is greater than the growth rate of the second electrical connection layer 107 on the second conductive layer 103, so that under the same process conditions, the second electrical connection layer 107 fails to fill the second opening 105. Subsequently, a pad layer (not shown) and a buffer layer (not shown) are formed on the first electrical connection layer 108 and the second electrical connection layer 107 to planarize the first electrical connection layer 108 so that the material in the second opening 105 is a stacked structure of the second electrical connection layer 107, the pad layer and the buffer layer; at the same time, due to the uneven growth rate of the second electrical connection layer 107 on the second conductive layer 103, the surface of the second electrical connection layer 107 is an uneven surface, and the thickness of the pad layer and the buffer layer is also uneven, so that the resistance of the second conductive layer 103 is significantly different from the preset value, thereby affecting the electrical properties of the formed semiconductor device, making the performance of the semiconductor device uncontrollable and resulting in large differences.

[0052] In order to solve the problem of slow growth rate when growing the second electrical connection layer 107 in the second opening 105, another solution is proposed. Figure 3 and Figure 4 .

[0053] Figure 3 and Figure 4 FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment.

[0054] Please refer to Figure 3 , providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II; forming a first dielectric layer 101 on the substrate 100; forming a first conductive layer 102 in the first dielectric layer 101 in the first region I; forming a barrier layer (not shown) on the first conductive layer 102 and the first dielectric layer 101; forming a second conductive layer 103 on the barrier layer in the second region II; forming a second dielectric layer 104 on the barrier layer and the second conductive layer 103; forming a first electrical connection layer 206 in the second dielectric layer 104 in the first region I; after forming the first electrical connection layer 206, forming an opening 205 in the second dielectric layer 104 in the second region II, wherein the opening 205 exposes a portion of the surface of the second conductive layer 103 in the second region II.

[0055] Please refer to Figure 4 A barrier layer 207 is formed on the sidewall surfaces and the bottom surface of the opening 205 ; and a second electrical connection material layer 208 is formed on the barrier layer 207 .

[0056] During the formation of the semiconductor structure, the material of the second conductive layer 103 is titanium nitride, and the material of the barrier layer 207 is titanium nitride. When forming the opening 205, the etching process causes certain damage to the surface of the second conductive layer 103. The material of the second electrical connection material layer 208 includes tungsten and is formed by a deposition process. The gas used in the deposition process includes WF6 gas. During the deposition process, the WF6 gas consumes the material of titanium nitride. As a result, the thickness of the barrier layer 207 and the second conductive layer 103 in contact with the second electrical connection material layer 208 will be uneven, resulting in a poor bonding effect between the second electrical connection material layer 208, the barrier layer 207 and the second conductive layer 103 (e.g., Figure 4 As shown in the middle region A), the resistance of the second conductive layer 103 is greatly different from the preset value, thereby affecting the electrical performance of the formed semiconductor device, making the performance of the semiconductor device uncontrollable and resulting in large differences.

[0057] To address the above-mentioned problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure. A reinforcement layer is formed on a second conductive layer, and then an electrical connection layer is formed within a first opening and a second opening using a selective deposition process. The electrical connection layer has a greater growth rate on the reinforcement layer than on the second conductive layer. The material of the second conductive layer is different from that of the first conductive layer, and the electrical connection layer has a greater growth rate on the reinforcement layer than on the second conductive layer. This reduces the difference between the growth rate of the electrical connection layer on the reinforcement layer and the growth rate on the first conductive layer. Consequently, when the electrical connection layer is formed within the first opening and the second opening, the electrical connection layer can grow synchronously within the first opening and the second opening. The process has good uniformity, resulting in a dense electrical connection layer structure with good resistance uniformity.

[0058] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0059] Figures 5 to 10 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0060] Please refer to Figure 5 , providing a substrate 200, the substrate 200 includes a first region I and a second region II, the substrate 200 has a first dielectric layer 201 and a first conductive layer 202, the first conductive layer 202 is located in the first dielectric layer 201 on the first region I.

[0061] In this embodiment, the substrate 200 includes: a base (not shown); a device layer (not shown) located on the base, the device layer includes a third dielectric layer and a device structure located in the third dielectric layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0062] The first conductive layer 202 is electrically connected to the device structure.

[0063] In this embodiment, the substrate is made of silicon.

[0064] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0065] In this embodiment, the substrate is a planar substrate.

[0066] In other embodiments, the substrate further has a fin structure.

[0067] The first dielectric layer 201 further has a third opening (not shown). The semiconductor structure further includes a barrier layer (not shown) located on the sidewall surface and bottom surface of the third opening; the first conductive layer 202 is located on the barrier layer.

[0068] The method for forming the first conductive layer 202 includes: forming a third opening (not shown) in the first dielectric layer 201, wherein the third opening exposes a portion of the device structure surface in the substrate; forming a barrier layer on the sidewall surface and bottom surface of the third opening; and forming the first conductive layer 202 on the surface of the barrier layer.

[0069] The material of the barrier layer includes metal nitride, the material of the first conductive layer 202 includes metal or metal nitride, the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0070] In this embodiment, the material of the barrier layer includes titanium nitride, and the material of the first conductive layer 202 includes cobalt.

[0071] The material of the first dielectric layer 201 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first dielectric layer 201 includes silicon oxide.

[0072] Please refer to Figure 6 , a stop layer 300 is formed on the first conductive layer 202 and the first dielectric layer 201 .

[0073] The stop layer 300 is used as an etching stop layer for subsequently etching the second dielectric layer.

[0074] The stop layer 300 is made of a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride.

[0075] In this embodiment, the material of the stop layer 300 includes silicon nitride, silicon oxynitride, or silicon carbide.

[0076] In other embodiments, the stop layer may not be formed.

[0077] Please continue to refer to Figure 6 A second conductive layer 203 is formed on the second region II. The material of the second conductive layer 203 is different from that of the first conductive layer 202 . The second conductive layer 203 is located on the stop layer 300 .

[0078] The method for forming the second conductive layer 203 includes: forming a second conductive material layer (not shown) on the stop layer 300; removing the second conductive material layer on the first region I, and forming the second conductive layer 203 on the stop layer in the second region II.

[0079] The material of the second conductive layer 203 includes a metal nitride, which may include a combination of one or more of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide. The second conductive layer 203 formed of these materials has a high film resistivity and also facilitates the subsequent growth of an enhancement layer on the second conductive layer 203, making it suitable for adjusting the performance of the semiconductor device formed in the first region I.

[0080] In this embodiment, the material of the second conductive layer 203 includes titanium nitride. The titanium nitride material has a simple formation process and can be formed by a physical vapor deposition process, with a high film forming rate and low cost, which is conducive to saving production costs.

[0081] Please refer to Figure 7 , a second dielectric layer 204 is formed on the stop layer and the second conductive layer 203 .

[0082] The material of the second dielectric layer 204 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride.

[0083] In this embodiment, the material of the second dielectric layer 204 includes silicon oxide.

[0084] Please continue to refer to Figure 7 , the second dielectric layer 204 and the stop layer 300 are etched to form a first opening 205 and a second opening 206 in the second dielectric layer 204, wherein the first opening 205 exposes a portion of the top surface of the first conductive layer 202 and the sidewall surface of the stop layer 300, and the second opening 206 exposes a portion of the top surface of the second conductive layer 203.

[0085] The method for forming the first opening 205 and the second opening 206 in the second dielectric layer 204 includes: forming a patterned layer (not shown) on the second dielectric layer 204; etching the second dielectric layer 202 and the stop layer 300 using the patterned layer as a mask until the top surface of the first conductive layer 202 and the top surface of the second conductive layer 203 are exposed, thereby forming the first opening 205 and the second opening 206.

[0086] The process of etching the second dielectric layer 204 includes a dry etching process, and the etching gas of the dry etching process includes a fluorine-containing gas.

[0087] In this embodiment, during the process of forming the first opening 205 and the second opening 206 in the second dielectric layer 204, a portion of the first conductive layer 202 is also removed to form a groove 301 in the first conductive layer 202. The first opening 205 is connected to the groove 301, and the projection range of the first opening 205 on the substrate is located within the projection range of the groove 301 on the substrate.

[0088] Therefore, when an electrical connection layer is subsequently formed in the first opening 205 and the groove 301, the electrical connection layer located in the groove 301 can protect the first conductive layer 202, and prevent the etching solution for flattening the electrical connection layer from flowing into the first conductive layer 202 along the gap between the electrical connection layer and the second dielectric layer 204, causing damage to the first conductive layer 202.

[0089] In other embodiments, the groove may not be formed.

[0090] The process of forming the first opening 205 and the second opening 206 in the second dielectric layer 204 further includes forming an oxide layer 207 on the exposed surface of the first conductive layer 202 .

[0091] The oxide layer 207 is a material obtained by oxidizing the first conductive layer 202 .

[0092] Please refer to Figure 8, the surface of the second conductive layer 203 is surface treated to form a reduction layer 208 at the bottom of the second opening 206, the material of the reduction layer 208 includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer 208 material is greater than the atomic percentage concentration of the metal element of the second conductive layer 203 material.

[0093] In this embodiment, the material of the second conductive layer 203 includes titanium nitride, and the material of the reduction layer 208 includes a titanium-rich material.

[0094] The process of performing surface treatment on the surface of the second conductive layer 203 includes a gas treatment process, and the gas used in the gas treatment process includes hydrogen.

[0095] The hydrogen treatment can generate a replacement reaction with the second conductive layer 203, so that the atomic percentage concentration of the metal element in the material of the formed reduction layer 208 is greater than the atomic percentage concentration of the metal element in the material of the second conductive layer 203. This reduces the contact resistance between the subsequently formed enhancement layer and the second conductive layer 203, thereby minimizing the difference between the resistance of the second conductive layer 203 and the designed value, and making the performance of the semiconductor structure controllable.

[0096] The ratio of the thickness of the reduction layer 208 to the thickness of the second conductive layer 203 is in the range of 1:3 to 1:2. If the thickness of the reduction layer 208 is too small, that is, the ratio is less than 1:3, the coverage of the second conductive layer 203 by the reduction layer 208 is small, and the rate of subsequent growth of the enhancement layer on the reduction layer 208 is slow. If the thickness of the reduction layer 208 is too large, that is, the ratio is greater than 1:2, the hydrogen treatment time is prolonged, which, on the one hand, may affect the morphology of the second opening 206, and on the other hand, may result in process waste.

[0097] The gas treatment process also reduces the oxide layer 207 on the surface of the first conductive layer 202 at the bottom of the groove 301. The oxide layer 207 on the surface of the first conductive layer 202 is reduced to the material of the first conductive layer 202, thereby reducing the contact resistance between the subsequently formed electrical connection layer and the first conductive layer 202, thereby improving device performance.

[0098] Please refer to Figure 9 A reinforcement layer 209 is formed on the bottom surface of the second opening 206 .

[0099] The reinforcement layer 209 is used to facilitate the subsequent formation of an electrical connection layer and to increase the growth rate of the electrical connection layer on the reinforcement layer 209 .

[0100] The material of the enhancement layer 209 includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0101] In this embodiment, the material of the reinforcement layer 209 includes a rare metal, and the rare metal includes cobalt. The rare metal material has a strong surface activity and can increase the growth rate of the electrical connection layer grown on the surface of the reinforcement layer 209, so that the difference in growth rate of the electrical connection layer on the surface of the first conductive layer and the surface of the reinforcement layer 209 is small.

[0102] The process of forming the enhancement layer 209 includes a selective deposition process.

[0103] The ratio of the thickness of the reinforcement layer 209 to the thickness of the second conductive layer 203 is in the range of 1:3 to 1:2. If the thickness of the reinforcement layer 209 is too small, that is, the ratio is less than 1:3, the coverage of the reinforcement layer 209 is small, and the subsequent rate of increasing the growth rate of the electrical connection layer on the reinforcement layer 209 is not significantly effective. If the thickness of the reinforcement layer 209 is too thick, that is, the ratio is greater than 1:2, the process time for forming the reinforcement layer 209 is long, and the process of forming the reinforcement layer 209 will modify and consume the surface of the second dielectric layer 204 to a certain extent, causing the reinforcement layer 209 to grow on the surface of the second dielectric layer 204. The subsequent growth of the electrical connection layer on the second dielectric layer 204 will also affect the insulation properties of the second dielectric layer 204, thereby affecting the performance of the semiconductor structure.

[0104] In this embodiment, the material of the reinforcement layer 209 is the same as that of the first conductive layer 202. The reinforcement layer 209 is also formed on the surface of the first conductive layer 202 (not shown). The reinforcement layer 209 has little effect on the size of the groove. The projection range of the first opening 205 on the substrate is within the projection range of the groove 301 on the substrate.

[0105] Please refer to Figure 10 After forming the enhancement layer 209 , an electrical connection layer 210 is formed in the first opening 205 , in the groove 301 and in the second opening 206 by a selective deposition process. The growth rate of the electrical connection layer 210 on the enhancement layer 209 is greater than the growth rate on the second conductive layer 203 .

[0106] The material of the second conductive layer 203 is different from that of the first conductive layer 202. The growth rate of the electrical connection layer 210 on the reinforcement layer 209 is greater than the growth rate on the second conductive layer 203, so that the difference between the growth rate of the electrical connection layer 210 on the reinforcement layer 209 and the growth rate on the first conductive layer 202 is reduced. Therefore, when the electrical connection layer 210 is formed in the first opening 205 and the second opening 206, the electrical connection layer 210 can grow synchronously in the first opening 205 and the second opening 206. The process has good uniformity, so that the formed electrical connection layer 210 has a dense structure and good resistance uniformity.

[0107] The material of the electrical connection layer 210 includes metal, and the metal includes tungsten.

[0108] The process parameters of the selective deposition process include: a temperature range of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0109] The gas used in the selective deposition process contains tungsten hexafluoride. The enhancement layer 209 can protect the second conductive layer 203 from being consumed by the tungsten hexafluoride gas.

[0110] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 10 ,include:

[0111] A substrate 200, comprising a first region I and a second region II. The substrate 200 has a first dielectric layer 201 and a first conductive layer, wherein the first conductive layer 202 is located within the first dielectric layer 201 on the first region I.

[0112] a stop layer 300 located on the first dielectric layer 201 and the first conductive layer 202;

[0113] a second conductive layer 203 located on the second region II, wherein the material of the second conductive layer 203 is different from that of the first conductive layer, and the second conductive layer 203 is located on the stop layer 300;

[0114] a second dielectric layer 204 located on the first dielectric layer 201 and the second conductive layer 203, wherein the second dielectric layer 204 has a first opening and a second opening, wherein the first opening exposes a portion of the top surface of the first conductive layer 202 and the sidewall surface of the stop layer 300, and the second opening exposes a portion of the top surface of the second conductive layer 203;

[0115] a reinforcement layer 209 located on the bottom surface of the second opening;

[0116] The electrical connection layer 210 is located in the first opening and the second opening.

[0117] In this embodiment, the material of the enhancement layer 209 includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

[0118] In this embodiment, the ratio of the thickness of the reinforcement layer 209 to the thickness of the second conductive layer 203 is in a range of 1:3 to 1:2.

[0119] In this embodiment, the material of the second conductive layer 203 includes metal nitride, and the metal nitride includes one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

[0120] In this embodiment, the present invention further includes: a groove located in the first conductive layer 202, the first dielectric layer 201 exposing the top of the groove, the first opening 205 communicating with the groove, and the projection range of the first opening 205 on the substrate being located within the projection range of the groove on the substrate; the electrical connection layer 210 is also located in the groove.

[0121] In this embodiment, it also includes: a reduction layer 208 located at the bottom of the second opening, the material of the reduction layer 208 includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the second conductive layer material; the enhancement layer 209 is located on the reduction layer 208.

[0122] In this embodiment, the material of the reduction layer 208 includes titanium-rich material.

[0123] In this embodiment, the ratio of the thickness of the reduction layer 208 to the thickness of the second conductive layer 203 is in a range of 1:3 to 1:2.

[0124] In this embodiment, the material of the electrical connection layer 210 includes metal, and the metal includes tungsten.

[0125] In this embodiment, the first dielectric layer 201 further has a third opening, and the semiconductor structure further includes: a barrier layer located on the sidewall surface and the bottom surface of the third opening; and the first conductive layer 202 is located on the barrier layer.

[0126] In this embodiment, the material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride; the material of the first conductive layer 202 includes metal or metal nitride, and the material of the first conductive layer 202 includes cobalt.

[0127] In this embodiment, the substrate 200 includes: a base; a device layer located on the base, the device layer including a third dielectric layer and a device structure located in the third dielectric layer, the device structure including a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0128] In other embodiments, the substrate further has a fin structure.

[0129] In this embodiment, the material of the stop layer 300 includes silicon nitride.

[0130] In the semiconductor structure, the material of the second conductive layer 203 is different from the material of the first conductive layer 202, and the growth rate of the electrical connection layer 210 on the enhancement layer 209 is greater than the growth rate on the second conductive layer 203, so that the difference between the growth rate of the electrical connection layer 210 on the enhancement layer 209 and the growth rate on the first conductive layer 202 is reduced, so that when the electrical connection layer 210 is formed in the first opening 205 and the second opening 206, the electrical connection layer 210 can grow synchronously in the first opening 205 and the second opening 206, and the process has good uniformity, so that the formed electrical connection layer 210 has a dense structure and good resistance uniformity.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a first region and a second region, wherein a first dielectric layer and a first conductive layer are formed on the substrate, and the first conductive layer is located within the first dielectric layer on the first region; a stop layer located on the first dielectric layer and the first conductive layer; a second conductive layer located on the second region, wherein the material of the second conductive layer is different from that of the first conductive layer, and the second conductive layer is located on the stop layer; a second dielectric layer located on the first dielectric layer and the second conductive layer, wherein the second dielectric layer has a first opening and a second opening, wherein the first opening exposes a portion of the top surface of the first conductive layer and the sidewall surface of the stop layer, and the second opening exposes a portion of the top surface of the second conductive layer; a reinforcement layer located on the bottom surface of the second opening; The electrical connection layer located in the first opening and the second opening has a growth rate on the reinforcement layer greater than that on the second conductive layer, so as to reduce the difference between the growth rate of the electrical connection layer on the reinforcement layer and the growth rate on the first conductive layer.

2. The semiconductor structure according to claim 1, wherein The material of the enhancement layer includes rare metals, and the rare metals include one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

3. The semiconductor structure according to claim 1, wherein: The ratio of the thickness of the reinforcement layer to the thickness of the second conductive layer is in the range of 1:3 to 1:

2.

4. The semiconductor structure according to claim 1, wherein: The material of the second conductive layer includes metal nitride, and the metal nitride includes one or more of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

5. The semiconductor structure according to claim 4, wherein: Also includes: A groove is located in the first conductive layer, the first dielectric layer exposes the top of the groove, the first opening is connected to the groove, and the projection range of the first opening on the substrate is located within the projection range of the groove on the substrate; the electrical connection layer is also located in the groove.

6. The semiconductor structure according to claim 5, wherein: Also includes: a reduction layer located at the bottom of the groove, wherein the material of the reduction layer includes a metal nitride, and the atomic percentage concentration of the metal element of the material of the reduction layer is greater than the atomic percentage concentration of the metal element of the material of the second conductive layer; The enhancement layer is located on the reduction layer.

7. The semiconductor structure according to claim 6, wherein: The material of the reduction layer includes titanium-rich material.

8. The semiconductor structure according to claim 6, wherein: The ratio of the thickness of the reduction layer to the thickness of the second conductive layer is in the range of 1:3 to 1:

2.

9. The semiconductor structure according to claim 1, wherein: The material of the electrical connection layer includes metal, and the metal includes tungsten.

10. The semiconductor structure according to claim 1, wherein: The first dielectric layer further has a third opening therein, and the semiconductor structure further includes: a barrier layer located on the sidewall surface and the bottom surface of the third opening; and the first conductive layer is located on the barrier layer.

11. The semiconductor structure according to claim 10, wherein: The material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride; the material of the first conductive layer includes metal or metal nitride, and the material of the first conductive layer includes cobalt.

12. The semiconductor structure according to claim 1, wherein The substrate includes: a base; a device layer located on the base, the device layer includes a third dielectric layer and a device structure located in the third dielectric layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

13. The semiconductor structure according to claim 12, wherein: The substrate also has a fin structure.

14. The semiconductor structure according to claim 1, wherein: The material of the stop layer includes silicon nitride.

15. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the substrate having a first dielectric layer and a first conductive layer, wherein the first conductive layer is located in the first dielectric layer on the first region; forming a stop layer on the first conductive layer and the first dielectric layer; forming a second conductive layer on the second region, wherein the material of the second conductive layer is different from that of the first conductive layer, and the second conductive layer is located on the stop layer; forming a second dielectric layer on the first dielectric layer and the second conductive layer; Etching the second dielectric layer to form a first opening and a second opening in the second dielectric layer, wherein the first opening exposes a portion of the top surface of the first conductive layer and the sidewall surface of the stop layer, and the second opening exposes a portion of the top surface of the second conductive layer; forming a reinforcement layer on the bottom surface of the second opening; After forming the enhancement layer, an electrical connection layer is formed in the first opening and the second opening using a selective deposition process. The growth rate of the electrical connection layer on the enhancement layer is greater than the growth rate on the second conductive layer, so as to reduce the difference between the growth rate of the electrical connection layer on the enhancement layer and the growth rate on the first conductive layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the enhancement layer includes metal, and the metal includes one or more of cobalt, cesium, ruthenium, rubidium and molybdenum.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process of forming the enhancement layer includes a selective deposition process.

18. The method for forming a semiconductor structure according to claim 15, wherein: The ratio of the thickness of the reinforcement layer to the thickness of the second conductive layer is in the range of 1:3 to 1:

2.

19. The method for forming a semiconductor structure according to claim 15, wherein: The material of the second conductive layer includes metal nitride, and the metal nitride includes one or more of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

20. The method for forming a semiconductor structure according to claim 19, wherein: Before forming the enhancement layer on the bottom surface of the second opening, it also includes: surface treatment of the surface of the second conductive layer to form a reduction layer at the bottom of the second opening, the material of the reduction layer includes metal nitride, and the atomic percentage concentration of the metal element of the reduction layer material is greater than the atomic percentage concentration of the metal element of the second conductive layer material.

21. The method for forming a semiconductor structure according to claim 20, wherein: The material of the reduction layer includes titanium-rich material.

22. The method for forming a semiconductor structure according to claim 20, wherein: The process of performing surface treatment on the surface of the second conductive layer includes a gas treatment process, and the gas of the gas treatment process includes hydrogen.

23. The method for forming a semiconductor structure according to claim 20, wherein: The ratio of the thickness of the reduction layer to the thickness of the second conductive layer is in the range of 1:3 to 1:

2.

24. The method for forming a semiconductor structure according to claim 22, wherein: The process of forming the first opening and the second opening in the second dielectric layer further includes: forming an oxide layer on the exposed surface of the first conductive layer.

25. The method for forming a semiconductor structure according to claim 24, wherein: The process of forming the first opening and the second opening in the second dielectric layer also includes: removing a portion of the first conductive layer to form a groove in the first conductive layer, the first opening being connected to the groove, the projection range of the first opening on the substrate being within the projection range of the groove on the substrate; and the oxide layer being located on the bottom surface of the groove.

26. The method for forming a semiconductor structure according to claim 25, wherein: The gas treatment process also reduces the oxide layer at the bottom of the groove.

27. The method for forming a semiconductor structure according to claim 15, wherein: The material of the electrical connection layer includes metal, and the metal includes tungsten.

28. The method for forming a semiconductor structure according to claim 27, wherein: The process parameters of the selective deposition process include: a temperature range of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

29. The method for forming a semiconductor structure according to claim 15, wherein: The first dielectric layer also has a third opening therein and further comprises: a barrier layer located on the sidewall surface and the bottom surface of the third opening; and the first conductive layer is located on the barrier layer.

30. The method for forming a semiconductor structure according to claim 29, wherein: The material of the barrier layer includes metal nitride, and the metal nitride includes titanium nitride; the material of the first conductive layer includes metal or metal nitride, and the material of the first conductive layer includes cobalt.

31. The method for forming a semiconductor structure according to claim 29, wherein: The method for forming the first conductive layer and the barrier layer includes: forming a third opening in the first dielectric layer; forming a barrier layer on the sidewall surface and the bottom surface of the third opening; and forming the first conductive layer on the barrier layer.

32. The method for forming a semiconductor structure according to claim 15, wherein: The substrate includes: a base; a device layer located on the base, the device layer including a third dielectric layer and a device structure located in the third dielectric layer, the device structure including a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; the first conductive layer is electrically connected to the device structure.

33. The method for forming a semiconductor structure according to claim 32, wherein: The substrate also has a fin structure.

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