A semiconductor device and a manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The method comprises: providing a semiconductor structure, the semiconductor structure comprising a substrate and a plurality of transistor pillars arranged in an array on the substrate; etching a top end of each of the transistor pillars to form a first recess; sequentially forming a metal silicide layer and a first metal layer in the first recess; the metal silicide layer covering a bottom and a sidewall of the first recess; and the first metal layer filling the first recess.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Generally, a dynamic random access memory (DRAM) is composed of a plurality of memory cells, each of which is composed of a memory capacitor controlled by a transistor, that is, the DRAM is a 1-transistor 1-memory capacitor (1T1C) memory cell. In each memory cell, the transistor includes a gate, a source and a drain, the gate of the transistor forms a word line, and the drain of the transistor is connected to a bit line; and the first electrode layer of the memory capacitor is connected to the source of the transistor, and the second electrode layer of the memory capacitor is connected to a common terminal. Among them, the memory capacitor is used to store data written into the memory cell. SUMMARY

[0003] Therefore, the embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof to solve at least one technical problem in the prior art.

[0004] To achieve the above-mentioned purpose, the technical solution of the present disclosure is as follows:

[0005] In a first aspect, the embodiment of the present disclosure provides a manufacturing method of a semiconductor device, the method comprising:

[0006] providing a semiconductor structure, the semiconductor structure comprising a substrate and a plurality of transistor columns arranged in an array on the substrate;

[0007] etching a top end of each of the transistor columns to form a first recess;

[0008] forming a metal silicide layer and a first metal layer in the first recess in sequence; the metal silicide layer covers the bottom and the sidewall of the first recess; and the first metal layer fills the first recess.

[0009] In some embodiments, the extension direction of the transistor column is perpendicular to the substrate.

[0010] In some embodiments, the metal silicide layer and the first metal layer at the top end of each of the transistor columns are used to realize electrical connection between the source and the memory capacitor.

[0011] In some embodiments, a gate oxide layer, a gate layer and an insulating structure are sequentially arranged on a first sidewall of the transistor column, and an isolation structure is arranged on a second sidewall of the transistor column; wherein the first sidewall of the transistor column and the second sidewall of the transistor column are opposite two sidewalls of the transistor column.

[0012] In some embodiments, the etching the top end of each of the transistor pillars to form a first recess includes:

[0013] The top end of each of the transistor pillars is etched to form a first recess, a first sidewall of the first recess exposes the insulating structure, and a second sidewall of the first recess exposes the isolation structure; wherein the first sidewall of the first recess and the second sidewall of the first recess are opposite two sidewalls of the first recess.

[0014] In some embodiments, after the etching the top end of each of the transistor pillars to form a first recess, the method further includes:

[0015] Forming a silicon liner on the bottom and sidewall of the first recess to form a second recess.

[0016] In some embodiments, the forming the metal silicide layer includes:

[0017] forming a second metal layer covering the bottom and sidewall of the second recess;

[0018] performing annealing treatment on the second metal layer, so that the bottom and sidewall of the first recess form the metal silicide layer.

[0019] In some embodiments, the performing annealing treatment on the second metal layer, so that the bottom and sidewall of the first recess form the metal silicide layer includes:

[0020] performing first annealing treatment on the second metal layer, so that atoms of the second metal layer and atoms of the silicon liner react to form a pre-metal silicide layer on the bottom and sidewall of the first recess;

[0021] performing second annealing treatment on the pre-metal silicide layer, so that the pre-metal silicide layer forms the metal silicide layer; wherein the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment.

[0022] In some embodiments, after the performing first annealing treatment on the second metal layer, the method further includes:

[0023] using a wet etching process to remove the second metal layer that is not reacted in the first annealing treatment.

[0024] In some embodiments, before the sequentially forming a metal silicide layer and a first metal layer in the first recess, the method further includes:

[0025] Ion implantation is performed on the top end of each of the transistor columns to form a source at the top end of each of the transistor columns; wherein the depth of the source is greater than the depth of the first groove in the direction perpendicular to the substrate.

[0026] In some embodiments, after the metal silicide layer and the first metal layer are sequentially formed in the first groove, the method further comprises:

[0027] A storage capacitor is formed on each of the transistor columns, a first electrode layer of the storage capacitor being electrically connected to the source through the metal silicide and the first metal layer at the top end of the transistor column, and a second electrode layer of the storage capacitor being connected to a common terminal.

[0028] In some embodiments, the semiconductor device comprises a vertical channel type memory.

[0029] In a second aspect, the embodiments of the present disclosure provide a semiconductor device, which comprises:

[0030] a transistor array with transistor columns;

[0031] The two ends of the extension direction of each of the transistor columns of the transistor array are respectively provided with a source and a drain; wherein a groove-shaped metal silicide layer and a first metal layer are formed on the top end of the source, and the first metal layer fills the groove formed by the metal silicide layer; the metal silicide layer and the first metal layer are used to realize electrical connection between the source and a storage capacitor.

[0032] In some embodiments, each of the transistor columns of the transistor array is arranged in an array along a first direction and a second direction, and the extension direction of the transistor column is perpendicular to the plane formed by the first direction and the second direction.

[0033] In some embodiments, the contact area between the metal silicide layer and the source is greater than the normal projection area of the source on the plane formed by the first direction and the second direction.

[0034] In some embodiments, a gate oxide layer, a gate layer and an insulating structure are sequentially arranged on the first sidewall of the transistor column, and an isolation structure is arranged on the second sidewall of the transistor column; wherein the first sidewall of the transistor column and the second sidewall of the transistor column are opposite two sidewalls of the transistor column.

[0035] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a plurality of transistor columns arranged in an array on the substrate; etching a top end of each transistor column to form a first groove; sequentially forming a metal silicide layer and a first metal layer in the first groove; the metal silicide layer covers the bottom and the sidewall of the first groove; and the first metal layer fills the first groove. In the embodiment of the present disclosure, the first groove is formed by etching the top end of the transistor column first, and then the metal silicide layer is formed on the bottom and the sidewall of the first groove. The contact area between the metal silicide layer and the transistor column is increased, the small size effect of forming the metal silicide layer is reduced, sufficient silicon source is provided for the reaction of forming the metal silicide layer, the metal silicide layer with stable crystal phase is ensured to be formed, and the thermal stability of the metal silicide layer is improved. Further, the stable metal silicide layer is used to realize stable electrical connection between the source of the transistor and the storage capacitor, so that the reliability of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figures 1A-1D A schematic diagram of a three-dimensional structure of a vertical channel type memory;

[0037] Figure 2 A partial sectional view of a vertical channel type memory;

[0038] Figure 3A A diagram of phase state of metal silicide changing with annealing temperature;

[0039] Figure 3B A diagram of T1 and T2 changing with thickness or line width of metal silicide;

[0040] Figure 4 A flow chart of a manufacturing method of a semiconductor device provided by the embodiment of the present disclosure;

[0041] Figures 5A-5F A schematic diagram of a three-dimensional structure in a manufacturing process of a semiconductor device provided by the embodiment of the present disclosure;

[0042] Figures 6A-6I A partial sectional view in a manufacturing process of a semiconductor device provided by the embodiment of the present disclosure;

[0043] Figure 7 A partial sectional view of a semiconductor device provided by the embodiment of the present disclosure;

[0044] The figure includes: 101, 501, substrate; 102, channel; 103, 505, 704, gate oxide layer; 104, 506, 705, gate layer; 105, insulation structure, 106, storage capacitor; 107, common end; 108, word line; 109, 519, 710, isolation structure; 110, 516, first electrode layer; 111, air gap; 112, 508, 706, source; 113, 512, 708, metal silicide layer; 114, tungsten layer; 502, 701, transistor column; 503, 702, first insulation structure; 504, 703, second insulation structure; 507, first recess; 509, silicon liner; 510, second recess; 511, second metal layer; 513, 709, first metal layer; 514, hard mask layer; 515, support layer; 517, capacitor dielectric layer, 518, second electrode layer; 707, drain. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the embodiments of the present disclosure and the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0046] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0047] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0048] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0049] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be proposed in the following description in order to explain the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementations.

[0052] The transistor array of the mainstream memory includes a planar transistor array and a buried channel transistor array (BCAT), however, no matter the planar transistor array or the buried channel transistor array, the source and the drain are located on the horizontal two sides of the gate in the structure. Under this structure, the source and the drain occupy different positions respectively, so that the area of the planar transistor array or the buried channel transistor array is larger.

[0053] In order to further reduce the size of the transistor array, the transistor array of the memory can include a vertical gate transistor array (VGT). In this structure, the channel of the transistor array is formed on the surface of the substrate; wherein the extension direction of the channel is perpendicular to the surface of the substrate; the channels are arrayed along a first direction parallel to the surface of the substrate and a second direction parallel to the surface of the substrate; a gate oxide layer and a gate can also be sequentially formed on at least one side of each channel of the transistor array, and the two ends of the extension direction of each channel of the transistor array have a source and a drain respectively. Specifically, the source can be formed by doping the first end of each channel of the transistor array; the substrate can also be thinned from the back to expose the second end of each channel of the transistor array, and the second end of each exposed channel can be doped to form the drain of each transistor; wherein the first end and the second end are two opposite ends of the channel along the extension direction.

[0054] Hereinafter, the thickness direction of the substrate is defined as the Z direction, the X direction and the Y direction intersecting with each other are defined in the top surface or the bottom surface of the substrate perpendicular to the Z direction, and the top surface or the bottom surface of the substrate perpendicular to the Z direction can be determined based on the X direction and the Y direction. For example, the X direction and the Y direction are perpendicular to each other, so the X direction, the Y direction and the Z direction are perpendicular to each other in pairs. In the embodiments of the present disclosure, the transistors and the channels are arrayed, the X direction is defined as the column direction, and the Y direction is defined as the row direction. It should be noted that the row direction in the arrayed arrangement can be perpendicular to the column direction, or can have a certain included angle.

[0055] Reference Figures 1A-1D , Figures 1A-1D is a schematic diagram of the three-dimensional structure of the vertical channel type memory. As shown in FIG. 1, the vertical channel type memory includes a substrate 1, a transistor array 2 and a control circuit 3. The transistor array 2 is formed on the substrate 1, and the control circuit 3 is formed on the substrate 1 and controls the transistor array 2. Figures 1A-1CAs shown, a plurality of channels 102 arranged in an array are formed on the substrate 101. A gate oxide layer 103, a gate layer 104, and an insulating structure 105 are sequentially formed on one sidewall of each channel 102. An isolation structure 109 is formed on the other sidewall of each channel 102 opposite to the first sidewall. The gate layers of channels 102 located in the same column (i.e., channels 102 arranged along the X direction) are connected to form word lines 108 (e.g., ...). Figure 1C As shown); the top of each channel 102 forms a source electrode (as shown); Figures 1A-1C (Not shown in the image), the source is connected to the first electrode layer of the storage capacitor 106, and the second electrode layer of the storage capacitor 106 is connected to the common terminal 107; the bottom of each channel 102 of the transistor array forms the drain ( Figures 1A-1C (Not shown in the image), the drains of each channel 102 located in the same row (i.e., each channel 102 arranged along the Y direction) are connected to form a bit line ( Figure 1A (Not shown in the image). Figure 1B and Figure 1C It is also shown that an insulating structure 105 is formed between two adjacent gate layers 104.

[0056] like Figure 1C As shown, a plurality of channels 102 arranged in an array are formed on the substrate 101, and the top of the channel 102 can be doped to form a source. Figure 1D The top of the channel, as shown in the diagram, is projected onto the substrate (i.e., the XY plane) as a rectangle with dimensions L1 in the X direction and L2 in the Y direction. In other words, the contact area between the transistor's source and the first electrode layer of the storage capacitor is L1*L2. Figure 2 The diagram illustrates the three-dimensional structure of a single storage unit.

[0057] In the aforementioned vertical channel memory, the channel extends in a direction perpendicular to the substrate, and the source and drain are formed at the upper and lower ends of the channel, respectively. The storage capacitor and bit line are located on the upper and lower sides of the channel, respectively. They can be fabricated on both sides of the substrate, improving the efficiency of process development.

[0058] refer to Figure 2 , Figure 2 This is a partial cross-sectional view of a vertical channel memory. (Example:) Figure 2 As shown, the channel 102 extends in the Z direction. A gate oxide layer 103, a gate layer 104, and an insulating structure 105 are sequentially formed on one sidewall of the channel 102. An insulating structure 105 is formed between two adjacent gate layers 104, and an isolation structure 109 with an air gap 111 is formed between two adjacent channels 102. The top of the channel 102 can also be doped to form a source electrode. The source electrode is electrically connected to the first electrode layer 110 of the storage capacitor, and the second electrode layer of the storage capacitor is connected to the common terminal. Figure 2The top end of the channel 102 shown in the dashed box is doped to form a source 112, which contacts the first electrode layer 110 of the storage capacitor. A metal silicide layer 113 is formed on the source 112, and the surface of the metal silicide layer 113 is lower than the surface of the gate oxide layer 103 (or the isolation structure 109). A tungsten layer 114 is formed on the metal silicide layer 113, and the surface of the tungsten layer 114 is flush with the surface of the gate oxide layer 103 (or the isolation structure 109). The first electrode layer 110 of the storage capacitor is formed on the tungsten layer 114.

[0059] Figure 3A The contact area between the metal silicide layer 113 and the source 112 is equal to the normal projection area of the source 112 on the XY plane.

[0060] As the feature size of the semiconductor process continues to shrink, the size of the gate, source and drain of the transistor will also shrink accordingly, and their equivalent series resistance will increase accordingly, thereby affecting the speed of the circuit. In the embodiment of the present disclosure, the source of the transistor and the first electrode layer of the storage capacitor are electrically connected through a metal silicide layer and a tungsten layer, and the metal silicide layer can reduce the contact resistance between the source (i.e., doped polysilicon) and the tungsten layer, thereby reducing the contact resistance between the source and the first electrode layer of the storage capacitor.

[0061] The process of phase change of the metal silicide formed directly on the source will be described in detail below in combination with Figure 3B and Figure 3A . Figure 3B The graph of the phase change of the metal silicide with the change of the annealing temperature is as follows: Figure 3A The graph of T1 and T2 with the change of the thickness or line width of the metal silicide is as follows:

[0062] First, a metal layer is formed to cover the source (i.e., doped polysilicon), the isolation structure (e.g., silicon dioxide) and the insulating structure (e.g., silicon dioxide), wherein the isolation structure and the insulating structure are both used to isolate the channels of different transistors, the metal layer directly contacts the doped polysilicon, and the metal layer directly contacts the silicon dioxide; then, a first rapid thermal annealing (RTA) process is performed, and the temperature of the annealing process is controlled so that only the doped polysilicon reacts with the atoms of the metal layer to form a C-49 phase metal silicide, and the silicon dioxide does not react with the atoms of the metal layer at this time. The C-49 phase metal silicide is a body-centered orthorhombic structure, and has a large resistance (for example, 1000 ohm-cm or more) at this time. Figure 3Athen, a wet etching process is used to remove the unreacted metal layer on the silicon dioxide; finally, a second rapid thermal annealing process is performed, and the temperature of the annealing process is controlled so that the C-49 phase metal silicide is converted into C-54 phase metal silicide, at this time, the C-54 phase metal silicide is a face-centered orthorhombic structure, and has a small resistance (for example Figure 3A

[0063] As shown in Figure 3B , the temperature T1 is the critical temperature at which the metal silicide is converted from the C-49 phase to the C-54 phase, and the temperature T2 is the critical temperature at which the metal silicide is bulked from the C-54 phase.

[0064] As shown in Figure 3A , as the thickness or line width of the metal silicide decreases, the critical temperature T1 at which the metal silicide is converted from the C-49 phase to the C-54 phase increases, and the critical temperature T2 at which the metal silicide is bulked from the C-54 phase decreases, so that a critical point T1 = T2 occurs, or even T2 < T1. Figure 4 As shown in , as the thickness or line width of the metal silicide decreases, if T2 < T1 occurs, the metal silicide is directly bulked from the C-49 phase, and there is no interval of the C-54 phase.

[0065] Due to the special structure of the vertical channel type memory, the size of the source is small, and the silicon source provided for the subsequent reaction with the atoms of the metal layer is small, so that the size of the metal silicide formed directly on the source is small, and the metal silicide is affected by the small size effect and the high temperature annealing process when forming the metal silicide, and it is difficult to form the C-54 phase metal silicide, and bulked directly and appear hollow defects. Further, the bulked metal silicide is difficult to achieve good electrical connection between the source of the transistor and the first electrode layer of the storage capacitor, and even can cause the channel formed by the silicon pillar to be broken, causing the semiconductor device to be open circuit.

[0066] Figures 5A-5F In view of this, the embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device provided by the embodiments of the present disclosure will be described in detail below in combination with Figures 6A-6I , Figure 4 .

[0067] The flow chart of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure is shown in Figure 4 . Figure 4 As shown in Figure 6A , the manufacturing method of the semiconductor device comprises the following steps:

[0068] ​In step S401, a semiconductor structure is provided, which includes a substrate and a plurality of transistor pillars arranged in an array on the substrate.

[0069] In step S402, a top end of each transistor pillar is etched to form a first recess.

[0070] In step S403, a metal silicide layer and a first metal layer are sequentially formed in the first recess; the metal silicide layer covers a bottom and sidewalls of the first recess; and the first metal layer fills the first recess.

[0071] Here, the semiconductor device provided by the embodiment of the present disclosure is taken as a vertical channel type memory for example.

[0072] In the embodiment of the present disclosure, the manufacturing method of the semiconductor device includes the following steps: etching from a substrate surface to form a plurality of silicon pillars arranged in an array and a first etching recess between the silicon pillars; wherein an extending direction of the silicon pillars is perpendicular to the substrate surface; the silicon pillars are arranged in an array along a first direction parallel to the substrate surface and a second direction parallel to the substrate surface; an insulating material is filled in the first etching recess to form an insulating structure surrounding each silicon pillar; the insulating structure is etched to form a second etching recess exposing at least two opposite sidewalls of each silicon pillar; and a metal material is filled in the second etching recess to form a gate layer.

[0073] In the embodiment of the present disclosure, the manufacturing method of the semiconductor device includes the following steps: etching from a substrate surface to form a plurality of silicon pillars arranged in an array and a first etching recess between the silicon pillars; wherein an extending direction of the silicon pillars is perpendicular to the substrate surface; the silicon pillars are arranged in an array along a first direction parallel to the substrate surface and a second direction parallel to the substrate surface; a gate oxide layer and a gate layer are sequentially formed on opposite sidewalls of each silicon pillar (or, opposite sidewalls of the first etching recess); and an insulating material is continuously filled in the first etching recess to form an insulating structure. Here, the insulating structure is used to realize electrical isolation between the gate layers on the sidewalls of adjacent two silicon pillars.

[0074] It should be noted that the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure does not have special limitation on the process sequence between the formation of the gate oxide layer, the gate layer and the insulating structure.

[0075] Here, the first direction can be an X direction, i.e., a column direction; and the second direction can be a Y direction, i.e., a row direction.

[0076] In some embodiments, before filling the metal material in the second etching groove, the method further comprises the following steps: performing an oxidation treatment on the exposed sidewall of the silicon pillar through the second etching groove to form a gate oxide layer on the sidewall of the silicon pillar. In other embodiments, before filling the metal material in the second etching groove, the method further comprises the following steps: forming a gate oxide layer through the second etching groove, the gate oxide layer covering the exposed sidewall of the silicon pillar.

[0077] In the embodiments of the present disclosure, the exposed sidewall of the silicon pillar can be in-situ oxidized by heating or pressurizing, so that the silicon on the sidewall of the silicon pillar chemically reacts with the gas containing the oxidizing substance at high temperature, thereby forming a dense silicon dioxide film on the surface of the silicon pillar to form a gate oxide layer. In the embodiments of the present disclosure, the gate oxide layer can also be formed by directly depositing silicon dioxide. The embodiments of the present disclosure do not limit the way of forming the gate oxide layer.

[0078] In the embodiments of the present disclosure, after forming the gate oxide layer and the gate layer, the method further comprises the following steps: etching the silicon pillar to form two transistor pillars. Here, the silicon pillar can be etched to form an isolation groove, and the isolation groove can be filled with an insulating material to form an isolation structure; wherein the isolation structure is used to isolate the two transistor pillars. As described above, the gate oxide layer and the gate layer are formed on the opposite two sidewalls of the silicon pillar, and after the silicon pillar is etched into two transistor pillars, the gate oxide layer and the gate layer are formed on one sidewall of each transistor pillar.

[0079] In the embodiments of the present disclosure, the method further comprises the following steps: etching from the surface of the substrate to form transistor pillars arranged in an array and isolation grooves or first etching grooves between adjacent transistor pillars; wherein the isolation grooves and the first etching grooves are arranged alternately; sequentially forming a gate oxide layer and a gate layer on the opposite two sidewalls of the first etching groove; and continuing to deposit an insulating material into the first etching groove and the isolation groove to form an insulating structure in the first etching groove and an isolation structure in the isolation groove.

[0080] It should be noted that the method for manufacturing the semiconductor device provided by the embodiments of the present disclosure does not have special limitations on the process sequence between the formation of the gate oxide layer, the gate layer, the insulating structure and the isolation structure.

[0081] In the embodiments of the present disclosure, before the step of filling the insulating material in the first etching groove to form the insulating structure surrounding each silicon pillar, the method for manufacturing the semiconductor device further comprises the following steps: depositing a first insulating structure to cover the bottom and sidewall of the first etching groove; wherein the first insulating structure only covers part of the sidewall of the first etching groove close to the bottom; and depositing a second insulating structure to cover the first insulating structure; wherein the second insulating structure fills the first etching groove. Here, the second insulating structure covers the first insulating structure and part of the sidewall of the first etching groove.

[0082] In the embodiments of the present disclosure, the first insulating structure and the second insulating structure can form a composite insulating structure. For example, the first insulating structure can be silicon nitride, and the second insulating structure can be silicon dioxide.

[0083] In the embodiments of the present disclosure, the adjacent two transistor pillars are electrically isolated by the isolation structure, and the gate layers of the adjacent two transistor pillars are electrically isolated by the first insulating structure and the second insulating structure. Here, the isolation structure can be the same material as the first insulating structure, or the isolation structure can be the same material as the second insulating structure. For ease of description, in the following description, the adjacent two transistor pillars and the gate layers of the adjacent two transistor pillars are electrically isolated by the composite insulating structure of the first insulating structure and the second insulating structure.

[0084] In step S401, a semiconductor structure is provided, and the semiconductor structure comprises a substrate and a plurality of transistor pillars arranged in an array on the substrate.

[0085] Figure 5A For Figure 5A The cross-sectional view corresponding to the three-dimensional structure is shown in FIG. 5B. Figure 6A and Figure 6B As shown in FIG. 5A, the semiconductor structure comprises a substrate 501 and a plurality of transistor pillars 502 arranged in an array on the substrate 501; wherein the extending direction of the transistor pillars 502 is perpendicular to the substrate 501. The first sidewall of the transistor pillar 502 sequentially forms a gate oxide layer 505, a gate layer 506 and a second insulating structure 504, and the second sidewall of the transistor pillar 502 forms an isolation structure 519; wherein the first sidewall and the second sidewall of the transistor pillar 502 are oppositely arranged. The gate layers 506 of the adjacent two transistor pillars 502 can be electrically isolated by the insulating structure (i.e., the first insulating structure 503 and the second insulating structure 504), and the adjacent two transistor pillars 502 can be electrically isolated by the isolation structure 519.

[0086] In the embodiments of the present disclosure, the first insulating structure and the second insulating structure are both insulating materials. The first insulating structure and the second insulating structure are located between the gate layers of two adjacent transistor columns, and are used for electrical isolation. Here, the first insulating structure and the second insulating structure jointly form a composite insulating structure, which is used for realizing electrical isolation between adjacent transistor columns.

[0087] In the embodiments of the present disclosure, in step S402, the top end of each transistor column is etched to form a first recess.

[0088] Figure 5B For Figure 5B The cross-sectional view corresponding to the three-dimensional structure is shown in Figure 6B and Figure 6B The top end of the transistor column 502 is etched to form a first recess 507. The first sidewall of the first recess 507 exposes the gate oxide layer 505 (or the second insulating structure 504), and the second sidewall of the first recess 507 exposes the isolation structure 519. The first sidewall and the second sidewall of the first recess are oppositely arranged. The transistor column 502 is partially etched in a direction perpendicular to the substrate (i.e., the Z direction) to form the first recess 507. The etching depth of the first recess 507 is less than the height of the transistor column 502. Figure 6B It is shown that the width of the opening of the first recess 507 is W1 along the Y direction, and the depth of the first recess 507 is H1 along the Z direction.

[0089] In the embodiments of the present disclosure, the transistor column 502 presents a rectangle in the YZ plane, and the width of the top end of the transistor column 502 is equal to the width of the bottom end of the silicon column. In fact, the present disclosure does not have special restrictions on the shape of the transistor column in the YZ plane.

[0090] As shown in Figure 6C The top end of the transistor column 502 exposed by the first recess 507 is ion implanted to form a source 508 at the top end of each transistor column 502. The doping depth H3 of the source 508 is greater than the depth H1 of the first recess 507. The width of the source 508 at the top end of each transistor column 502 along the Y direction is equal to the width W1 of the transistor column 502.

[0091] Here, the transistor column has two ends in the direction perpendicular to the substrate. The end of the transistor column away from the surface of the substrate is the top end of the transistor column.

[0092] Figure 5C For Figure 5C The cross-sectional view corresponding to the three-dimensional structure is shown in Figure 6C and Figure 6C A silicon liner 509 is deposited on the bottom and sidewall of the first recess and the second insulating structure 504 to form a second recess 510.

[0093] Here, the material of the silicon substrate may include polycrystalline silicon or doped polycrystalline silicon. Figure 6D The diagram shows that the material of the silicon substrate is the same as that of the source electrode, both being doped polycrystalline silicon.

[0094] Figure 5D for Figure 5D The sectional view corresponding to the three-dimensional structure shown is as follows: Figure 6D and Figure 6D As shown, the silicon substrate 509 covering the bottom and sidewalls of the first groove is retained. The silicon substrate 509 on the second insulating structure 504 is removed by chemical mechanical polishing (CMP) to expose the surface of the second insulating structure 504. Figure 6D The diagram illustrates that along the Y direction, the width of the opening of the second groove 510 is W2; and along the Z direction, the depth of the second groove 510 is H2. Specifically, the width W1 of the opening of the first groove 507 is greater than the width W2 of the opening of the second groove 510; and the depth H1 of the first groove 507 is greater than the depth H2 of the second groove 510. Thus, Figure 6E As shown, along the Z direction, the thickness of the silicon substrate 509 covering the bottom of the first groove is (H1-H2); along the Y direction, the thickness of the silicon substrate 509 covering the sidewall of the first groove is [(W1-W2) / 2].

[0095] like Figure 6F As shown, a second metal layer 511 is formed covering the bottom and sidewalls of the second groove and the second insulating structure 504. More specifically, a second metal layer 511 is formed covering the silicon substrate 509 and the second insulating structure 504.

[0096] In some embodiments, the material of the second metal layer includes at least one of the following: nickel, cobalt, and titanium.

[0097] In some embodiments, a titanium nitride layer is formed on the second metal layer. Here, forming a titanium nitride layer covering the second metal layer can prevent the second metal layer from flowing during subsequent annealing processes.

[0098] In this embodiment of the disclosure, a second metal layer or titanium nitride layer can be deposited using processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0099] In this embodiment of the present disclosure, in step S403, a metal silicide layer and a first metal layer are sequentially formed in the first groove; the metal silicide layer covers the bottom and sidewalls of the first groove; and the first metal layer fills the first groove.

[0100] In this embodiment, the second metal layer covering the bottom and sidewalls of the second groove and the second insulating structure is annealed. The depth of atomic diffusion from the second metal layer into the silicon substrate can be controlled by adjusting parameters such as the annealing temperature and time, thereby controlling the thickness of the metal silicide layer. Here, the thickness of the metal silicide layer along the Y direction can be the same as the thickness of the silicon substrate covering the sidewalls of the first groove, i.e., [(W1-W2) / 2]; the thickness of the metal silicide layer along the Z direction can be the same as the thickness of the silicon substrate covering the bottom of the first groove, i.e., (H1-H2). Thus, annealing the second metal layer forms a metal silicide layer at the bottom and sidewalls of the first groove. At this point, the metal silicide layer at the top of the transistor pillar is groove-shaped, and the second metal layer fills the groove formed by the metal silicide layer. The contact area between the metal silicide layer and the source electrode is the orthogonal projection area of ​​the source electrode on the XY plane.

[0101] certainly, Figure 6F The illustrated metal silicide layer has a thickness along the Y direction that is less than the thickness of the silicon substrate covering the sidewall of the first groove. In this case, the metal silicide layer at the top of the transistor pillar is groove-shaped, and the second metal layer fills the groove formed by the metal silicide layer. The contact area between the metal silicide layer and the source is greater than the orthogonal projection area of ​​the source on the XY plane. In this embodiment, ensuring an increased contact area between the second metal layer and the top of the transistor pillar (i.e., the silicon substrate) reduces the small-size effect of forming the metal silicide layer and provides sufficient silicon source for the reaction to form the metal silicide layer, ensuring the formation of a stable crystalline phase metal silicide layer and improving its thermal stability.

[0102] Figure 5E for Figure 5E The sectional view corresponding to the three-dimensional structure shown is as follows: Figure 6E , Figure 6F and Figure 6E As shown, the second metal layer 511 is annealed, causing atoms of the second metal layer 511 to interdiffused with atoms of the doped polycrystalline silicon (i.e., silicon substrate 509) at the bottom and sidewalls of the first trench, forming a metal silicide layer 512 at the bottom and sidewalls of the first trench. During this process, the silicon substrate at the top of each transistor pillar (i.e., the silicon substrate located on the source) reacts with the second metal layer to form a metal silicide layer. In subsequent processes, the metal silicide layer on the source of the transistor can be used to reduce the contact resistance between the source of the transistor and the first electrode layer of the storage capacitor.

[0103] Here, the second metal layer undergoes a first annealing process, and the annealing temperature is controlled so that only the silicon substrate (i.e., polysilicon or doped polysilicon) at the top of each transistor pillar reacts with the atoms of the second metal layer to form a pre-metal silicide layer, while the second insulating structure between two adjacent transistor pillars does not react with the atoms of the second metal layer; the unreacted second metal layer in the first annealing process is removed using a wet etching process; the pre-metal silicide layer undergoes a second annealing process, and the annealing temperature is controlled so that the phase state of the pre-metal silicide layer changes to form a metal silicide layer with a more stable phase and lower resistance.

[0104] In this embodiment, the pre-metal silicide layer can be a C-49 phase metal silicide, which has a higher resistance; the metal silicide layer can be a C-54 phase metal silicide, which has a lower resistance.

[0105] In this embodiment of the disclosure, the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment. The temperature of the first annealing treatment may be, for example, 450°C to 650°C, and the temperature of the second annealing treatment may be, for example, 750°C to 950°C.

[0106] Figure 6F The contact area between the schematic second metal layer 511 and the top of each transistor pillar 502 (more specifically, the silicon substrate 509 at the top of each transistor pillar 502) is equal to the sum of the areas of the bottom and sidewalls of the second recess. Figure 6F The schematic metal silicide layer 512 covers the bottom and sidewalls of the first groove. Thus, Figure 6G The contact area between the schematic metal silicide layer 512 and the source 508 at the top of each transistor pillar 502 can also be the sum of the areas of the bottom and sidewalls of the first groove. It should be noted that the orthographic projection area of ​​the top of each transistor pillar 502 on the XY plane is the same as the orthographic projection area of ​​the source 508 at the top of each transistor pillar 502 on the XY plane, and is also equivalent to the orthographic projection area of ​​the bottom of the first groove on the XY plane.

[0107] In other words, by first etching a first groove at the top of the transistor pillar, a silicon substrate is deposited at the bottom and sidewalls of the first groove to form a second groove; a second metal layer is deposited at the bottom and sidewalls of the second groove. The contact area between the second metal layer and the silicon substrate is the sum of the areas of the bottom and sidewalls of the second groove, which is greater than the orthogonal projection area of ​​the source on the XY plane. This reduces the small size effect of forming the metal silicide layer and provides sufficient silicon source for the reaction to form the metal silicide layer, ensuring the formation of a stable crystalline phase metal silicide layer and improving the thermal stability of the metal silicide layer.

[0108] Figure 5F for Figure 5F The sectional view corresponding to the three-dimensional structure shown is as follows:Figure 6G and Figure 6H As shown, a first metal layer 513 is formed by filling the first groove with metal material. The metal silicide layer 512 and the first metal layer 513 are used to realize the electrical connection between the source 508 and the first electrode layer of the storage capacitor. More specifically, the metal silicide layer 512 at the top of the transistor pillar 502 is groove-shaped, and the first metal layer 513 fills the groove formed by the metal silicide layer 512.

[0109] In this embodiment, a metal silicide layer is formed on the sidewalls and bottom of the first groove at the top of the transistor pillar, instead of only at the top of the source. The contact area between the second metal layer and the transistor pillar (i.e., the contact area between the second metal layer and the silicon substrate, or the sum of the areas of the bottom and sidewalls of the second groove) is greater than the contact area between the second metal layer and the source (i.e., the orthogonal projection area of ​​the source on the XY plane). This increased contact area reduces the small-size effect of forming the metal silicide layer and provides sufficient silicon source for the reaction, ensuring the formation of a metal silicide layer of sufficient thickness and a stable crystalline phase, thereby improving the thermal stability of the metal silicide layer. Furthermore, in this embodiment, the size of the metal silicide layer formed after etching the first groove at the top of the transistor pillar is significantly larger than that formed directly at the top of the source, which reduces the impact of the small-size effect on the formation of a stable metal silicide layer.

[0110] like Figure 6H As shown, a hard mask layer 514 and a support layer 515 are formed on a first metal layer 513, a metal silicide layer 512, and a second insulating structure 504. The support layer 515 and the hard mask layer 514 are etched to form capacitor vias exposing the metal silicide layer. A first electrode layer 516 is deposited to cover the bottom and sidewalls of the capacitor vias and the surface of the support layer. The first electrode layer covering the support layer is removed, exposing the surface of the support layer, leaving only the first electrode layer covering the bottom and sidewalls of the capacitor vias. Thus, the corresponding first electrode layer within each capacitor via can be used to form an independent storage capacitor, with different storage capacitors being insulated from each other.

[0111] like Figure 6I and Figure 7 As shown, after removing the support layer, a capacitor dielectric layer 517 and a second electrode layer 518 are sequentially deposited on the hard mask layer 514 and the inner and outer sidewalls of the first electrode layer 516 to form a storage capacitor. This disclosure does not limit the structure of the storage capacitor, and the storage capacitor in the semiconductor device provided in this disclosure is not limited to the structure shown in 6I.

[0112] In this embodiment of the present disclosure, after forming a capacitor via exposing a metal silicide layer, a first electrode layer is formed covering the bottom and sidewalls of the capacitor via. The first electrode layer is connected to the source through the metal silicide layer and the first metal layer. A capacitor dielectric layer covering the first electrode layer and a second electrode layer covering the capacitor dielectric layer are then formed. The second electrode layer is connected to the common terminal.

[0113] This disclosure provides a semiconductor device, which includes: a transistor array having transistor pillars; each transistor pillar of the transistor array has a source and a drain at both ends of its extension direction; wherein a trench-shaped metal silicide layer and a first metal layer are formed on the top of the source, and the first metal layer fills the trench formed by the metal silicide layer; the metal silicide layer and the first metal layer are used to realize the electrical connection between the source and the storage capacitor.

[0114] In this embodiment of the disclosure, the transistor pillars of the transistor array are arranged in an array along a first direction and a second direction, and the extension direction of the transistor pillars is perpendicular to the plane formed by the first direction and the second direction.

[0115] In this embodiment of the disclosure, the contact area between the metal silicide layer and the source electrode is greater than the orthogonal projection area of ​​the source electrode on the plane formed by the first direction and the second direction.

[0116] refer to Figure 7 , Figure 7 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. (See attached image.) ​ As shown, the semiconductor device includes a transistor array with transistor pillars 701; wherein each transistor pillar 701 of the transistor array is arranged in an array along a first direction (i.e., the X direction) and a second direction (i.e., the Y direction), and the extension direction (i.e., the Z direction) of the transistor pillar 701 is perpendicular to the plane formed by the first direction and the second direction; at least one sidewall of each transistor pillar 701 of the transistor array has a gate oxide layer 704 and a gate layer 705; each end of the extension direction of each transistor pillar 701 of the transistor array has a source 706 and a drain 707, respectively; wherein a metal silicide layer 708 and a first metal layer 709 are formed on the source 706, and the metal silicide layer 708 and the first metal layer 709 are used to realize the electrical connection between the source 706 and the first electrode layer of the storage capacitor; the contact area between the metal silicide layer 708 and the source 706 is larger than the orthogonal projection area of ​​the source 706 on the plane formed by the first direction and the second direction.

[0117] In this embodiment of the present disclosure, a first insulating structure 702 and a second insulating structure 703 are formed between the gate layers 705 of two adjacent transistor pillars to form a composite insulating structure.

[0118] In this embodiment of the present disclosure, a gate oxide layer 704, a gate layer 705 and an insulating structure (i.e., a first insulating structure 702 and a second insulating structure 703) are sequentially provided on the first sidewall of the transistor pillar 701, and an isolation structure 710 is provided on the second sidewall of the transistor pillar 701; wherein, the first sidewall and the second sidewall of the transistor pillar are two opposite sidewalls of the transistor pillar.

[0119] In this embodiment of the present disclosure, the contact area between the metal silicide layer and the source electrode is increased, and the metal silicide layer and the first metal layer can achieve a stable electrical connection between the source electrode of the transistor and the first electrode layer of the storage capacitor, thereby improving the stability of the semiconductor device.

[0120] In this embodiment of the disclosure, the semiconductor device further includes: a storage capacitor; wherein the first electrode layer of the storage capacitor is connected to the source of each transistor, and the second electrode layer of the storage capacitor is connected to a common terminal.

[0121] This disclosure provides a semiconductor device and a method for manufacturing the same. The method includes: providing a semiconductor structure, the semiconductor structure including a substrate and a plurality of transistor pillars arranged in an array on the substrate; etching the top of each transistor pillar to form a first groove; sequentially forming a metal silicide layer and a first metal layer in the first groove; the metal silicide layer covering the bottom and sidewalls of the first groove; and the first metal layer filling the first groove. In this disclosure, by first etching the top of the transistor pillar to form the first groove, and then forming the metal silicide layer at the bottom and sidewalls of the first groove, the contact area between the metal silicide layer and the transistor pillar is increased, reducing the small-size effect of forming the metal silicide layer, and providing sufficient silicon source for the reaction to form the metal silicide layer, ensuring the formation of a stable crystalline phase metal silicide layer, thereby improving the thermal stability of the metal silicide layer. Furthermore, the stable metal silicide layer is used to achieve a stable electrical connection between the source of the transistor and the storage capacitor, thereby improving the reliability of the semiconductor device.

[0122] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0123] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: providing a semiconductor structure comprising a substrate and a plurality of transistor columns arranged in an array on the substrate; a gate oxide layer, a gate layer and an insulating structure are sequentially arranged on a first sidewall of the transistor column; an isolation structure is arranged on a second sidewall of the transistor column; wherein the first sidewall of the transistor column and the second sidewall of the transistor column are opposite two sidewalls of the transistor column; etching a top end of each transistor column to form a first recess, comprising: etching a top end of each transistor column to form a first recess, a first sidewall of the first recess exposes the insulating structure, and a second sidewall of the first recess exposes the isolation structure; wherein the first sidewall of the first recess and the second sidewall of the first recess are opposite two sidewalls of the first recess; forming a metal silicide layer and a first metal layer in the first recess in sequence; the metal silicide layer covers the bottom and sidewall of the first recess; the first metal layer fills the first recess.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The extension direction of the transistor column is perpendicular to the substrate.

3. The method of manufacturing a semiconductor device according to claim 1, wherein The metal silicide layer and the first metal layer at the top end of each transistor column are used to realize electrical connection between the source and the storage capacitor.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein After etching the top end of each transistor column to form a first recess, the method further comprises: forming a silicon liner on the bottom and sidewall of the first recess to form a second recess.

5. The method of manufacturing a semiconductor device according to claim 4, wherein forming the metal silicide layer comprises: forming a second metal layer covering the bottom and sidewall of the second recess; annealing the second metal layer to form the metal silicide layer on the bottom and sidewall of the first recess.

6. The method of manufacturing a semiconductor device according to claim 5, wherein The annealing of the second metal layer to form the metal silicide layer on the bottom and sidewall of the first recess comprises: first annealing the second metal layer to make atoms of the second metal layer and atoms of the silicon liner react to form a pre-metal silicide layer on the bottom and sidewall of the first recess; second annealing the pre-metal silicide layer to form the metal silicide layer; wherein the temperature of the first annealing is lower than the temperature of the second annealing.

7. The method of manufacturing a semiconductor device according to claim 6, wherein After the first annealing of the second metal layer, the method further comprises: using a wet etching process to remove the second metal layer that is not reacted in the first annealing.

8. The method of manufacturing a semiconductor device according to Claim 1, wherein Before forming the metal silicide layer and the first metal layer in the first recess in sequence, the method further comprises: ion implanting the top end of each transistor column to form a source at the top end of each transistor column; wherein, in a direction perpendicular to the substrate, the depth of the source is greater than the depth of the first recess.

9. The method of manufacturing a semiconductor device according to Claim 1, wherein After forming the metal silicide layer and the first metal layer in the first recess in sequence, the method further comprises: A storage capacitor is formed on each of the transistor columns, a first electrode layer of the storage capacitor is electrically connected to a source through the metal silicide at the top end of the transistor column and the first metal layer, and a second electrode layer of the storage capacitor is connected to a common terminal.

10. The method of manufacturing a semiconductor device according to Claim 1, wherein The semiconductor device includes a vertical channel type memory.

11. A semiconductor device, characterized by comprising: The semiconductor device includes: A transistor array with transistor columns; a gate oxide layer, a gate layer and an insulating structure are sequentially arranged on a first sidewall of the transistor column, and an isolation structure is arranged on a second sidewall of the transistor column; wherein the first sidewall of the transistor column and the second sidewall of the transistor column are opposite two sidewalls of the transistor column. Two ends of the extension direction of each of the transistor columns of the transistor array are respectively provided with a source and a drain; wherein a groove-shaped metal silicide layer and a first metal layer are formed on the top end of the source, and the first metal layer fills the groove formed by the metal silicide layer; the metal silicide layer and the first metal layer are used to realize the electrical connection between the source and a storage capacitor; a first sidewall of the groove-shaped metal silicide layer is close to the insulating structure, and a second sidewall of the groove-shaped metal silicide layer is close to the isolation structure; wherein the first sidewall of the groove-shaped metal silicide layer and the second sidewall of the groove-shaped metal silicide layer are opposite two sidewalls of the groove-shaped metal silicide layer.

12. The semiconductor device of claim 11, wherein, The transistor columns of the transistor array are arranged in an array along a first direction and a second direction, and the extension direction of the transistor column is perpendicular to the plane formed by the first direction and the second direction.

13. The semiconductor device of claim 12, wherein, The contact area between the metal silicide layer and the source is greater than the normal projection area of the source on the plane formed by the first direction and the second direction.

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