Substrate integrated with passive devices and preparation method thereof

Abstract

The present disclosure provides a substrate integrated with passive devices and a preparation method thereof, belonging to the field of radio frequency device technology. The preparation method of the substrate integrated with passive devices disclosed in the present disclosure includes: providing a first dielectric layer and a second dielectric layer, and forming a first connecting through-hole and a second connecting through-hole on the first dielectric layer and the second dielectric layer, respectively; forming an integrated passive device on the first dielectric layer and the second dielectric layer; the passive device includes at least an inductor; the inductor includes: forming a first substructure on the first dielectric layer, forming a first connecting electrode in the first connecting through-hole, forming a second substructure on the second dielectric layer, and forming a second connecting electrode in the second connecting through-hole; the first dielectric layer and the second dielectric layer are bonded together, and the first substructure, the first connecting electrode, the second connecting electrode and the second substructure are electrically connected to form the coil structure of the inductor.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency devices, and in particular relates to a substrate integrated with passive devices and a preparation method thereof. Background Art

[0002] In modern times, the consumer electronics industry is developing rapidly. Mobile communication terminals represented by mobile phones, especially 5G mobile phones, are developing rapidly. Mobile phones need to process more and more signal frequency bands, and the number of radio frequency chips required is also rising. The mobile phone forms that are popular with consumers are constantly developing towards miniaturization, lightness, and long battery life. In traditional mobile phones, there are a large number of discrete components such as resistors, capacitors, inductors, filters, etc. on the radio frequency PCB (Printed Circuit Board). They have the disadvantages of large size, high power consumption, many solder joints, and large variations in parasitic parameters, making it difficult to meet future needs. The interconnection and matching between radio frequency chips require integrated passive components with small area, high performance, and good consistency.

[0003] Currently, integrated passive devices on the market are primarily based on Si (silicon) and GaAs (gallium arsenide) substrates. Si-based integrated passive devices are inexpensive, but trace impurities in Si (poor insulation) lead to high microwave losses and mediocre performance. GaAs-based integrated passive devices offer excellent performance but are expensive. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a substrate integrated with passive devices and a preparation method thereof.

[0005] An embodiment of the present disclosure provides a method for preparing a substrate for integrating passive devices, comprising:

[0006] Providing a first dielectric layer and a second dielectric layer, and forming a plurality of first connecting vias on the first dielectric layer, and forming a plurality of second connecting vias on the second dielectric layer; the first dielectric layer includes a first surface and a second surface disposed opposite to each other along a thickness direction; and the second dielectric layer includes a third surface and a fourth surface disposed opposite to each other along the thickness direction;

[0007] An integrated passive device, wherein the passive device comprises at least an inductor; the steps of forming the inductor include:

[0008] forming a first substructure on the first surface of the first dielectric layer, and forming a first connecting electrode in the first connecting via hole;

[0009] forming a second substructure on the fourth surface of the second dielectric layer, and forming a second connecting electrode in the second connecting via hole;

[0010] The second surface of the first dielectric layer and the third surface of the second dielectric layer are bonded together, the orthographic projections of one first connecting via and one second connecting via on the first dielectric layer at least partially overlap, one first connecting electrode and one second connecting electrode are electrically connected, and the first substructure, the first connecting electrode, the second connecting electrode, and the second substructure are electrically connected to form the coil structure of the inductor.

[0011] The step of forming a plurality of first connecting vias on the first dielectric layer and forming a plurality of second connecting vias on the second dielectric layer includes:

[0012] Cleaning, drilling, and etching the first dielectric layer to form a plurality of first connecting vias penetrating the first dielectric layer in a thickness direction thereof;

[0013] A plurality of second connecting vias penetrating the second dielectric layer in a thickness direction are formed by cleaning, drilling and etching the second dielectric layer.

[0014] The steps of forming the first substructure and forming the first connecting electrode include:

[0015] attaching the second surface of the first dielectric layer to the first base substrate;

[0016] forming a first metal film layer on the first connecting via hole and the first surface as a first seed layer;

[0017] performing an electroplating process on the first seed layer to form the first connecting electrode located in the first connecting via hole and the first metal film layer covering the first surface;

[0018] performing a patterning process on the first metal film layer to form a pattern including the first substructure;

[0019] The first base substrate is peeled off from the second surface of the first dielectric layer.

[0020] The steps of forming the second substructure and forming the second connecting electrode include:

[0021] attaching the third surface of the second dielectric layer to the second base substrate;

[0022] forming a fourth metal film layer on the second connecting through hole and the fourth surface as a second seed layer;

[0023] performing an electroplating process on the second seed layer to form the second connecting electrode located in the second connecting via hole and the second metal film layer covering the fourth surface;

[0024] performing a patterning process on the fourth metal film layer to form a pattern including the second substructure;

[0025] The second base substrate is peeled off from the third surface of the second dielectric layer.

[0026] The step of laminating the first dielectric layer and the second dielectric layer comprises:

[0027] A first adhesive layer is formed on the second surface of the first dielectric layer or the third surface of the second dielectric layer, and the second surface of the first dielectric layer or the third surface of the second dielectric layer is bonded to the first adhesive layer.

[0028] Wherein, the material of the first bonding layer includes anisotropic conductive adhesive.

[0029] Wherein, the passive component further includes a capacitor; and the preparation method further includes:

[0030] Performing a patterning process on the first metal film layer to form a pattern including a first plate of the capacitor on the first surface;

[0031] forming a first insulating layer on a side of the first electrode plate of the capacitor facing away from the first dielectric layer;

[0032] Through a patterning process, a pattern including the second plate of the capacitor is formed on a side of the first insulating layer facing away from the first dielectric layer.

[0033] The step of forming the first plate of the capacitor includes:

[0034] The first electrode plate of the capacitor and the first substructure are manufactured by a single patterning process.

[0035] Wherein, the preparation method further comprises:

[0036] forming a second insulating layer on a side of the second plate of the capacitor facing away from the first dielectric layer, and forming a third connecting via and a fourth connecting via penetrating the first insulating layer and the second insulating layer; the third connecting via at least partially overlaps with an orthographic projection of the first end of the inductor on the first dielectric layer;

[0037] The fourth connecting via hole at least partially overlaps with the orthographic projection of the second electrode plate of the capacitor on the first dielectric layer;

[0038] A third connecting electrode is formed on a side of the second insulating layer away from the first dielectric layer; the first connecting electrode is electrically connected to the first end of the inductor and the second plate of the capacitor through the third connecting via and the fourth connecting via.

[0039] Wherein, the preparation method further comprises:

[0040] forming a first isolation layer and a first protection layer in sequence on a side of the third connection electrode facing away from the first dielectric layer, and forming a fifth connection via hole penetrating the first isolation layer and the first protection layer;

[0041] A third insulating layer and a second protective layer are sequentially formed on the fourth surface of the second dielectric layer.

[0042] Wherein, the first dielectric layer and / or the second dielectric layer comprises a glass substrate.

[0043] The present disclosure provides a substrate integrated with passive devices, comprising:

[0044] A first dielectric layer and a second dielectric layer are stacked, and passive components are integrated on the first dielectric layer and the second dielectric layer; wherein,

[0045] The first dielectric layer includes a first surface and a second surface arranged along the thickness direction thereof; the first dielectric layer is provided with a first connecting via hole penetrating along the thickness direction thereof;

[0046] The second dielectric layer includes a third surface and a fourth surface arranged along the thickness direction thereof; the second dielectric layer is provided with a second connecting via hole penetrating along the thickness direction thereof;

[0047] The passive component includes at least an inductor; the inductor includes a first substructure arranged on the first surface and a second substructure arranged on the fourth surface, as well as a first connecting electrode arranged in the first connecting via and a second connecting electrode arranged in the second connecting via; the orthographic projections of one first connecting via and one second connecting via on the first dielectric layer at least partially overlap, one first connecting electrode is electrically connected to one second connecting electrode, and the first substructure, the first connecting electrode, the second connecting electrode and the second substructure are electrically connected to form the coil structure of the inductor.

[0048] Wherein, the first dielectric layer and / or the second dielectric layer comprises a glass substrate.

[0049] Wherein, the thickness of the first dielectric layer and / or the second dielectric layer is 0.2 mm-0.3 mm.

[0050] In which, the passive component also includes a capacitor; wherein the first plate of the capacitor is arranged in the same layer as the first substructure of the inductor; the substrate also includes a first insulating layer located on the side of the first plate of the capacitor facing away from the first dielectric layer; the second plate of the capacitor is located on the side facing away from the first insulating layer, and the second plate of the capacitor at least partially overlaps with the orthographic projection of the first plate on the first surface of the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 FIG. 4 is a top view of an inductor according to an embodiment of the present disclosure.

[0052] Figure 2 This is an LC oscillation circuit diagram.

[0053] Figure 3 Schematic diagram of a substrate integrated with passive devices according to an embodiment of the present disclosure.

[0054] Figure 4 FIG. 1 is a schematic diagram of a substrate formed in step S11 according to an embodiment of the present disclosure.

[0055] Figure 5 Schematic diagram of a substrate formed in step S12 of an embodiment of the present disclosure.

[0056] Figure 6 FIG. 1 is a schematic diagram of a substrate formed in step S13 according to an embodiment of the present disclosure.

[0057] Figure 7 FIG. 1 is a schematic diagram of a substrate formed in step S14 according to an embodiment of the present disclosure.

[0058] Figure 8 FIG. 1 is a schematic diagram of a substrate formed in step S15 according to an embodiment of the present disclosure.

[0059] Figure 9 Schematic diagram of a substrate formed in step S16 according to an embodiment of the present disclosure.

[0060] Figure 10 Schematic diagram of a substrate formed in step S19 of an embodiment of the present disclosure.

[0061] Figure 11 FIG. 1 is a schematic diagram of a substrate formed in step S20 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0063] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by persons of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar expressions used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one. Terms such as "include" or "comprising" mean that the element or object preceding the term includes the elements or objects listed after the term, and their equivalents, without excluding other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; if the absolute position of the described object changes, the relative positional relationship may also change accordingly. Considering the manufacturing cost and complexity of integrated passive devices, glass substrates are selected as the substrate for integrated passive devices. Glass-based integrated passive devices have the advantages of excellent high-frequency characteristics, high insulation, and low loss.

[0064] The inventors discovered that when manufacturing glass-based integrated passive devices, the depth-to-width ratio of the TGV (Through Glass Via) holes produced by existing glass laser drilling technology is relatively large. This makes sputtering the seed layer of the integrated passive device more difficult during the manufacturing process, increasing the difficulty of manufacturing the integrated passive device. Therefore, providing a glass-based integrated passive device that is easier to manufacture is an urgent technical problem to be solved.

[0065] The present disclosure provides a substrate with integrated passive components and a method for manufacturing the same. Passive components, such as capacitors and inductors, are integrated onto the substrate to form a circuit structure. In the present disclosure, an LC oscillator circuit integrated onto the substrate is used as an example. In other words, at least components such as an inductor and a capacitor are integrated onto the substrate.

[0066] Figure 1 is a top view of the inductor according to an embodiment of the present disclosure, referring to Figure 1, each first substructure 212 of the inductor extends along the first direction and is arranged side by side along the second direction; each second substructure 211 of the inductor extends along the third direction and is arranged side by side along the second direction. Among them, the first direction, the second direction, and the third direction are all different directions. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are arranged non-perpendicularly. Of course, the extension directions of the first substructure 212 and the second substructure 211 can also be interchanged, and are all within the protection scope of the embodiment of the present disclosure. In addition, in the embodiment of the present disclosure, an example is given in which the inductor includes N first substructures 212 and N-1 second substructures 211, where N≥2 and N is an integer. The first end and the second end of the first substructure 212 respectively overlap with the orthographic projection of a first connecting via 11 on the first glass substrate 10. And the first end and the second end of a first substructure 212 correspond to different first connecting vias 11, that is, the orthographic projections of a first substructure 212 and two first connecting vias 11 on the first glass substrate 10 at least partially overlap. At this time, the first end of the i-th second substructure 211 of the inductor is connected to the first end of the i-th first substructure 212 and the second end of the i+1-th first substructure 212 to form an inductor coil, where 1≤i≤N-1 and i is an integer.

[0067] It should be noted that the first lead terminal 22 is connected to the second end of the first first substructure 212 of the inductor, and the second lead terminal 23 is connected to the first end of the Nth first substructure 212. Furthermore, the first lead terminal 22 and the second lead terminal 23 can be arranged on the same layer as the second substructure 211 and made of the same material. In this case, the first lead terminal 22 can be connected to the second end of the first first substructure 212 through the first connecting via 11, and correspondingly, the second lead terminal 23 can be connected to the first end of the Nth first substructure 212 through the first connecting via 11.

[0068] Figure 2 It is a LC oscillation circuit diagram; Figure 2 As shown, the LC oscillating circuit includes an inductor and a capacitor. The inductor in the figure is referred to as the first inductor L1, and the capacitor in the figure is referred to as the first capacitor C1. Figure 2 The first lead end of the first inductor L1 is connected to the second plate of the first capacitor C1, and the second end of the first inductor L1 is connected to the first plate of the first capacitor C1.

[0069] Figure 3 is a cross-sectional view of a substrate integrated with passive devices in an embodiment of the present disclosure; Figure 3 As shown, the passive device is Figure 2The LC oscillator circuit shown is integrated onto a first dielectric layer and a second dielectric layer. The first dielectric layer includes a first surface and a second surface extending along its thickness, and has a first connection via 11 extending through its thickness. The second dielectric layer includes a third surface and a fourth surface extending along its thickness, and has a second connection via extending through its thickness. The first connection electrode 213 of the inductor is formed in the first connection via 11, and the second connection electrode 214 is formed in the second connection via. The first substructure 212 of the inductor is formed on the first surface of the first dielectric layer, and the second substructure 211 of the inductor is formed on the fourth surface of the second dielectric layer. The second surface of the first dielectric layer and the third surface of the second dielectric layer are aligned, and the orthographic projections of the first and second connection vias on the first dielectric layer at least partially overlap.

[0070] In the embodiments of the present disclosure, the first and second dielectric layers include, but are not limited to, any one of a glass substrate, a flexible substrate, and an interlayer dielectric layer comprising at least an organic insulating layer. Because integrating passive components on a glass substrate offers advantages such as small size, light weight, high performance, and low power consumption, the first and second dielectric layers in the embodiments of the present disclosure are preferably constructed using a glass substrate. The following description uses a glass substrate as an example for the first and second dielectric layers.

[0071] Continue to refer to Figure 3 In some examples, the first electrode 31 of the first capacitor C1 is disposed on the first surface and is disposed in the same layer as the first substructure 212 of the inductor coil. A first insulating layer 5 is disposed on a side of the first capacitor C1 facing away from the first electrode 31, and a second electrode 32 of the first capacitor C1 is disposed on a side of the first insulating layer 5 facing away from the first electrode 31 of the first capacitor C1. A second insulating layer 6 is disposed on a side of the first capacitor C1 facing away from the second electrode 32, and a third connecting electrode 7 is disposed on a side of the second insulating layer 6 facing away from the second electrode 32. The third electrode 7 connects the first end of the first inductor L1 to the second electrode 32 of the first capacitor C1 via a third connecting via penetrating the first and second insulating layers 5 and 6 and a fourth connecting via in the second insulating layer 6. A first isolation layer 8 and a first protective layer 9 are disposed on a side of the third electrode 7 facing away from the first glass substrate 10, and a fifth connecting via is formed penetrating the first isolation layer 8 and the first protective layer 9.

[0072] Continue to refer to Figure 3 A third insulating layer 12 and a second protective layer 13 are provided on the side of the second substructure 211 facing away from the second glass substrate 20 to insulate and protect the second substructure 211 .

[0073] Since the passive device is formed by laminating the first glass substrate 10 and the second glass substrate 20, thinner first glass substrate 10 and second glass substrate 20 can be selected to reduce the aspect ratio of the first connecting via 11 and the second connecting via thereon, thereby reducing the difficulty of sputtering the seed layer. Ultimately, a passive device is obtained that is easier to manufacture.

[0074] The structural parameters of each device on the substrate integrated with passive devices in the embodiment of the present disclosure are described one by one in the following preparation method, and therefore will not be described in detail here.

[0075] In an embodiment of the present disclosure, a method for preparing a substrate integrated with passive devices is provided. The substrate may be the above-mentioned substrate. The method comprises the following steps:

[0076] A first glass substrate 10 is provided and processed to obtain a first glass substrate 10 having a first connection via 11. The first glass substrate 10 includes a first surface and a second surface disposed opposite to each other along the thickness direction. A second glass substrate 20 is provided and processed to obtain a second glass substrate 20 having a second connection via. The second glass substrate 20 includes a third surface and a fourth surface disposed opposite to each other along the thickness direction.

[0077] Passive components are integrated on the first glass substrate 10 and the second glass substrate 20 ; the passive components at least include an inductor.

[0078] The passive components on the first glass substrate 10 include: a first substructure 212 formed on the first surface of the first glass substrate 10, and a first connecting electrode 31 formed within the first connecting via 11. The passive components on the second glass substrate 20 include: a second substructure 211 formed on the fourth surface of the second glass substrate 20, and a second connecting electrode 214 formed within the second connecting via. The second surface of the first glass substrate 10 and the third surface of the second glass substrate 20 are bonded together, the first connecting electrode 213 is electrically connected to the second connecting electrode 214, and the first substructure 212, the first connecting electrode 213, the second connecting electrode 214, and the second substructure 211 are electrically connected to form an inductor.

[0079] In order to clarify the preparation method in the embodiment of the present disclosure, the preparation method of the substrate integrated with passive devices in the embodiment of the present disclosure is described below with reference to the accompanying drawings and specific embodiments. The specific steps of the preparation method are as follows:

[0080] S11, providing a first glass base 10, attaching the first surface of the first glass base 10 to the first base substrate 1, and processing the first glass base 10 to form a plurality of first connecting vias 11 penetrating along the thickness direction thereof, such as Figure 4 shown.

[0081] In some examples, the first base substrate 1 may be a glass substrate with a thickness of 0.4 mm to 0.5 mm.

[0082] In some examples, step S11 may provide a first glass substrate 10 , modify a first surface of the first glass substrate 10 by laser, and form the first glass substrate 10 having a plurality of first connecting vias 11 by HF etching.

[0083] For example: (1) Cleaning: The first glass substrate 10 is placed into a cleaning machine for cleaning.

[0084] In some examples, the thickness of the first glass substrate 10 is about 0.2 mm to 0.3 mm.

[0085] (2) Laser drilling: A laser is used to vertically incident a laser beam onto the first surface of the first glass substrate 10 to modify the surface, thereby drilling through the first surface of the first glass substrate 10 to form a first connecting via hole 11 .

[0086] Specifically, when the laser beam interacts with the first glass substrate 10, the atoms in the first glass substrate 10 are ionized and ejected out of the first surface of the first glass substrate 10 due to the high energy of the laser photons. As time goes by, the hole drilled gradually deepens until the first connecting via 11 is formed. Among them, the generally available laser wavelength is 532nm, 355nm, 266nm, 248nm, 197nm, etc., the laser pulse width can be 1-100fs, 1-100ps, 1-100ns, etc., and the type of laser can be continuous laser, pulsed laser, etc. The laser drilling method can include but is not limited to the following two methods. The first method is that when the spot diameter is large, the relative position of the laser beam and the first glass substrate 10 is fixed, and the first glass substrate 10 is directly drilled to a preset depth by relying on high energy. At this time, the shape of the first connecting via 11 formed is an inverted frustum, and the diameter of the inverted frustum decreases from top to bottom (from the first surface to the second surface). The second method is that when the spot diameter is small, the laser beam scans in circles on the first glass base 10, the focal point of the spot is constantly changing, and the depth of the focus is also constantly changing. A spiral line is drawn from the lower surface of the first glass base 10 (the second surface) to the upper surface of the first glass base 10 (the first surface), and the spiral radius decreases from bottom to top. The first glass base 10 is laser cut into a truncated cone to form a first connecting via 11. The shape of the first blind hole is the first connecting via 11.

[0087] Of course, the first connecting via 11 in the embodiment of the present disclosure can also be formed by only using a laser beam to irradiate the first surface or the second surface of the first glass base 10 to form a truncated cone or cylindrical connecting via. The formation method can be the same as the above method, so it will not be repeated here.

[0088] (3) HF Etching: During the laser drilling process, a stress zone is formed within a range of approximately 5-20 microns on the upper surface of the inner wall of the first connecting via 11 near the hole. The surface of the first glass substrate 10 in this area is uneven and has many molten burrs, and contains a large number of microcracks and macrocracks, as well as residual stress. At this time, a 2%-20% HF etching solution is used at an appropriate temperature and for a certain period of time to wet-etch the glass in the stress zone, leaving the interior of the first connecting via 11 and the surface area near the hole smooth and flat, without any microcracks or macrocracks, and completely etching away the stress zone.

[0089] S12, forming a first connection electrode 213 located at the first connection via 11, and forming a first substructure 212 of the inductor, such as Figure 5 shown.

[0090] In some examples, step S12 may specifically be as follows:

[0091] (1) Growing a first seed layer: depositing a first metal film layer on the first surface of the first glass substrate 10 by magnetron sputtering, and simultaneously forming a first metal film layer on the sidewall of the first connecting via 11 as a first seed layer.

[0092] In some examples, the material of the first metal film layer includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal film layer is approximately 0.2 μm to 10 μm. The following description uses copper as the material of the first metal film layer as an example.

[0093] In some examples, to enhance adhesion between the first metal material and the first surface of the first glass substrate 10, an auxiliary metal film layer may be formed on the first surface of the first glass substrate 10 by methods including, but not limited to, magnetron sputtering before forming the first metal material. The material of the auxiliary metal film layer includes, but is not limited to, at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is approximately 2 nm to 20 nm.

[0094] (2) Electroplating: Place the first glass substrate 10 on the electroplating machine carrier, press the power pad (pad), and place it in the hole-filling electroplating tank (a special hole-filling electrolyte is used in the tank). Apply current, and the electroplating solution is kept flowing rapidly on the first surface of the first glass substrate 10. The cations in the electroplating solution on the inner wall of the first connecting via 11 obtain electrons and become atoms and deposit on the inner wall. Through the special hole-filling electrolyte with a special ratio, it is possible to achieve high-speed deposition of metal copper (deposition rate 0.5-3um / min) mainly in the first blind hole. The first surface of the first glass substrate 10 is a flat area, and the deposition rate of metal copper on these two surfaces is extremely low (0.005-0.05um / min). As time goes by, the metal copper on the inner wall of the first connecting via 11 gradually grows thicker to form a first metal film layer. At this time, the first metal film layer grows more than 5μm compared to the original first metal film layer. At this time, the first metal film layer covers the first connecting via 11, and even fills the first connecting via 11.

[0095] It should be noted that, in the embodiment of the present disclosure, the first metal film layer is used as an example to fully fill the first connection via hole 11 .

[0096] (3) Patterning of the first metal film layer on the first surface: Glue coating, exposure, and development are performed on the first metal film layer on the first surface, followed by etching. After etching, the strip is removed and the patterning of the first metal film layer is completed. At this time, the first substructure 212 of the inductor coil and the first plate 31 of the capacitor located on the first surface are formed.

[0097] In some examples, the step of forming the first substructure 212 and the first plate 31 of the capacitor further includes grinding the two layers to prevent the first substructure 212 and the first plate 31 of the capacitor from being smooth and to ensure that the thickness meets the capacitor requirements.

[0098] S13, forming a first insulating layer 5 on the side of the first substructure 212 of the inductor away from the first glass substrate 10, and forming a second electrode 32 pattern including a capacitor on the side of the first insulating layer 5 away from the first glass substrate 10, as shown in FIG. Figure 6 shown.

[0099] In some examples, the material of the first insulating layer 5 is an inorganic insulating material. For example, the first insulating layer 5 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked film layer composed of several inorganic insulating layers of SiNx and SiO2. Of course, the first insulating layer 5 also serves as the intermediate dielectric layer of the capacitor.

[0100] In some examples, the second plate 32 of the capacitor can be formed into a second metal film layer on the side of the first insulating layer 5 facing away from the first glass base 10 by magnetron sputtering, and then coated, exposed, developed, and then wet-etched. After etching, the strip is removed to form a pattern including the second plate 32 of the capacitor.

[0101] S14, forming a second insulating layer 6 on the side of the second plate 32 of the capacitor away from the first glass substrate 10, and forming a third connecting via hole penetrating the first insulating layer 5 and the second insulating layer 6, and a fourth connecting via hole penetrating the second insulating layer 6, as shown in FIG. Figure 7 shown.

[0102] The material of the second insulating layer 6 may be the same as that of the first insulating layer 5 , and therefore will not be described again here.

[0103] S15, on the side of the second insulating layer 6 away from the first glass substrate 10, a pattern including the third electrode 7 is formed by a patterning process, and the first end of the first substructure 212 is connected to the second plate of the first capacitor C1 through the third connecting via hole, as shown in FIG. Figure 8 shown.

[0104] In some examples, step S15 may include forming a third metal film layer by magnetron sputtering, applying a resist, exposing, developing, and then performing wet etching. After etching, stripping the resist to form a pattern including the third connection electrode 7. The material of the third metal film layer may be the same as that of the first metal film layer, and therefore will not be described in detail here.

[0105] In some examples, the thickness of the third metal film layer may be greater than 5 μm.

[0106] S16, forming a first isolation layer 8 and a first protective layer 9 in sequence on the side of the third connection electrode 7 away from the first glass substrate 10; and forming a fifth connection via hole penetrating the first isolation layer 8 and the first protective layer 9, such as Figure 9 shown.

[0107] Among them, the first isolation layer 8 is used to prevent water and oxygen from corroding the devices formed on the first surface of the first glass substrate 10. The thickness of the first isolation layer 8 is between 0.1 μm and 2 μm; the material of the first isolation layer 8 can be an inorganic insulating material. For example, the isolation layer can be an inorganic insulating layer formed by silicon nitride (SiNx), or an inorganic insulating layer formed by silicon oxide (SiO2), or a laminated composite film layer of several types of silicon nitride (SiNx) inorganic insulating layers and SiO2 inorganic insulating layers. The thickness of the first protective layer 9 is above 2 μm; the material of the first protective layer 9 can include organic insulating materials, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone and other resin materials. For another example, the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), etc.

[0108] After the first isolation layer 8 and the first protective layer 9 are formed, the first glass base 10 is peeled off from the first base substrate 1 .

[0109] S17, providing a second glass base 20, attaching the third surface of the second glass base 20 to the second base substrate 2, and processing the second glass base 20 to form a plurality of second connecting vias penetrating along the thickness direction thereof.

[0110] In some examples, the second base substrate 2 and the first base substrate 1 may be made of the same material and have the same thickness, which will not be described in detail herein.

[0111] In some examples, the step of forming the second connecting via hole in step S17 may be similar to the step of forming the first connecting via hole 11 in step S11 described above, and thus will not be described in detail herein.

[0112] S18 , forming a second connection electrode 214 located at the second connection via hole, and forming a second substructure 211 of the inductor.

[0113] In some examples, the specific steps of step S18 are: depositing a fourth metal film layer on the fourth surface of the second glass substrate 20 by magnetron sputtering, and forming a fourth metal film layer on the side wall of the second connecting via as a second seed layer; by electroplating, the second seed layer is gradually thickened, and the fourth metal film layer covers the second connecting via, and even fills the second connecting via to form a second connecting electrode 214; coating, exposing, and developing the fourth metal film layer on the fourth surface, and then etching, and stripping the glue after etching, and the patterning of the fourth metal film layer is completed, at this time, the second substructure 211 of the inductor coil located on the fourth surface is formed.

[0114] In some examples, the formation of the second seed layer and the second connection electrode 214 in step S18 may be similar to the formation of the first seed layer and the first connection electrode 213 in step S13 described above, and thus will not be described in detail herein.

[0115] In some examples, the formation of the second substructure 211 in step S18 may be similar to the formation of the first substructure 212 in step S13 described above, and thus will not be described in detail herein.

[0116] S19, forming a third insulating layer 12 and a second protective layer 13 in sequence on the side of the second substructure 211 of the inductor away from the second glass substrate 20, as shown in FIG. Figure 10 The material of the third insulating layer 12 can be the same as that of the first insulating layer 5 , and the material of the second protective layer 13 can be the same as that of the first protective layer 9 , so they will not be described in detail here.

[0117] After the third insulating layer 12 and the second protective layer 13 are formed, the second glass base 20 is peeled off from the second base substrate 2. S20, forming a first adhesive layer 14 on the second surface of the first glass base 10, such as Figure 11 The third surface of the second glass substrate 20 is bonded to the first adhesive layer 14 so that the orthographic projections of the first connecting via 11 and the second connecting via on the first glass substrate 10 at least partially overlap, the first connecting electrode 213 and the second connecting electrode 214 are connected, and the first substructure 212, the first connecting electrode 213, the second connecting electrode 214, and the second substructure 211 form an inductor coil structure.

[0118] It should be noted that, in some examples, steps S11-S16 and steps S17-S20 can be interchanged, that is, each layer structure on the second dielectric layer can be formed first and then each layer structure on the first dielectric layer can be formed.

[0119] At this point, the production of the substrate for integrated passive devices is completed.

[0120] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A method for preparing a substrate integrated with passive devices, comprising: Providing a first dielectric layer and a second dielectric layer, and forming a plurality of first connecting vias on the first dielectric layer, and forming a plurality of second connecting vias on the second dielectric layer; The first dielectric layer includes a first surface and a second surface disposed opposite to each other along the thickness direction; the second dielectric layer includes a third surface and a fourth surface disposed opposite to each other along the thickness direction; The thickness of the first dielectric layer and / or the second dielectric layer is 0.2 mm to 0.3 mm; An integrated passive device, wherein the passive device comprises at least an inductor; the steps of forming the inductor include: forming a first substructure on the first surface of the first dielectric layer, and forming a first connecting electrode in the first connecting via hole; forming a second substructure on the fourth surface of the second dielectric layer, and forming a second connecting electrode in the second connecting via hole; The second surface of the first dielectric layer and the third surface of the second dielectric layer are bonded together, the orthographic projections of one first connecting via and one second connecting via on the first dielectric layer at least partially overlap, one first connecting electrode and one second connecting electrode are electrically connected, and the first substructure, the first connecting electrode, the second connecting electrode, and the second substructure are electrically connected to form the coil structure of the inductor.

2. The preparation method according to claim 1, wherein The steps of forming a plurality of first connecting vias on the first dielectric layer and forming a plurality of second connecting vias on the second dielectric layer include: Cleaning, drilling, and etching the first dielectric layer to form a plurality of first connecting vias penetrating the first dielectric layer in a thickness direction thereof; A plurality of second connecting vias penetrating the second dielectric layer in a thickness direction are formed by cleaning, drilling and etching the second dielectric layer.

3. The preparation method according to claim 1, wherein The steps of forming the first substructure and the first connecting electrode include: attaching the second surface of the first dielectric layer to the first base substrate; forming a first metal film layer on the first connecting via hole and the first surface as a first seed layer; performing an electroplating process on the first seed layer to form the first connecting electrode located in the first connecting via hole and the first metal film layer covering the first surface; performing a patterning process on the first metal film layer to form a pattern including the first substructure; The first base substrate is peeled off from the second surface of the first dielectric layer.

4. The preparation method according to claim 1, wherein The steps of forming the second substructure and forming the second connecting electrode include: attaching the third surface of the second dielectric layer to the second base substrate; forming a fourth metal film layer on the second connecting through hole and the fourth surface as a second seed layer; performing an electroplating process on the second seed layer to form the second connecting electrode located in the second connecting via hole and the second metal film layer covering the fourth surface; performing a patterning process on the fourth metal film layer to form a pattern including the second substructure; The second base substrate is peeled off from the third surface of the second dielectric layer.

5. The preparation method according to claim 1, wherein The step of laminating the first dielectric layer and the second dielectric layer comprises: A first adhesive layer is formed on the second surface of the first dielectric layer or the third surface of the second dielectric layer, and the second surface of the first dielectric layer or the third surface of the second dielectric layer is bonded to the first adhesive layer.

6. The preparation method according to claim 5, wherein The material of the first bonding layer includes anisotropic conductive adhesive.

7. The preparation method according to claim 1, wherein The passive component further includes a capacitor; and the preparation method further includes: Performing a patterning process on the first metal film layer to form a pattern including a first plate of the capacitor on the first surface; forming a first insulating layer on a side of the first electrode plate of the capacitor facing away from the first dielectric layer; Through a patterning process, a pattern including the second plate of the capacitor is formed on a side of the first insulating layer facing away from the first dielectric layer.

8. The preparation method according to claim 7, wherein The steps of forming the first plate of the capacitor include: The first electrode plate of the capacitor and the first substructure are manufactured by a single patterning process.

9. The preparation method according to claim 8, wherein The preparation method further comprises: forming a second insulating layer on a side of the second plate of the capacitor facing away from the first dielectric layer, and forming a third connecting via and a fourth connecting via penetrating the first insulating layer and the second insulating layer; the third connecting via at least partially overlaps with an orthographic projection of the first end of the inductor on the first dielectric layer; The fourth connecting via hole at least partially overlaps with the orthographic projection of the second electrode plate of the capacitor on the first dielectric layer; A third connecting electrode is formed on a side of the second insulating layer away from the first dielectric layer; the first connecting electrode is electrically connected to the first end of the inductor and the second plate of the capacitor through the third connecting via and the fourth connecting via.

10. The preparation method according to claim 9, wherein The preparation method further comprises: forming a first isolation layer and a first protection layer in sequence on a side of the third connection electrode facing away from the first dielectric layer, and forming a fifth connection via hole penetrating the first isolation layer and the first protection layer; A third insulating layer and a second protective layer are sequentially formed on the fourth surface of the second dielectric layer.

11. The preparation method according to claim 1, wherein The first dielectric layer and / or the second dielectric layer includes a glass substrate.

12. A substrate integrated with passive devices, comprising: A first dielectric layer and a second dielectric layer are stacked, and passive components are integrated on the first dielectric layer and the second dielectric layer; wherein, The first dielectric layer includes a first surface and a second surface arranged along the thickness direction thereof; the first dielectric layer is provided with a first connecting via hole penetrating along the thickness direction thereof; The second dielectric layer includes a third surface and a fourth surface arranged along the thickness direction thereof; the second dielectric layer is provided with a second connecting via hole penetrating along the thickness direction thereof; The passive component includes at least an inductor; the inductor includes a first substructure arranged on the first surface and a second substructure arranged on the fourth surface, as well as a first connecting electrode arranged in the first connecting via and a second connecting electrode arranged in the second connecting via; the orthographic projections of one first connecting via and one second connecting via on the first dielectric layer at least partially overlap, one first connecting electrode is electrically connected to one second connecting electrode, and the first substructure, the first connecting electrode, the second connecting electrode and the second substructure are electrically connected to form the coil structure of the inductor.

13. The substrate according to claim 12, wherein The first dielectric layer and / or the second dielectric layer includes a glass substrate.

14. The substrate according to claim 12, wherein The thickness of the first dielectric layer and / or the second dielectric layer is 0.2 mm to 0.3 mm.

15. The substrate according to claim 12, wherein The passive component further includes a capacitor; wherein the first plate of the capacitor is arranged in the same layer as the first substructure of the inductor; the substrate further includes a first insulating layer located on the side of the first plate of the capacitor facing away from the first dielectric layer; the second plate of the capacitor is located on the side facing away from the first insulating layer, and the second plate of the capacitor at least partially overlaps with the orthographic projection of the first plate on the first surface of the first dielectric layer.

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