A GeSe-based double-heterojunction CMOS type photoelectric detector and a manufacturing method thereof

Abstract

The application relates to the technical field of microelectronics and optoelectronics, and particularly relates to a GeSe-based double-heterojunction CMOS type photoelectric detector and a manufacturing method, which comprises a first gate, a second gate, an insulating layer, a first source, a second source, a first P-type GeSe semiconductor active layer, a first N-type semiconductor photosensitive layer, a second N-type semiconductor photosensitive layer, a second P-type GeSe semiconductor active layer, a first drain and a second drain, a PN heterojunction is formed by contact of the P-type semiconductor active layer and the N-type semiconductor photosensitive layer, the source and the drain are respectively located on two sides of the PN heterojunction, and the first drain is connected with the second drain. The application novelly proposes a CMOS inverter with a double heterojunction constructed by taking GeSe as a p-type active layer material, and three corresponding examples are given. The inverter has excellent working performance, high carrier mobility, high detection rate and high light response rate, and can realize controllable gate voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microelectronics and optoelectronics, and particularly relates to a GeSe-based double-heterojunction CMOS type photoelectric detector and a manufacturing method. BACKGROUND

[0002] Generally, a CMOS inverter needs to have a bipolar characteristic thin film transistor (one N-type thin film transistor and one P-type thin film transistor), and the two transistor drain electrodes are connected and controlled by the same gate electrode.

[0003] At present, most of the CMOS inverters are realized by using the same semiconductor material as the active layer to realize the bipolar characteristic, for example, for a semiconductor material, different types of carrier transport can be formed by using the different work functions of the asymmetric source / drain electrode metal materials; bipolar transistors can also be formed by the attraction and repulsion of different adjacent layers to the carriers of the active layer to prepare CMOS inverters, such as the patent CN110707042A mentioned above, which uses the increase of electron-philic / donating blocking layers on CNT (carbon nanotube) to form a transistor with bipolar characteristics, but it has the performance defects of small carrier mobility and low photoelectric response rate, and the difficulty of CNT (carbon nanotube) chirality control is large, causing the manufacturing process to be complex.

[0004] The compound semiconductor materials commonly used for preparing TFTs (thin film transistors) are mostly electron-conducting (n-type), and the hole-conducting (p-type) materials matching the performance of n-type are extremely rare. The p-type semiconductor materials commonly used at present include graphene, CNT (carbon nanotube), WSe2, BP and some organic materials through a doping process. The two-dimensional nanomaterials represented by graphene have excellent optical and electrical properties, and the carrier mobility at room temperature can reach 104, but graphene lacks intrinsic band gap, which is not conducive to the construction of photoelectronic devices with high detection efficiency, large on-off ratio and low power consumption; black phosphorus has high carrier mobility and suitable band gap, but black phosphorus is easily oxidized in air. Although most organic semiconductors exhibit p-type conduction, the hole mobility of organic TFTs is low, and the device life, uniformity between devices and stability of the device in an oxygen atmosphere and humid environment are poor, and the processability of organic materials is also poor. Among a series of p-type semiconductor materials, GeSe is theoretically considered to be the only material with a direct band gap, and has high carrier mobility and high stability. These characteristics make GeSe the most promising candidate material in the field of infrared spectral detection. However, since the band gap of GeSe is 1.1-1.2 eV, they usually have excellent photosensitive properties in the visible band and lack sufficient response in the infrared region, so the patent novelly proposes to construct a CMOS inverter with a heterojunction using GeSe as a p-type active layer semiconductor material, so that the inverter has excellent performance in the infrared band. In addition, the inverter based on the heterojunction structure greatly improves the carrier mobility, has high detection rate and high response rate, and the process is relatively simple and the cost is low, which has great potential in infrared light detection and driving. SUMMARY

[0005] In view of the deficiencies mentioned in the above technical background, the purpose of the present application is to provide a GeSe-based double-heterojunction CMOS photoelectric detector and a manufacturing method.

[0006] The purpose of the present application can be achieved by the following technical solutions.

[0007] A photoelectric inverter, comprising a first gate, a second gate, an insulating layer, a first source, a second source, a first P-type GeSe semiconductor active layer, a first N-type semiconductor photosensitive layer, a second N-type semiconductor photosensitive layer, a second P-type GeSe semiconductor active layer, a first drain, a second drain, characterized in that the PN heterojunction is formed by the contact of the P-type semiconductor active layer and the N-type semiconductor photosensitive layer, the source and the drain are located on the two sides of the PN heterojunction respectively, and the first drain and the second drain are connected.

[0008] Furthermore, if the first gate electrode is adjacent to the P-type semiconductor active layer of the PN heterojunction, then together with the first source, the first drain, and the PN heterojunction, it constitutes an NMOS phototransistor. If the second gate electrode is adjacent to the N-type semiconductor photosensitive layer of the PN heterojunction, then together with the second source, the second drain, and the PN heterojunction, it constitutes a PMOS phototransistor. The PMOS phototransistor and the NMOS phototransistor together constitute a CMOS phototransistor inverter.

[0009] Furthermore, the gate electrode can be located at the top as a top gate or at the bottom as a bottom gate.

[0010] Furthermore, the P-type semiconductor active layer is made of GeSe two-dimensional nanomaterial, and the N-type semiconductor photosensitive layer is made of PbSe, PbS, PbO, IGZO, MoS2, CdSe, ZnO, SnO, In2O3, InZnO, or IGO.

[0011] Furthermore, the insulating layer is located between the gate and the adjacent source (drain) electrodes of the two PN heterojunctions. The insulating layer can be a solid insulating layer made of silicon dioxide, silicon nitride, aluminum oxide, etc., using chemical vapor deposition, atomic layer deposition or magnetron sputtering, or an organic gate insulating layer made of PMMA, Su8 or other sol-gels using spin coating, printing or dispensing methods.

[0012] Furthermore, the substrate material is silicon wafer, glass, quartz, ceramic, plastic, polyimide, or polyethylene terephthalate.

[0013] Furthermore, the aforementioned CMOS photodetector includes a double PN heterojunction photoinverter.

[0014] A method for manufacturing a photoelectric inverter, the method of using the inverter includes the following steps:

[0015] Step 1: Select a suitable substrate and fabricate the first gate electrode and the second gate electrode on the substrate, and connect the two gate electrodes together;

[0016] Step 2: Cover the two gate electrodes with an insulating layer;

[0017] Step 3: Fabricate the first source electrode and the second source electrode on the insulating layer;

[0018] Step 4: Fabricate the first P-type semiconductor active layer, pattern the two-dimensional nanomaterial GeSe of the active layer, and position and distribute it at the location;

[0019] Step 5: Fabricate the second N-type semiconductor photosensitive layer, pattern the photosensitive layer material, and position and distribute it at the location;

[0020] Step 6: Form a first semiconductor photosensitive layer on the first semiconductor active layer;

[0021] Step 7: Form a first semiconductor active layer on the second semiconductor photosensitive layer;

[0022] Step 8: Form a first drain electrode that contacts the first semiconductor photosensitive layer and a second drain electrode that contacts the second semiconductor active layer, and connect the first drain electrode and the second drain electrode.

[0023] Furthermore, the semiconductor material layer is uniformly distributed on the entire device using a spin coating process, and then the semiconductor material in non-required areas is removed by an etching process, or magnetron sputtering is performed using a mask, or ink is applied using a corresponding material for targeted ink-splash printing, or photolithography is used to fabricate the material layer.

[0024] Furthermore, the gate electrode and source / drain electrode are formed on the substrate by methods such as silver ion inkjet printing or laser etching.

[0025] Furthermore, Comparative column 2 includes a first source, a first P-type GeSe semiconductor active layer, a first N-type semiconductor photosensitive layer, a first drain, an insulating layer, a gate, an insulating layer, a second source, a second P-type GeSe semiconductor active layer, a second N-type semiconductor photosensitive layer, and a second drain;

[0026] Furthermore, the first gate electrode is connected to the second gate electrode, or the NOMS phototransistor and the PMOS phototransistor share a single gate electrode.

[0027] The beneficial effects of this invention are:

[0028] This invention novelly proposes a CMOS inverter with a double heterojunction constructed using GeSe as the p-type active layer material, and provides three corresponding examples. The inverter exhibits excellent performance, with high carrier mobility, high detectivity, and high photoresponse, and allows for controllable gate voltage.

[0029] Example A employs a bottom-gate structure. Compared to Comparative Example 1, where the gate and insulating layer are located on top, the semiconductor photosensitive layer (semiconductor active layer) is directly deposited on the insulating layer. During fabrication, the insulating layer can be modified to alter the semiconductor film structure and morphology, resulting in a high-quality semiconductor layer and thus improving the device's carrier mobility. Furthermore, in Example A, the semiconductor layer is exposed to the testing environment without any covering, leading to higher detectivity and photoresponse of the fabricated device. Comparative Example 1, with its multilayer structure, has a complex fabrication process, requiring advanced experimental equipment and advanced technology, making it difficult to implement. Based on the above analysis, the bottom-gate structure in Example A offers significant advantages.

[0030] A CMOS inverter with a double heterojunction, constructed using GeSe as the p-type active layer material based on the bottom-gate structure in Example A, exhibits high carrier mobility (hole mobility approximately 1 cm² / vs), high detectivity (5.8 × 10¹⁴ Jones), and high photoresponse (1.2 × 10⁶ V / W), enabling controllable gate voltage. Furthermore, the gate voltage can amplify and stabilize the photocurrent with extreme rise times (0.1 ms) and fall times (0.3 ms). Through the IV conversion function of the CMOS inverter, the photocurrent is directly converted into a photovoltage signal and output to the back-end signal acquisition circuit. In addition, the process of this patent is relatively simple and low-cost, showing great potential in infrared light detection and driving. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the CMOS inverter example A of the dual heterostructure optical transistor of the present invention;

[0033] Figure 2 This is a schematic diagram of the CMOS inverter example B of the dual heterostructure optical transistor of the present invention;

[0034] Figure 3 This is a schematic diagram of the CMOS inverter example C of the dual heterostructure optical transistor of the present invention;

[0035] Figure 4 This is a scanning electron microscope (SEM) characterization image of the p-type GeSe active layer material;

[0036] Figure 5 The photoresponse of the CMOS inverter of the dual heterostructure phototransistor of the present invention is shown under different incident light wavelengths.

[0037] Appendix Figure 1 Labels: A1 - substrate, A21 - first gate electrode, A22 - second gate electrode, A3 - insulating layer, A41 - first source, A42 - second source, A51 - first P-type GeSe semiconductor active layer, A61 - first N-type semiconductor photosensitive layer, A52 - second N-type semiconductor photosensitive layer, A62 - second P-type GeSe semiconductor active layer, A71 - first drain, A72 - second drain.

[0038] Appendix Figure 2Labels: B1 - substrate, B21 - first drain, B22 - second drain, B31 - first P-type GeSe semiconductor active layer, B41 - first N-type semiconductor photosensitive layer, B32 - second N-type semiconductor photosensitive layer, B42 - second P-type GeSe semiconductor active layer, B51 - first source, B52 - second source, B6 - insulating layer, B71 - first gate electrode, B72 - second gate electrode.

[0039] Appendix Figure 3 Labels: C1 - substrate, C2 - first source, C3 - first P-type GeSe semiconductor active layer, C4 - first N-type semiconductor photosensitive layer, C5 - first drain, C6 - insulating layer, C7 - gate, C8 - insulating layer, C9 - second source, C10 - second P-type GeSe semiconductor active layer, C11 - second N-type semiconductor photosensitive layer, C12 - second drain. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] In the description of this invention, it should be understood that the terms "opening", "upper", "lower", "thickness", "top", "middle", "length", "inner", "around", etc., which indicate orientation or positional relationship, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this invention.

[0042] Example A: This example provides a structural design and fabrication method for a double heterostructure optoelectronic CMOS inverter with the gate on the bottom side. A first gate electrode A21 and a second gate electrode A22 (the two gate electrodes are connected), an insulating layer A3, a first source electrode A41, a second source electrode A42, a first P-type GeSe semiconductor active layer A51, a first N-type semiconductor photosensitive layer A61, a second N-type semiconductor photosensitive layer A52, a second P-type GeSe semiconductor active layer A62, a first drain electrode A71, and a second drain electrode A72 (the two drain electrodes are connected) are formed on a substrate A1.

[0043] The specific fabrication method of the above-mentioned bottom-gate dual heterostructure optoelectronic CMOS inverter includes the following steps:

[0044] Step AS1: Select a suitable substrate and fabricate a first gate electrode A21 and a second gate electrode A22 on the substrate, and connect the two gate electrodes together;

[0045] Step AS2: Cover the two gate electrodes A21 and A22 with an insulating layer A3;

[0046] Step AS3: Fabricate the first source electrode A41 and the second source electrode A42 on the insulating layer A3;

[0047] Step AS4: Fabricate the first P-type semiconductor active layer, pattern the two-dimensional nanomaterial GeSe of the active layer, and position it at A51;

[0048] Step AS5: Fabricate the second N-type semiconductor photosensitive layer, pattern the photosensitive layer material, and position and distribute it at A52;

[0049] Step AS6: A first semiconductor photosensitive layer A61 is formed on the first semiconductor active layer A51;

[0050] Step AS7: A first semiconductor active layer A62 is formed on the second semiconductor photosensitive layer A52;

[0051] Step AS8: Form a first drain A71 that contacts the first semiconductor photosensitive layer and a second drain A72 that contacts the second semiconductor active layer, and connect the first drain to the second drain.

[0052] Working principle: The substrate A1 material should be an insulating material, such as silicon wafer, glass, quartz, ceramic, plastic, polyimide, polyethylene terephthalate, etc. Gate electrodes A21, A22 and source / drain electrodes A41, A42, A71, A72 can be formed on the substrate by methods such as silver ion inkjet printing or laser etching; insulating layer A3 can be a solid insulating layer such as silicon dioxide, silicon nitride, or aluminum oxide, formed by chemical vapor deposition, atomic layer deposition, or magnetron sputtering, or it can be an organic gate insulating layer such as PMMA or Su8 sol-gel manufactured by spin coating, printing, or dispensing methods; the first P-type semiconductor active layer A51 and the second P-type semiconductor active layer A62 can be selected from the P-type two-dimensional nanomaterial GeSe; the first N-type semiconductor photosensitive layer A61 and the second N-type semiconductor photosensitive layer A52 can be selected from PbSe, PbS, PbO, IGZO, MoS2, CdSe, ZnO, SnO, In2O3, InZnO, IGO, etc. as photosensitive semiconductor materials. Fabricating the A51, A52, A61, and A62 material layers can be achieved by spin-coating to uniformly distribute the semiconductor material across the entire device, followed by etching to remove the semiconductor material from undesirable areas. Alternatively, magnetron sputtering using a mask or targeted inkjet printing or photolithography can be employed. If the material layers of the first and second transistors are swapped—that is, the order of A51 and A61, and the order of A52 and A62 are interchanged top to bottom (equivalent to swapping the positions of the left and right MOS transistors)—this also falls within the scope of this example.

[0053] Comparative Example 1: This example provides a structural design and fabrication method of a double heterostructure optoelectronic CMOS inverter with the gate on the top side. A first drain B21 and a second drain B22 (the two drain electrodes are connected), a first P-type GeSe semiconductor active layer B31, a first N-type semiconductor photosensitive layer B41, a second N-type semiconductor photosensitive layer B32, a second P-type GeSe semiconductor active layer B42, a first source B51, a second source B52, an insulating layer B6, a first gate electrode B71, and a second gate electrode B72 (the two gate electrodes are connected) are formed on a substrate B1.

[0054] The fabrication of the above-mentioned top-gate dual heterostructure optoelectronic CMOS inverter includes the following steps:

[0055] Step BS1: Select a suitable substrate and fabricate a first drain electrode B21 and a second drain electrode B22 on the substrate, and connect the two drain electrodes together.

[0056] Step BS2: Fabricate the first P-type semiconductor active layer, pattern the two-dimensional nanomaterial GeSe of the active layer, and position it at B31;

[0057] Step BS3: Fabricate the second N-type semiconductor photosensitive layer, pattern the photosensitive layer material, and position and distribute it at B41;

[0058] Step BS4: A first semiconductor photosensitive layer B41 is formed on the first semiconductor active layer B31;

[0059] Step BS5: A first semiconductor active layer B42 is formed on the second semiconductor photosensitive layer B32;

[0060] Step BS6: Form a first source electrode B51 that is in contact with the first semiconductor photosensitive layer and a second source electrode B52 that is in contact with the second semiconductor active layer.

[0061] Step BS7: Cover the two source electrodes B51 and B52 with an insulating layer B6;

[0062] Step BS8: Fabricate a first gate electrode B71 and a second gate electrode B72 on the insulating layer B6, and connect the two gate electrodes together.

[0063] Working principle: The substrate B1 material should be an insulating material, which can be silicon wafer, glass, quartz, ceramic, plastic, polyimide, polyethylene terephthalate, etc. Drain electrodes B21 and B22, source electrodes B51 and B52, and gate electrodes B71 and B72 can be formed on the substrate by methods such as silver ion inkjet printing or laser etching; the insulating layer B6 can be a solid insulating layer such as silicon dioxide, silicon nitride, or aluminum oxide, formed by chemical vapor deposition, atomic layer deposition, or magnetron sputtering, or it can be an organic gate insulating layer of PMMA, Su8, or other sol-gels manufactured by spin coating, printing, or dispensing methods; the first P-type semiconductor active layer B31 and the second P-type semiconductor active layer B42 can be selected from the P-type two-dimensional nanomaterial GeSe; the first N-type semiconductor photosensitive layer B41 and the second N-type semiconductor photosensitive layer B32 can be selected from PbSe, PbS, PbO, IGZO, MoS2, CdSe, ZnO, SnO, In2O3, InZnO, IGO, etc. as photosensitive semiconductor materials. Fabricating the B31, B32, B41, and B42 material layers can be achieved by spin-coating to uniformly distribute the semiconductor material across the entire device, followed by etching to remove the semiconductor material from undesirable areas. Alternatively, magnetron sputtering using a mask or targeted inkjet printing or photolithography can be employed. Swapping the material layers of the first and second transistors—that is, reversing the order of B31 and B41, and B32 and B42 (equivalent to swapping the positions of the left and right MOSFETs)—also falls within the scope of this example.

[0064] Comparative Example 2: This example provides a structural design and fabrication method of a dual heterostructure optoelectronic CMOS inverter with the gate in the middle. A first source C2, a first P-type GeSe semiconductor active layer C3, a first N-type semiconductor photosensitive layer C4, a first drain C5, an insulating layer C6, a gate C7, an insulating layer C8, a second source C9, a second P-type GeSe semiconductor active layer C10, a second N-type semiconductor photosensitive layer C11, and a second drain C12 (the two drain electrodes C5 and C12 are connected) are formed on a substrate C1.

[0065] The fabrication of the aforementioned double heterostructure photoelectric CMOS inverter with the gate in the middle includes the following steps:

[0066] Step CS1: Select a suitable substrate C1 and fabricate the first source C2 on the substrate;

[0067] Step CS2: Fabricate the first P-type GeSe semiconductor active layer and position it at C3;

[0068] Step CS3: Fabricate the first N-type semiconductor photosensitive layer and position it at C4;

[0069] Step CS4: Form the first drain C5 that contacts the first N-type semiconductor photosensitive layer;

[0070] Step CS5: Completely cover the first drain C5 with the insulating layer C6;

[0071] Step CS6: Fabricate the gate electrode C7 on the insulating layer C6;

[0072] Step CS7: Cover the gate electrode C7 with an insulating layer C8;

[0073] Step CS8: Fabricate the second source electrode C9 on the insulating layer c8;

[0074] Step CS9: Fabricate the second P-type GeSe semiconductor active layer and position it at C10;

[0075] Step CS10: Fabricate the second N-type semiconductor photosensitive layer and position it at C11;

[0076] Step CS11: A drain electrode C12 is formed on the second N-type semiconductor photosensitive layer, and C5 is connected to C12.

[0077] Working principle: The substrate C1 material should be an insulating material, which can be silicon wafer, glass, quartz, ceramic, plastic, polyimide, polyethylene terephthalate, etc. Drain electrodes C5 and C12, source electrodes C2 and C9, and gate electrode C7 can be formed on the substrate by methods such as silver ion inkjet printing or laser etching; insulating layers C6 and C8 can be solid insulating layers such as silicon dioxide, silicon nitride, and aluminum oxide, which are formed by chemical vapor deposition, atomic layer deposition, or magnetron sputtering, or organic gate insulating layers such as PMMA and Su8 sol-gels manufactured by spin coating, printing, or dispensing methods; the first P-type semiconductor active layer C3 and the second P-type semiconductor active layer C10 can be made of P-type two-dimensional nanomaterial GeSe; the first N-type semiconductor photosensitive layer C4 and the second N-type semiconductor photosensitive layer C11 can be made of PbSe, PbS, PbO, IGZO, MoS2, CdSe, ZnO, SnO, In2O3, InZnO, IGO, etc. as photosensitive semiconductor materials. Fabricating the C3, C4, C10, and C11 material layers can be achieved by spin-coating to uniformly distribute the semiconductor material across the entire device, followed by etching to remove the semiconductor material from undesirable areas. Alternatively, magnetron sputtering using a mask or targeted inkjet printing or photolithography can be employed. If the material layers of the first and second transistors are swapped, and the order of C3 and C4, and C10 and C11 are interchanged (equivalent to swapping the positions of the two MOS transistors), this also falls within the scope of this example.

[0078] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A photoelectric inverter, comprising a substrate (A1), a first gate electrode (A21), a second gate electrode (A22), an insulating layer (A3), a first source electrode (A41), a second source electrode (A42), a first P-type semiconductor active layer (A51), a first N-type semiconductor photosensitive layer (A61), a second N-type semiconductor photosensitive layer (A52), a second P-type semiconductor active layer (A62), a first drain electrode (A71), and a second drain electrode (A72), characterized in that, The first PN heterojunction is formed by contacting a first P-type semiconductor active layer (A51) and a first N-type semiconductor photosensitive layer (A61), wherein the first P-type semiconductor active layer (A51) contacts the first N-type semiconductor photosensitive layer (A61), and the first N-type semiconductor photosensitive layer (A61) contacts the first drain (A71); the second PN heterojunction is formed by contacting a second N-type semiconductor photosensitive layer (A52) and a second P-type semiconductor active layer (A62), wherein the second N-type semiconductor photosensitive layer (A52) contacts the second P-type semiconductor active layer (A62), and the second P-type semiconductor active layer (A62) contacts the second drain (A72); The first source (A41) and the first drain (A71) are located on the upper and lower sides of the first PN heterojunction in the vertical direction, and on the left and right sides of the first PN heterojunction in the horizontal direction, respectively; the second source (A42) and the second drain (A72) are located on the upper and lower sides of the second PN heterojunction in the vertical direction, and on the left and right sides of the second PN heterojunction in the horizontal direction, respectively, and the first drain (A71) and the second drain (A72) are connected. The first gate electrode is adjacent to the first P-type semiconductor active layer of the first PN heterojunction, and together with the first source, the first drain, and the first PN heterojunction, they form an NMOS phototransistor. The second gate electrode is adjacent to the second N-type semiconductor photosensitive layer of the second PN heterojunction, and together with the second source, the second drain, and the second PN heterojunction, they form a PMOS phototransistor. The PMOS phototransistor and the NMOS phototransistor together form a CMOS phototransistor inverter. The gate electrode is located at the top as a top gate or at the bottom as a bottom gate.

2. The photoelectric inverter according to claim 1, characterized in that, The P-type semiconductor active layer is made of GeSe two-dimensional nanomaterial, and the N-type semiconductor photosensitive layer is made of one or more of PbSe, PbS, PbO, IGZO, MoS2, CdSe, ZnO, SnO, In2O3, InZnO, and IGO.

3. The photoelectric inverter according to claim 1, characterized in that, The insulating layer is located between the gate and the adjacent drain electrode connecting the two PN heterojunctions. The insulating layer is a solid insulating layer or an organic gate insulating layer. The solid insulating layer is manufactured by chemical vapor deposition, atomic layer deposition or magnetron sputtering of one or more of silicon dioxide, silicon nitride and aluminum oxide. The organic gate insulating layer is manufactured by spin coating, printing or dispensing methods of one or more of PMMA and Su8 sol-gel.

4. The photoelectric inverter according to claim 1, characterized in that, The substrate material is silicon wafer, glass, quartz, ceramic, plastic, polyimide, or polyethylene terephthalate.

5. A CMOS photodetector, comprising a photoelectric inverter as described in any one of 1-4.

6. A method for manufacturing a photoelectric inverter according to any one of claims 1-4, characterized in that, The manufacturing method includes the following steps: Step 1: Select a suitable substrate and fabricate a first gate electrode (A21) and a second gate electrode (A22) on the substrate, and connect the two gate electrodes together; Step 2: Cover the two gate electrodes (A21) and (A22) with an insulating layer (A3); Step 3: Fabricate the first source electrode (A41) and the second source electrode (A42) on the insulating layer (A3); Step 4: Fabricate the first P-type semiconductor active layer, pattern the two-dimensional nanomaterial GeSe of the active layer, and position and distribute it at the first semiconductor active layer (A51); Step 5: Fabricate the second N-type semiconductor photosensitive layer, pattern the photosensitive layer material, and position and distribute it at the second semiconductor photosensitive layer (A52); Step 6: Form a first semiconductor photosensitive layer (A61) on the first semiconductor active layer (A51); Step 7: Form a second semiconductor active layer (A62) on the second semiconductor photosensitive layer (A52); Step 8: Form a first drain (A71) in contact with the first semiconductor photosensitive layer and a second drain (A72) in contact with the second semiconductor active layer, and connect the first drain to the second drain.

7. A method for manufacturing a photoelectric inverter according to claim 6, characterized in that, The first semiconductor active layer, the second semiconductor photosensitive layer, and the second semiconductor active layer are fabricated by using a spin coating process to uniformly distribute semiconductor material on the entire device, followed by an etching process to remove semiconductor material from non-required areas, or by using a mask for magnetron sputtering, or by using ink-splashing of corresponding materials for positioning, or by photolithography.

8. A method for manufacturing a photoelectric inverter according to claim 6, characterized in that, The gate electrode and source / drain electrode are formed on the substrate by methods such as silver ion inkjet printing or laser etching.

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