An enhanced gallium nitride heterojunction field effect transistor

Abstract

The present invention relates to the field of microelectronics technology. Specifically, it relates to an enhanced gallium nitride heterojunction field effect transistor. A connection unit is provided between the gate and the barrier layer. The connection unit includes a first gallium nitride layer, a second gallium nitride layer, a third gallium nitride layer, and a fourth gallium nitride layer. The first gallium nitride layer to the fourth gallium nitride layer are arranged in sequence from top to bottom. The first gallium nitride layer is connected to the gate, and the fourth gallium nitride layer is connected to the barrier layer. When the device has a positive gate breakdown voltage, the n-i-p diode formed by the first gallium nitride layer, the second gallium nitride layer, and the third gallium nitride layer is reverse-biased. At this time, the peak value of the electric field is distributed in the second gallium nitride layer. Since the breakdown voltage of the p-i-n diode formed by the third gallium nitride layer, the fourth gallium nitride layer, and the barrier layer is also higher than that of the PN junction diode, the device structure simultaneously has a higher reverse gate breakdown voltage.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and more particularly, to an enhanced gallium nitride heterojunction field effect transistor. Background Art

[0002] With the development of technology and the progress of human society, there is an increasing demand for faster, more energy-efficient, and more portable electronic devices. However, traditional silicon (Si)-based semiconductor devices are difficult to break through the limitations of their materials to meet these demands. To make a breakthrough, the scientific community and the industry have begun to explore and develop new semiconductor materials. Gallium nitride (GaN), as a representative of the third-generation semiconductor materials, has gradually come into people's view. It is found that gallium nitride materials have significant advantages such as high bandgap width, high electron mobility, high critical breakdown electric field strength, high thermal conductivity, and high electron saturation velocity, making them perfect substitutes for traditional semiconductor materials such as silicon and gallium arsenide. The gallium nitride heterojunction field effect transistor (GaN HFET) based on gallium nitride epitaxial materials has excellent characteristics such as higher breakdown voltage, lower on-resistance, higher current density, and higher switching speed compared to traditional Si devices, and can easily break through the performance limits of Si devices. The significant advantages of GaN HFET over Si MOSFET and IGBT have enabled it to gradually replace Si devices in high-voltage, high-current, and high-frequency application fields and expand its application areas.

[0003] The core structure of GaN HFET is the AlGaN / GaN heterojunction. Due to the spontaneous polarization and piezoelectric polarization effects, a two-dimensional electron gas (2DEG) with high concentration and high electron mobility will be naturally formed at the AlGaN / GaN heterojunction interface. Therefore, conventional GaN HFETs are depletion-mode devices. The turn-off of depletion-mode devices requires a negative gate voltage, so the drive design of depletion-mode devices is relatively complex and prone to false turn-on. To solve this problem, an enhanced structure is required for practical applications of GaN HFET. To achieve the enhanced structure, it is necessary to deplete the 2DEG in the channel under the gate at 0 bias voltage. Enhanced implementation schemes such as F ion implantation, trench gate structure, ultra-thin barrier layer, Fin structure, and p-type gate structure have been reported successively. Due to the relatively stable threshold voltage, the p-type gate structure has become the current mainstream enhanced scheme. However, there is still a large room for optimization in the gate breakdown voltage and gate reliability of the p-type gate structure.

[0004] The p-type gate GaN HFET gate structure consists of two back-to-back diodes, namely, the Schottky diode formed by the gate and p-GaN, and the PN junction diode formed by p-GaN and AlGaN. When the gate is forward-biased for voltage withstand, the Schottky junction diode is reverse-biased and the PN junction diode is forward-biased. At this time, the voltage withstand is mainly provided by the Schottky junction. When the gate is reverse-biased for voltage withstand, the Schottky diode is forward-biased and the PN junction diode is reverse-biased. At this time, the voltage withstand is mainly provided by the PN junction. Since the voltage withstand of the Schottky junction is only borne by the depletion region of p-GaN on one side, while the voltage withstand of the PN junction is borne by the p-type region and the n-type region, the breakdown voltage of the Schottky junction is generally lower than that of the PN junction. Therefore, the forward gate breakdown voltage of the p-type gate GaN HFET is lower than the reverse breakdown voltage. To increase the forward gate breakdown voltage, a conventional and practical solution is to reduce the doping concentration of p-GaN, thereby expanding the depletion region width of the Schottky junction. However, reducing the doping concentration of p-GaN will lead to a decrease in the threshold voltage of the device. Another solution that can theoretically increase the gate breakdown voltage is to increase the thickness of p-GaN. In fact, due to the relatively high doping concentration of p-GaN, increasing the thickness of p-GaN cannot significantly increase the depletion region width of the Schottky junction. Therefore, a new device structure is proposed to increase the gate breakdown voltage and reliability of the p-type gate GaN HFET. Summary of the Invention

[0005] The object of the present invention is to modulate the electric field distribution in the gate region when the gate is forward-biased and reverse-biased for voltage withstand, so that the vertical electric field distribution in the gate region is more uniform, thereby increasing the gate breakdown voltage and reliability of the device. The present invention proposes an enhancement-mode gallium nitride heterojunction field effect transistor.

[0006] The embodiments of the present invention are implemented through the following technical solutions:

[0007] An enhancement-mode gallium nitride heterojunction field effect transistor includes a substrate, a nucleation layer, a buffer layer, and a barrier layer sequentially arranged from bottom to top. An anode, a drain, and a gate are respectively arranged above the barrier layer. A connection unit is arranged between the gate and the barrier layer. The connection unit includes a first gallium nitride layer, a second gallium nitride layer, a third gallium nitride layer, and a fourth gallium nitride layer. The first gallium nitride layer to the fourth gallium nitride layer are sequentially arranged from top to bottom. The first gallium nitride layer is connected to the gate, and the fourth gallium nitride layer is connected to the barrier layer.

[0008] In an embodiment of the present invention, the first gallium nitride layer is an n-type doped gallium nitride layer, the third gallium nitride layer is a p-type doped gallium nitride layer, and the second gallium nitride layer and the fourth gallium nitride layer are unintentionally doped gallium nitride layers.

[0009] In an embodiment of the present invention, the doping concentration of the first gallium nitride layer is 1e16 cm -3 ~1e20 cm -3, the doping concentration of the third gallium nitride layer is 1e19 cm -3 ~3e19 cm -3 .

[0010] In an embodiment of the present invention, the thickness of the first gallium nitride layer is 10 - 20 nm, the thickness of the third gallium nitride layer is 50 - 100 nm, and the thicknesses of the second gallium nitride layer and the fourth gallium nitride layer are 1 - 10 nm.

[0011] In an embodiment of the present invention, the source electrode and the drain electrode form an ohmic contact with the barrier layer.

[0012] In an embodiment of the present invention, the gate electrode forms a Schottky contact with the first gallium nitride layer.

[0013] In an embodiment of the present invention, the thickness of the substrate is 0.3 - 1 mm.

[0014] The technical solution of the embodiment of the present invention has at least the following advantages and beneficial effects:

[0015] When the device is forward-biased with respect to the gate voltage, the n-i-p diode composed of the first gallium nitride layer, the second gallium nitride layer, and the third gallium nitride layer is reverse-biased, and at this time, the peak electric field is distributed in the second gallium nitride layer. Compared with the traditional P-type gate GaN HEFT, the reverse-biased n-i-p diode has a higher breakdown voltage than the reverse-biased Schottky diode. This structure shifts the peak electric field to the second gallium nitride layer instead of the Schottky interface of the traditional device, avoiding the premature breakdown of the device caused by the interface states generated during surface cleaning and gate metal deposition. In addition, since the breakdown voltage of the p-i-n diode composed of the third gallium nitride layer, the fourth gallium nitride layer, and the barrier layer is also higher than that of the PN junction diode, the device structure also has a higher reverse gate breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following will briefly introduce the drawings required to be used in the embodiment. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic structural diagram of an enhancement-mode gallium nitride heterojunction field-effect transistor of the present invention;

[0018] Reference numerals: 101 - substrate, 102 - nucleation layer, 103 - buffer layer, 104 - barrier layer, 105 - source electrode, 106 - fourth gallium nitride layer, 107 - third gallium nitride layer, 108 - second gallium nitride layer, 109 - first gallium nitride layer, 110 - gate electrode, 111 - drain electrode. Detailed implementation manners

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the drawings here may be arranged and designed in various different configurations.

[0020] Please refer to Figure 1 , a kind of enhanced gallium nitride heterojunction field effect transistor provided by the present invention includes a substrate 101, a nucleation layer 102, a buffer layer 103 and a barrier layer 104 which are sequentially arranged from bottom to top. An anode 105, a drain 111 and a gate 110 are respectively arranged above the barrier layer 104. A connection unit is arranged between the gate 110 and the barrier layer 104. The connection unit includes a first gallium nitride layer 109, a second gallium nitride layer 108, a third gallium nitride layer 107 and a fourth gallium nitride layer 106. The first gallium nitride layer 109 to the fourth gallium nitride layer 106 are sequentially arranged from top to bottom. The first gallium nitride layer 109 is connected to the gate 110, and the fourth gallium nitride layer 106 is connected to the barrier layer 104.

[0021] In addition, in an embodiment of the present invention, the anode 105 and the drain 111 form an ohmic contact with the barrier layer 104, the gate 110 forms a Schottky contact with the first gallium nitride layer 109, the nucleation layer 102 is an aluminum nitride nucleation layer 102, the buffer layer 103 is a gallium nitride buffer layer 103, and the barrier layer 104 is an aluminum gallium nitride barrier layer 104.

[0022] When the device withstands positive gate 110 voltage, the Schottky junction formed by the first gallium nitride layer 109 and the gate 110 is forward biased. However, the n-i-p diode composed of the first gallium nitride layer 109, the second gallium nitride layer 108 and the third gallium nitride layer 107 is reverse biased. At this time, the electric field peak is distributed in the second gallium nitride layer 108 and the fourth gallium nitride layer 106. Compared with the traditional P-type gate GaN HEFT, the reverse-biased n-i-p diode has a higher breakdown voltage than the reverse-biased Schottky diode. In addition, this structure moves the electric field peak to the second gallium nitride layer 108 and the fourth gallium nitride layer 106 instead of the Schottky interface of the traditional device, avoiding premature breakdown of the device caused by interface states generated by surface cleaning and gate metal deposition.

[0023] In this connection unit, the first gallium nitride layer 109, the second gallium nitride layer 108, the third gallium nitride layer 107, and the fourth gallium nitride layer 106 can grow an epitaxial structure by MOCVD, and then obtain the corresponding structure through etching, and the interface quality of the n-i-p structure can be guaranteed. In addition, since the breakdown voltage of the p-i-n diode composed of the third gallium nitride layer 107, the fourth gallium nitride layer 106, and the barrier layer 104 is also higher than that of the PN junction diode, the device structure also has a higher reverse gate 110 breakdown voltage.

[0024] For further explanation of the compositions of the first gallium nitride layer 109, the second gallium nitride layer 108, the third gallium nitride layer 107, and the fourth gallium nitride layer 106, the first gallium nitride layer 109 is an n-type doped gallium nitride layer (n-GaN), the third gallium nitride layer 107 is a p-type doped gallium nitride layer (p-GaN), and the second gallium nitride layer 108 and the fourth gallium nitride layer 106 are unintentionally doped gallium nitride layers (u-GaN).

[0025] Preferably, the first gallium nitride layer 109 is an n-type lightly doped gallium nitride layer, and the third gallium nitride layer 107 is a p-type heavily doped gallium nitride layer.

[0026] The purpose of the above settings is that the fourth gallium nitride layer 106 is set to be unintentionally doped to prevent Mg in the third gallium nitride layer 107 from diffusing into the barrier layer 104. Additionally, when the device gate 110 has reverse breakdown voltage, the third gallium nitride layer 107, the fourth gallium nitride layer 106, and the barrier layer 104 form a p-i-n junction, which can effectively improve the reverse breakdown voltage of the device gate 110.

[0027] The third gallium nitride layer 107 is set to be p-type doped to raise the energy levels of the underlying barrier layer 104 and buffer layer 103, and deplete the two-dimensional electron gas in the buffer layer 103, thereby achieving enhancement mode.

[0028] The second gallium nitride layer 108 is set to be an unintentionally doped layer to shift the electric field peak into the unintentionally doped layer during the forward breakdown voltage of the device, thereby enhancing the forward breakdown voltage capability of the device.

[0029] The first gallium nitride layer 109 is set to be n-type doped to form an n-i-p structure with the second gallium nitride layer 108 and the third gallium nitride layer 107, which is reverse-biased during the forward breakdown voltage of the device gate 110 and bears the breakdown voltage of the gate 110.

[0030] Therefore, a further explanation of this solution is that the n-i-p diode composed of an n-type doped gallium nitride layer, an unintentionally doped gallium nitride layer, and a p-type doped gallium nitride layer is reverse-biased, and at this time, the peak electric field is distributed within the unintentionally doped gallium nitride layer. Compared with the traditional p-gate GaN HEFT, the reverse-biased n-i-p diode has a higher breakdown voltage than the reverse-biased Schottky diode. In addition, this structure shifts the peak electric field to the unintentionally doped gallium nitride layer instead of the Schottky interface of the traditional device, avoiding premature breakdown of the device caused by interface states generated during surface cleaning and gate metal deposition.

[0031] In addition, when considering the doping concentration range of the first gallium nitride layer 109, a threshold voltage between 0.8V and 2.5V is achieved, preferably 1e16 cm -3 ~1e20 cm -3 , and the doping concentration of the third gallium nitride layer 107 is selected as an achievable value of the actual doping concentration, which is 1e19 cm -3 ~3e19 cm -3 .

[0032] In an embodiment of the present invention, the thickness of the fourth gallium nitride layer 106 is set to 1 - 10 nm, which is a compromise consideration for the threshold voltage and the breakdown voltage of the gate 110. If it is too thin, it cannot play the role of improving the breakdown voltage, and if it is too thick, the threshold voltage of the device will be too low; the thickness of the third gallium nitride layer 107 is set to 50 - 100 nm, and the compromise relationship between the threshold voltage of the device and the breakdown voltage of the gate 110 needs to be considered. If it is too thick, the threshold voltage will be too high, and if it is too thin, the breakdown voltage of the gate 110 will be too low; the thickness of the second gallium nitride layer 108 is set to 1 - 10 nm, and the compromise relationship between the breakdown voltage of the gate 110 and the transconductance of the gate 110 needs to be considered. If it is too thick, the transconductance will be too low, and if it is too thin, it cannot play the role of improving the breakdown voltage; the thickness of the first gallium nitride layer 109 is set to 10 - 20 nm, and the compromise relationship between the breakdown voltage of the gate 110 and the transconductance of the gate 110 needs to be considered. If it is too thick, the transconductance will be too low, and if it is too thin, it cannot play the role of improving the breakdown voltage. The substrate 101 is selected to be a conventional one with a thickness of 0.3 - 1 mm.

[0033] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An enhanced gallium nitride heterojunction field effect transistor, comprising a substrate (101), a nucleation layer (102), a buffer layer (103) and a barrier layer (104) sequentially arranged from bottom to top, and a source electrode (105), a drain electrode (111) and a gate electrode (110) are respectively arranged above the barrier layer (104), characterized in that, A connection unit is provided between the gate (110) and the barrier layer (104). The connection unit includes a first gallium nitride layer (109), a second gallium nitride layer (108), a third gallium nitride layer (107), and a fourth gallium nitride layer (106). The first gallium nitride layer (109) to the fourth gallium nitride layer (106) are arranged in sequence from top to bottom. The first gallium nitride layer (109) is connected to the gate (110), and the fourth gallium nitride layer (106) is connected to the barrier layer (104). The first gallium nitride layer (109) is an n-type doped gallium nitride layer, the third gallium nitride layer (107) is a p-type doped gallium nitride layer, and the second gallium nitride layer (108) and the fourth gallium nitride layer (106) are unintentionally doped gallium nitride layers. The doping concentration of the first gallium nitride layer (109) is 1e16 cm -3 ~1e20 cm -3 , and the doping concentration of the third gallium nitride layer (107) is 1e19 cm -3 ~3e19 cm -3 .

2. The enhanced gallium nitride heterojunction field effect transistor according to claim 1, characterized in that, The thickness of the first gallium nitride layer (109) is 10 - 20 nm, the thickness of the third gallium nitride layer (107) is 50 - 100 nm, and the thickness of the second gallium nitride layer (108) and the fourth gallium nitride layer (106) is 1 - 10 nm.

3. The enhanced gallium nitride heterojunction field effect transistor according to claim 1, characterized in that, The source electrode (105) and the drain electrode (111) form an ohmic contact with the barrier layer (104).

4. The enhanced gallium nitride heterojunction field effect transistor according to claim 1, characterized in that, The gate (110) forms a Schottky contact with the first gallium nitride layer (109).

5. The enhanced gallium nitride heterojunction field effect transistor according to claim 1, characterized in that, The thickness of the substrate (101) is 0.3 - 1 mm.

6. The enhanced gallium nitride heterojunction field effect transistor according to claim 1, characterized in that, The nucleation layer (102) is an aluminum nitride nucleation layer (102), the buffer layer (103) is a gallium nitride buffer layer (103), and the barrier layer (104) is an aluminum gallium nitride barrier layer (104).

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