Multi-process corner delay circuit, phase adjustment circuit, clock control circuit and chip

Abstract

Embodiments of the present application disclose a multi-process corner delay circuit, a phase adjusting circuit, a clock control circuit and a chip. The multi-process corner delay circuit comprises a first delay selector and n delay units, wherein one delay unit corresponds to one process corner, each delay unit corresponds to a different process corner, and the delay unit is configured to control a first signal output end of itself to output a first delay signal according to a first selection signal, the first delay signal being a signal after a first delay or a second delay of a to-be-delayed signal corresponding to the process corner; the first delay selector comprises n selection input ends corresponding to the first signal output ends of the delay units one by one, the selection input end of the first delay selector is connected with the first signal output end of the corresponding delay unit, and the first delay selector is configured to control a selection output end of itself to output a signal of the corresponding selection input end according to a second selection signal; thus, the embodiments of the present application realize phase offsets of the to-be-delayed signal under n process corners, and the phase offsets comprise the first delay corresponding to the process corner or the second delay corresponding to the process corner.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device technology, and in particular to a multi-process corner delay circuit, a phase adjustment circuit, a clock control circuit, and a chip. Background Technology

[0002] With the rapid growth in demand for AI computing power, the number of operators within an AI chip's integrated operator cluster is also increasing dramatically. This makes improving the power consumption performance of cluster operators increasingly challenging. The stability of the chip's computing units during full-load operation after receiving instructions is often affected by operator power consumption noise. During parallel computing, there is a significant power consumption. A major challenge for large chips during this power consumption process is that power supply noise can interfere with or impact the chip's internal circuitry.

[0003] The traditional approach to this is to add sufficient capacitors to the chip's power supply unit for protection, similar to energy storage, to prevent excessive voltage drop. However, due to the limited chip area, the capacitor protection mechanism cannot respond quickly enough to overcome the instantaneous noise impact generated by multiple operators. Therefore, clock cycle phase adjustment is one solution. Multiple operators are grouped to different clock start points, with large-granular switching such as 0 degrees, 90 degrees (1 / 4 of the clock cycle), 180 degrees, and 270 degrees. This switching adjusts the clock phase, activating operator units in groups within a clock cycle. Dividing operator units into multiple groups and staggering their activation can achieve a certain degree of power consumption noise suppression.

[0004] However, as semiconductor processes advance to 7nm, 5nm, and 3nm, the density of operator units and the scale of operators continue to increase. The aforementioned large-granularity methods can no longer meet the requirements for control precision, and the problems of system noise interference and impact cannot be effectively solved. At this point, we need a fine-granular clock phase modulation method to achieve fine-granular phase control such as 0 degrees, 5 degrees, and 15 degrees while increasing the density of operator units. In the process of achieving fine-granular phase control, how to achieve phase shift of the clock signal at various process angles, and how to allow arbitrary phase shifts at corresponding process angles, has become a new and urgent problem to be solved. Summary of the Invention

[0005] This invention provides a multi-process-angle delay circuit, a phase adjustment circuit, a clock control circuit, and a chip to achieve phase shift of the clock signal at various process angles, as well as phase shift of arbitrary magnitude at the corresponding process angles, thereby realizing fine-grained phase control of multiple operator units.

[0006] In a first aspect, embodiments of the present invention provide a multi-process-angle delay circuit, comprising: a first receiving end, a second receiving end, a delay input end, a first delay output end, a first delay selector, and n delay units, where n is a positive integer. Each delay unit corresponds to a process angle, and each delay unit corresponds to a different process angle. Each delay unit includes a first sub-receiving end, a signal input end, and a first signal output end.

[0007] The first sub-receiving ends of the n delay units are all connected to the first receiving end, and the signal input ends of the n delay units serve as the n delay input ends;

[0008] The delay input terminal is used to receive the signal to be delayed, and the first receiving terminal is used to receive the first selection signal; the delay unit is used to control the corresponding first signal output terminal to output a first delay signal according to the first selection signal, and the first delay signal is the signal after the signal to be delayed has a first delay or a second delay corresponding to the process corner, and the first delay corresponding to the process corner is half of the second delay corresponding to the process corner.

[0009] The first delay selector includes a selection receiver, a selection output, and n selection inputs that correspond one-to-one with the first signal output. The selection inputs of the first delay selector are connected to the corresponding first signal outputs. The selection output of the first delay selector is connected to the first delay output. The selection receiver of the first delay selector is connected to the second receiver.

[0010] The second receiving end is used to receive the second selection signal; the first delay selector is used to control the signals of each of the selection input ends of the first delay selector to arrive at the selection output end of the first delay selector at the same time, and is used to control the selection output end of the first delay selector to output the corresponding signal of the selection input end according to the second selection signal.

[0011] Optionally, the selection receiver of the first delay selector includes Y selection sub-receivers, where Y is a positive integer, and the second selection signal includes Y second sub-selection signals. The y-th selection sub-receiver of the first delay selector is used to receive the y-th second sub-selection signal.

[0012] The first delay selector includes: Y-row selection units arranged in sequence, each selection unit including a second sub-receiver, a first input, a second input, and a selection sub-output;

[0013] The first and second input terminals of all the selection units in the first row serve as the n selection input terminals of the first delay selector;

[0014] The number of selection units in the (y-1)th row is k, and the number of selection units in the yth row is s, where s = int(k / 2) + mod(k, 2), y, k, and s are all positive integers. The yth row has 1 selection unit, and 2 ≤ y ≤ Y. In the same row direction, the selector outputs of the 2p-1th and 2pth selection units in the (y-1)th row are respectively connected to the first and second inputs of the pth selection unit in the yth row, where p is a positive integer and 1 ≤ p ≤ s. The selector outputs of the 2(p+1)-1th and 2(p+1)th selection units in the (y-1)th row are respectively connected to the first and second inputs of the (p+1)th selection unit in the yth row.

[0015] The selector output of the selection unit in row Y is used as the selection output of the first delay selector;

[0016] The second sub-receiving terminal of all the selection units in the y-th row is connected to the y-th selection sub-receiving terminal of the first delay selector; the selection unit is used to control the corresponding selection sub-output terminal to output the signal of the corresponding first input terminal or the second input terminal according to the corresponding second sub-selection signal.

[0017] Optionally, the delay unit includes: a first buffer, a second buffer, and the selection unit, wherein the selection unit includes a second sub-receiver, a first input, a second input, and a selection sub-output.

[0018] The input terminal of the first buffer serves as the signal input terminal, the output terminal of the first buffer is connected to the first input terminal of the selection unit, the input terminal of the second buffer is connected to the output terminal of the first buffer, the output terminal of the second buffer is connected to the second input terminal of the selection unit, the second sub-receiving terminal of the selection unit serves as the first sub-receiving terminal, the selection sub-output terminal of the selection unit serves as the first signal output terminal, and the output terminal of the second buffer serves as the second signal output terminal.

[0019] The delay magnitude of the first buffer and the characteristic information of the signal transmission line between the input terminals of the first buffer and the input terminals of the second buffer jointly determine the first delay corresponding to the process angle, wherein the characteristic information includes the length of the signal transmission line.

[0020] Optionally, the selection unit includes: a first selection element, a second selection element, a third selection element, a fourth selection element, and an inverting element;

[0021] The first sub-input terminal of the first selection element serves as the first input terminal of the selection unit, the second sub-input terminal of the first selection element serves as the second input terminal of the selection unit, the third sub-input terminal of the first selection element serves as the second sub-receiving terminal of the selection unit, and the output terminal of the first selection element serves as the selection sub-output terminal of the selection unit.

[0022] The first sub-input terminal of the second selection element is connected to the second sub-input terminal of the first selection element, the second sub-input terminal of the second selection element is connected to the first sub-input terminal of the first selection element, and the third sub-input terminal of the second selection element is connected to the third sub-input terminal of the first selection element.

[0023] The first sub-input terminal of the third selection element is connected to the first sub-input terminal of the first selection element, the second sub-input terminal of the third selection element is connected to the second sub-input terminal of the first selection element, and the third sub-input terminal of the third selection element is connected to the third sub-input terminal of the first selection element through the inverting element.

[0024] The first sub-input terminal of the fourth selection element is connected to the second sub-input terminal of the first selection element, the second sub-input terminal of the fourth selection element is connected to the first sub-input terminal of the first selection element, and the third sub-input terminal of the fourth selection element is connected to the third sub-input terminal of the first selection element through the inverting element.

[0025] Secondly, embodiments of the present invention also provide a phase adjustment circuit, including a third receiving end, a fourth receiving end, a fifth receiving end, a commutation input end, a commutation output end, a second delay selector, and M multi-process angle delay circuits as described in the first aspect above, where M is a positive integer;

[0026] The number of delay units set in each of the multi-process-corner delay circuits is the same; in each of the multi-process-corner circuits, the multi-process-corner delay circuit further includes n second delay output terminals, and the delay unit further includes a second signal output terminal. The second signal output terminals of the n delay units serve as n second delay output terminals, wherein the second signal output terminal of the delay unit is used to output the signal after the second delay of the signal to be delayed at the corresponding process corner;

[0027] M multi-process-angle delay circuits are connected in series with each other in sequence; wherein, the n delay input terminals of the first multi-process-angle delay circuit are connected together to serve as the commutation input terminal, the n second delay output terminals of the (m-1)th multi-process-angle delay circuit are connected one-to-one with the n delay input terminals of the mth multi-process-angle delay circuit, M≥m≥2, the first receiving terminals of the M multi-process-angle delay circuits are connected together to serve as the third receiving terminal, the second receiving terminals of the M multi-process-angle delay circuits are connected together to serve as the fourth receiving terminal, and m is a positive integer;

[0028] The second delay selector includes a selection receiver, a selection output, and M selection inputs that correspond one-to-one with the first delay output. The selection inputs of the second delay selector are connected to the corresponding first delay outputs. The selection outputs of the second delay selector are connected to the commutation outputs. The selection receiver of the second delay selector is connected to the fifth receiver.

[0029] The fifth receiving end is used to receive the third selection signal, and the second delay selector is used to control the signals of each of the selection input ends of the second delay selector to arrive at the selection output end of the first delay selector at the same time, and to control the selection output end of the second delay selector to output the corresponding signal of the selection input end according to the third selection signal.

[0030] Optionally, the selection receiver of the second delay selector includes X selection sub-receivers, where X is a positive integer, and the fifth selection signal includes X fifth sub-selection signals. The xth selection sub-receiver of the second delay selector is used to receive the xth fifth sub-selection signal, where x is a positive integer.

[0031] The second delay selector includes: X rows of selection units arranged in sequence, each selection unit including a second sub-receiver, a first input, a second input, and a selection sub-output;

[0032] The first and second input terminals of all the selection units in the first row serve as the M selection input terminals of the second delay selector;

[0033] The number of selection units in the (x-1)th row is k, and the number of selection units in the xth row is s, where s = int(k / 2) + mod(k, 2), x, k, and s are all positive integers. The xth row has one selection unit, and 2 ≤ x ≤ x. In the same row direction, the selector outputs of the 2p-1th and 2pth selection units in the (x-1)th row are connected to the first and second inputs of the pth selection unit in the xth row, respectively, where p is a positive integer and 1 ≤ p ≤ s. The selector outputs of the 2(p+1)-1th and 2(p+1)th selection units in the (y-1)th row are connected to the first and second inputs of the (p+1)th selection unit in the xth row, respectively.

[0034] The selector output of the selection unit in row X serves as the selection output of the second delay selector;

[0035] The second sub-receiving terminal of all the selection units in the xth row is connected to the xth selection sub-receiving terminal of the second delay selector; the selection unit is used to control the corresponding selection sub-output terminal to output the signal of the corresponding first input terminal or the second input terminal according to the corresponding fifth sub-selection signal.

[0036] Optionally, the selection unit includes: a first selection element, a second selection element, a third selection element, a fourth selection element, and an inverting element;

[0037] The first sub-input terminal of the first selection element serves as the first input terminal of the selection unit, the second sub-input terminal of the first selection element serves as the second input terminal of the selection unit, the third sub-input terminal of the first selection element serves as the second sub-receiving terminal of the selection unit, and the output terminal of the first selection element serves as the selection sub-output terminal of the selection unit.

[0038] The first sub-input terminal of the second selection element is connected to the second sub-input terminal of the first selection element, the second sub-input terminal of the second selection element is connected to the first sub-input terminal of the first selection element, and the third sub-input terminal of the second selection element is connected to the third sub-input terminal of the first selection element.

[0039] The first sub-input terminal of the third selection element is connected to the first sub-input terminal of the first selection element, the second sub-input terminal of the third selection element is connected to the second sub-input terminal of the first selection element, and the third sub-input terminal of the third selection element is connected to the third sub-input terminal of the first selection element through the inverting element.

[0040] The first sub-input terminal of the fourth selection element is connected to the second sub-input terminal of the first selection element, the second sub-input terminal of the fourth selection element is connected to the first sub-input terminal of the first selection element, and the third sub-input terminal of the fourth selection element is connected to the third sub-input terminal of the first selection element through the inverting element.

[0041] Thirdly, embodiments of the present invention also provide a clock control circuit for controlling the phase of a clock signal, characterized in that it includes a clock distribution module and a plurality of phase adjustment circuits as described in the second aspect above.

[0042] The clock distribution module includes an equidistant distribution unit, an anti-interference unit, a clock receiver, and multiple clock transmitters.

[0043] The clock receiving end is connected to each of the clock transmitting ends through the equidistant distribution unit; the equidistant distribution unit is used to distribute the clock signal received by the clock receiving end into multiple branch clock signals that are respectively transmitted from each of the clock transmitting ends, and is used to control the total length of the signal transmission lines between the clock receiving end and each of the clock transmitting ends to be the same.

[0044] The anti-interference unit extends in the same direction as the signal transmission line, and the anti-interference unit is disposed on at least two opposite sides of the signal transmission line; the anti-interference unit is used to absorb interference signals distributed on the outer surface of the signal transmission line.

[0045] The phase adjustment circuit corresponds one-to-one with the clock transmitting end, and the commutation input end of the phase adjustment circuit is connected to the corresponding clock transmitting end.

[0046] Fourthly, embodiments of the present invention also provide a chip including the phase adjustment circuit described in the second aspect above.

[0047] Optionally, it also includes multiple operator units; there are multiple phase adjustment circuits, each corresponding to one of the operator units, and the commutation output terminal of the phase adjustment circuit is connected to the corresponding operator unit.

[0048] This invention embodiment includes a multi-process-corner delay circuit comprising a first delay selector and n delay units. Each delay unit corresponds to a specific process corner, and each delay unit corresponds to a different process corner. Each delay unit controls its first signal output terminal to output a first delay signal based on a first selection signal. The first delay signal is the signal after the delay signal has undergone a first delay or a second delay at the corresponding process corner, where the first delay is half of the second delay. Simultaneously, the first delay selector includes n selection input terminals, each corresponding to a first signal output terminal of one of the delay units. The selection input terminal of the first delay selector is connected to the first signal output terminal of the corresponding delay unit. The first delay selector controls its selection output terminal to output the signal of the corresponding selection input terminal based on a second selection signal. This invention embodiment thereby achieves phase shift of the delay signal (i.e., the clock signal) at n different process corners. The phase shift can be either the first delay or the second delay at the corresponding process corner.

[0049] Furthermore, this embodiment of the invention sets up a phase adjustment circuit including a second delay selector and M multi-process angle delay circuits provided in this embodiment of the invention. The n delay inputs of the first multi-process angle delay circuit are connected together to serve as commutation inputs (for receiving the signal to be delayed). The n second delay outputs of the (m-1)th multi-process angle delay circuit are connected one-to-one with the n delay inputs of the mth multi-process angle delay circuit. Simultaneously, the second delay selector includes M selection inputs that correspond one-to-one with the first delay outputs of the multi-process angle delay circuits. The selection inputs of the second delay selector are connected to the corresponding first delay outputs. The second delay selector is used to control its selection output to output the signal of the corresponding selection input according to a third selection control signal. Based on this, this embodiment of the invention achieves 2M phase shifts for the signal to be delayed under n process angles. The magnitude of the phase shift can be (2u-1)T or uT, where M≥u≥1, where M and u are both positive integers, and T is the first delay of the corresponding process angle. Different magnitudes of T correspond to different process angles.

[0050] Furthermore, this embodiment of the invention sets up a clock control circuit including a clock distribution module and multiple phase adjustment circuits provided in this embodiment of the invention. The clock distribution module is used to distribute the original single clock signal into multiple branch clock signals sent from its respective clock transmitting ends. The phase adjustment circuits correspond one-to-one with the clock transmitting ends, and the commutation input of the phase adjustment circuit is connected to the corresponding clock transmitting end, so that the branch clock signal of the clock transmitting end serves as the delay signal of the corresponding commutation input. When the delay signal passes through the corresponding phase adjustment circuit, it can undergo 2M phase shifts at any one of the n process angles. The magnitude of the phase shift can be (2u-1)T or uT, where M≥u≥1. The signal that has undergone the phase shift is output to the corresponding operator unit, and the corresponding operator unit can be started. Based on this, this embodiment of the invention realizes fine-grained phase control of multiple operator units. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of a multi-process corner delay circuit provided in an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of the structure of a selection unit provided in an embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram of the structure of a first delay selector provided in an embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of the structure of a delay unit provided in an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of a phase adjustment circuit provided in an embodiment of the present invention. Detailed Implementation

[0056] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0057] Figure 1 This is a schematic diagram of a multi-process corner delay circuit provided in an embodiment of the present invention. (Reference) Figure 1The multi-process angle delay circuit 10 includes: a first receiving terminal A1, a second receiving terminal A2, a delay input terminal B1, a first delay output terminal B2, a first delay selector 30, and n delay units 20, where n is a positive integer. Each delay unit 20 corresponds to a process angle, and each delay unit 20 corresponds to a different process angle. The delay unit 20 includes a first sub-receiving terminal a1, a signal input terminal b1, and a first signal output terminal b2.

[0058] The first sub-receiver a1 of each of the n delay units 20 is connected to the first receiver A1, and the signal input terminal b1 of the n delay units 20 serves as the n delay input terminals B1.

[0059] The delay input terminal B1 is used to receive the signal to be delayed, and the first receiving terminal A1 is used to receive the first selection signal; the delay unit 20 is used to control the corresponding first signal output terminal b2 to output the first delay signal according to the first selection signal. The first delay signal is the signal after the first delay or the second delay of the signal to be delayed occurs at the corresponding process corner. The first delay at the corresponding process corner is half of the second delay at the corresponding process corner.

[0060] The first delay selector 30 includes a selection receiver D3, a selection output D2, and n selection inputs D1 corresponding one-to-one with the first signal output b2. The selection inputs D1 of the first delay selector 30 are connected to the corresponding first signal output b2, the selection output D2 of the first delay selector 30 is connected to the first delay output B2, and the selection receiver D3 of the first delay selector 30 is connected to the second receiver A2.

[0061] The second receiving terminal A2 is used to receive the second selection signal; the first delay selector 30 is used to control the signals of each selection input terminal D1 of the first delay selector 30 to arrive at the selection output terminal D2 of the first delay selector 30 at the same time, and is used to control the selection output terminal D2 of the first delay selector 30 to output the corresponding selection input terminal D1 signal according to the second selection signal.

[0062] Among them, the multi-process-angle delay circuit can also be called the multi-process-angle signal delay circuit. A process angle refers to the process deviation in the semiconductor device fabrication process; that is, one process angle corresponds to one process deviation, and different process deviations correspond to different operating performance of the semiconductor device. For example, in the transistor fabrication process, different process angles can correspond to different response speeds of the transistor. The specific value of n can be flexibly set according to actual needs. Based on its own structural characteristics, each delay unit 20 corresponds to one process angle, and n process angles correspond to n first delays. Different process angles correspond to different sizes of first delays, and the second delay is twice the first delay.

[0063] Specifically, the signal input terminals b1 of the n delay units 20 serve as the n delay input terminals B1 of the multi-process corner delay circuit. The n delay input terminals B1 are used to simultaneously receive the signal to be delayed, thus allowing the n delay units 20 to simultaneously receive the signal to be delayed. The first sub-receiving terminals a1 of the n delay units 20 are all connected to the first receiving terminal A1 of the multi-process corner delay circuit, allowing the n delay units 20 to simultaneously receive the first selection signal. When a delay unit 20 receives both the signal to be delayed and the first selection signal, the delay unit 20 controls its first signal output terminal b2 to output a first delay signal. The first delay signal is the signal after the signal to be delayed has undergone a first delay or a second delay corresponding to the corresponding process corner after passing through the delay unit 20. For example, when the first selection signal is a high-level signal, the signal to be delayed undergoes a first delay corresponding to the corresponding process corner after passing through the delay unit 20; when the first selection signal is a low-level signal, the signal to be delayed undergoes a second delay corresponding to the corresponding process corner after passing through the delay unit 20.

[0064] Assume the first delay unit 20 corresponds to the first process angle, the second delay unit 20 corresponds to the second process angle, and so on up to the nth delay unit 20 corresponding to the nth process angle. For example, refer to... Figure 1 When the first delay unit 20 receives the signal to be delayed and the first selection signal, the first delay unit 20 controls its first signal output terminal b2 to output a first delay signal. The first delay signal is either a first delay of the signal to be delayed occurring at a first process angle or a second delay of the signal occurring at a first process angle. The magnitude of the second delay at the first process angle is equal to the first delay signal. The delay signal is twice the first delay of the process angle. When the second delay unit 20 receives the signal to be delayed and the first selection signal, the second delay unit 20 controls the first signal output terminal b2 of the second delay unit 20 to output the second first delay signal. The second first delay signal is either the first delay of the signal to be delayed at the second process angle or the second delay of the signal to be delayed at the second process angle. The magnitude of the second delay of the second process angle is equal to twice the first delay of the second process angle. The working principle of the remaining delay units 20 is the same as that of the first or second delay unit 20, and will not be described again. Based on this, the embodiment of the present invention realizes the phase shift of the signal to be delayed at multiple process angles, respectively and simultaneously.

[0065] Based on this, the n selection inputs D1 of the first delay selector 30 correspond one-to-one with the n first signal outputs b2 of the n delay units 20, and the selection inputs D1 of the first delay selector 30 are connected to the corresponding first signal outputs b2, so that the selection inputs D1 of the first delay selector 30 receive the first delayed signal output by the corresponding first signal output b2. For example, the first selection input D1 of the first delay selector 30 receives the first first delayed signal output by the first signal output b2 of the first delay unit 20, the second selection input D1 of the first delay selector 30 receives the second first delayed signal output by the first signal output b2 of the second delay unit 20, and so on. Similarly, the nth selection input D1 of the first delay selector 30 receives the nth first delayed signal output by the first signal output b2 of the nth delay unit 20.

[0066] Based on its structural features, the first delay selector 30 ensures that the signals from each selection input terminal D1 arrive at the selection output terminal D2 of the first delay selector 30 at the same time. Specifically, the arrival times of the first first delay signal from the first selection input terminal D1, the second first delay signal from the second selection input terminal D1, and so on, up to the nth first delay signal from the nth selection input terminal D1, are all the same. This configuration ensures that each first delay signal has the same delay when arriving at the selection output terminal D2 of the first delay selector 30, thereby guaranteeing a relatively high accuracy in the arrival of the first delay signals at the selection output terminal D2.

[0067] Furthermore, when the first delay selector 30 receives the second selection signal, the first delay selector 30 controls the selection output terminal D2 of the first delay selector 30 to output the corresponding signal of the selection input terminal D1 according to the second selection signal. That is, the first delay selector 30 controls the selection output terminal D2 of the first delay selector 30 to output the corresponding first delay signal among n first delay signals according to the second selection signal, thereby realizing the phase shift of the signal to be delayed at any one of the n process angles.

[0068] In summary, the multi-process-angle delay circuit provided in this embodiment of the invention achieves the delay of the signal to be delayed at the corresponding process angle (including the first delay or the second delay of the corresponding process angle) by setting the delay unit 20; on this basis, by setting the first delay selector 30 and n delay units 20, the delay of the signal to be delayed at any one of the n process angles (including the first delay or the second delay of any one process angle) is achieved; at the same time, since the signals of each selection input terminal D1 of the first delay selector 30 arrive at the selection output terminal D2 of the first delay selector 30 at the same time, it is ensured that the signal to be delayed has high relative accuracy when it is output from the selection output terminal D2 of the first delay selector 30 after being delayed at any one of the n process angles. Compared with the prior art that uses phase-locked loops or registers and combinational logic to achieve signal phase shift, the technical solution of this invention has a simpler circuit structure, is easier to manufacture and implement, and can achieve delays for more process angles when the value of n is large, thus meeting the needs of phase shift for various process angles, which is beneficial to achieving fine-grained phase control of multiple operator units.

[0069] The multi-process angle delay circuit provided in this embodiment of the invention is versatile and can be applied to any circuit that needs to achieve multiple process angle phase shifts. The only difference is that the value of n can be reasonably set according to the actual type of multi-process angle delay required. That is, the structure of the multi-process angle delay circuit provided in this embodiment of the invention can be customized according to the actual type of multi-process angle delay required.

[0070] Figure 2 This is a schematic diagram of a selection unit provided in an embodiment of the present invention. (Reference) Figure 2 In one embodiment of the present invention, the selection unit 40 may optionally include: a first selection element 41, a second selection element 42, a third selection element 43, a fourth selection element 44, and an inverting element 45;

[0071] The first sub-input terminal of the first selection element 41 serves as the first input terminal d2 of the selection unit 40, the second sub-input terminal of the first selection element 41 serves as the second input terminal d3 of the selection unit 40, the third sub-input terminal of the first selection element 41 serves as the second sub-receiving terminal a2 of the selection unit 40, and the output terminal of the first selection element 41 serves as the selection sub-output terminal d4 of the selection unit 40.

[0072] The first sub-input terminal of the second selection element 42 is connected to the second sub-input terminal of the first selection element 41, the second sub-input terminal of the second selection element 42 is connected to the first sub-input terminal of the first selection element 41, and the third sub-input terminal of the second selection element 42 is connected to the third sub-input terminal of the first selection element 41.

[0073] The first sub-input terminal of the third selection element 43 is connected to the first sub-input terminal of the first selection element 41, the second sub-input terminal of the third selection element 43 is connected to the second sub-input terminal of the first selection element 41, and the third sub-input terminal of the third selection element 43 is connected to the third sub-input terminal of the first selection element 41 through the inverting element 45.

[0074] The first sub-input terminal of the fourth selection element 44 is connected to the second sub-input terminal of the first selection element 41, the second sub-input terminal of the fourth selection element 44 is connected to the first sub-input terminal of the first selection element 41, and the third sub-input terminal of the fourth selection element 44 is connected to the third sub-input terminal of the first selection element 41 through the inverting element 45.

[0075] Specifically, the selection element can be a selector, and the inverting element 45 can be an inverter, which can control the signal to flip. Here, we take the first selection element 41 as an example to illustrate the characteristics of the selection element: Due to the structural characteristics of the first selection element 41, the opening time of the first sub-input terminal, the closing time of the first sub-input terminal, the opening time of the second sub-input terminal, and the closing time of the second sub-input terminal are all different. This can easily cause the delay from the signal at the first sub-input terminal to the output terminal of the first selection element 41 to be different from the delay from the signal at the second sub-input terminal to the output terminal of the first selection element 41, that is, the relative accuracy of the signal output by the first selection element 41 is relatively low.

[0076] Accordingly, in this embodiment of the invention, the selection unit 40 includes a first selection element 41, a second selection element 42, a third selection element 43, a fourth selection element 44, an inverter, and their interconnections, such that when the output terminal of the first selection element 41 outputs a signal from its first sub-input terminal, the signal from the first sub-input terminal corresponds to an open first sub-input terminal, a closed second sub-input terminal, a closed first sub-input terminal, and an open second sub-input terminal; similarly, when the output terminal of the first selection element 41 outputs a signal from its second sub-input terminal, the signal from the second sub-input terminal corresponds to an open second sub-input terminal, a closed first sub-input terminal, a closed second sub-input terminal, and an open first sub-input terminal; thereby ensuring that the delay from the signal from the first sub-input terminal of the first selection element 41 to its output terminal is the same as the delay from the signal from the second sub-input terminal of the first selection element 41 to its output terminal, thus improving the relative accuracy of the signal output by the first selection element 41.

[0077] The selection unit 40 provided in this embodiment of the invention has high relative accuracy of its output signal because the delay between the signal from the first sub-input terminal of the first selection element 41 and the delay between the signal from the second sub-input terminal of the first selection element 41 and the output terminal is the same. It is versatile and can be applied to any circuit that requires signal selection to improve the relative accuracy of the output signal. For example, it can be used in delay selectors, delay units 20, multi-process angle delay circuits, phase adjustment circuits, and clock control circuits. The following examples illustrate application scenarios of the selection unit 40, but are not intended to limit its application.

[0078] Based on the above embodiments, Figure 3 This is a schematic diagram of a first delay selector provided in an embodiment of the present invention. (Reference) Figure 3 In one embodiment of the present invention, optionally, the selection receiver D3 of the first delay selector 30 includes Y selection sub-receivers, where Y is a positive integer, and the second selection signal includes Y second sub-selection signals. The y-th selection sub-receiver of the first delay selector 30 is used to receive the y-th second sub-selection signal.

[0079] The first delay selector 30 includes: Y-row selection units 40 arranged sequentially, each selection unit 40 including a second sub-receiver, a first input, a second input, and a selection sub-output.

[0080] The first input terminal d2 and the second input terminal of all selection units 40 in the first row are used as the n selection input terminals D1 of the first delay selector 30;

[0081] The number of selection units 40 in the (y-1)th row is k, and the number of selection units 40 in the yth row is s, where s = int(k / 2) + mod(k, 2), y, k, and s are all positive integers. The yth row has 1 selection unit 40, and 2 ≤ y ≤ Y. In the same row direction, the selector output terminal d4 of the 2p-1th and 2pth selection units 40 in the (y-1)th row is connected to the first input terminal d2 and the second input terminal of the pth selection unit 40 in the yth row, respectively, where p is a positive integer and 1 ≤ p ≤ s. The selector output terminal d4 of the 2(p+1)-1th and 2(p+1)th selection units 40 in the (y-1)th row is connected to the first input terminal d2 and the second input terminal of the (p+1)th selection unit 40 in the yth row, respectively.

[0082] The selector output terminal d4 of the selection unit 40 in row Y is used as the selection output terminal D2 of the first delay selector 30;

[0083] The second sub-receiver a2 of all selection units 40 in the y-th row is connected to the y-th selection sub-receiver of the first delay selector 30; the selection unit 40 is used to control the corresponding selection sub-output to output the signal of the corresponding first input or second input according to the corresponding second sub-selection signal.

[0084] In this embodiment of the invention, the first delay selector 30 is configured such that the signals at each selection input terminal D1 of the first delay selector 30 traverse the same number of selection units 40 and follow the same signal transmission path during their transmission to the selection output terminal D2. This ensures that the signals at each selection input terminal D1 arrive at the selection output terminal D2 of the first delay selector 30 at equal times, resulting in the same delay and guaranteeing the relative accuracy of the output signal from the first delay selector 30. The first delay selector 30 provided in this embodiment of the invention is versatile and applicable to other circuits requiring multiple-choice signal selection. While achieving multiple-choice signal selection, it ensures high relative accuracy of the selected output signal. The only difference in the specific configuration is adjusting the value of Y, i.e., adjusting the number of selection units 40, without changing the overall structure. For example, in this embodiment of the invention, the structure of the first delay selector 30 is also applied to the phase adjustment circuit, which will be mentioned below.

[0085] Based on the above embodiments, Figure 4 This is a schematic diagram of a delay unit provided in an embodiment of the present invention. (Reference) Figure 4 In one embodiment of the present invention, the delay unit 20 may optionally include: a first buffer 21, a second buffer 22 and a selection unit 40, wherein the selection unit 40 includes a second sub-receiver, a first input, a second input and a selection sub-output.

[0086] The input terminal of the first buffer 21 serves as the signal input terminal b1, and the output terminal of the first buffer 21 is connected to the first input terminal d2 of the selection unit 40. The input terminal of the second buffer 22 is connected to the output terminal of the first buffer 21, and the output terminal of the second buffer 22 is connected to the second input terminal d3 of the selection unit 40. The second sub-receiver terminal a2 of the selection unit 40 serves as the first sub-receiver terminal a1, and the selection sub-output terminal d4 of the selection unit 40 serves as the first signal output terminal b2. The output terminal of the second buffer 22 serves as the second signal output terminal b3.

[0087] The delay magnitude of the first buffer 21 and the characteristic information of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the second buffer 22 jointly determine the first delay of the corresponding process corner. The characteristic information includes the length of the signal transmission line.

[0088] Specifically, the structure of the selection unit 40 in the delay unit 20 is the same as the structure of the selection unit 40 in the first delay selector 30, that is, both are... Figure 2 The selection unit 40 is shown in the diagram. Because the signal output by the selection unit 40 has relatively high accuracy, the delay unit 20 is configured to include the selection unit 40 so that the signal output by the delay unit 20 also has relatively high accuracy; that is, the time taken for the signal after the first delay in the delay unit 20 to reach the first signal output terminal b2 of the delay unit 20 is equal to the time taken for the signal after the second delay in the delay unit 20 to reach the first signal output terminal b2 of the delay unit 20. The characteristic information of the signal transmission line may include the length and / or width of the signal transmission line, etc. Optionally, the first delay of the process angle corresponding to the delay unit 20 is determined by the delay magnitude of the first buffer 21 and the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the second buffer 22. Meanwhile, the second buffer 22 may have the same delay as the first buffer 21.

[0089] When the delay values ​​of the first buffers 21 in each delay unit 20 are all the same, the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the corresponding second buffer 22 in each delay unit 20 determines the magnitude of the first delay for the corresponding process corner of the delay unit 20. For example, the first delay for the first process corner corresponding to the first delay unit 20 is determined by the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the second buffer 22 in the first delay unit 20; the first delay for the second process corner corresponding to the second delay unit 20 is determined by the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the second buffer 22 in the second delay unit 20... Similarly, the first delay for the nth process corner corresponding to the nth delay unit 20 is determined by the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the second buffer 22 in the nth delay unit 20.

[0090] Therefore, in this embodiment of the invention, when the delay size of the first buffer 21 in each delay unit 20 is the same, the size of the first delay of the corresponding delay unit 20 corresponding to the process corner can be set by setting the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the corresponding second buffer 22. In this embodiment of the invention, the minimum first delay can be as short as 5ps, and the corresponding minimum second delay can be as short as 10ps, where ps is a unit of time, 1ps = 10⁻¹² seconds. That is, the delay unit 20 provided in this embodiment of the invention is universal and applicable to any circuit that needs to achieve clock signal phase shift. It has a simple structure and is easy to customize. Based on the determination of the first buffer 21 and the second buffer 22, only the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the second buffer 22 needs to be adjusted to obtain the delay unit 20 with the required delay size.

[0091] This invention also provides a phase adjustment circuit. Figure 5 This is a schematic diagram of a phase adjustment circuit provided in an embodiment of the present invention. (Reference) Figure 5 The phase adjustment circuit 60 includes: a third receiving terminal F2, a fourth receiving terminal F3, a fifth receiving terminal F4, a commutation input terminal F1, a commutation output terminal F5, a second delay selector 50, and M multi-process angle delay circuits 10 as provided in any of the above embodiments, where M is a positive integer;

[0092] The number of delay units 20 set in each multi-process corner delay circuit 10 is the same; in each multi-process corner circuit 10, the multi-process corner delay circuit 10 also includes n second delay output terminals B3, and the delay unit 20 also includes a second signal output terminal b3. The second signal output terminals b3 of the n delay units 20 serve as n second delay output terminals B3. The second signal output terminal b2 of the delay unit 20 is used to output the signal after the second delay of the signal to be delayed at the corresponding process corner.

[0093] M multi-process-angle delay circuits 10 are connected in series with each other. Among them, the n delay input terminals B1 of the first multi-process-angle delay circuit 10 are connected together to form the commutation input terminal F1. The n second delay output terminals B3 of the (m-1)th multi-process-angle delay circuit 10 are connected one-to-one with the n delay input terminals B1 of the mth multi-process-angle delay circuit 10, M≥m≥2. The first receiving terminals A1 of the M multi-process-angle delay circuits 10 are connected together to form the third receiving terminal F2. The second receiving terminals A2 of the M multi-process-angle delay circuits 10 are connected together to form the fourth receiving terminal F3. m is a positive integer.

[0094] The second delay selector 50 includes a selection receiver E3, a selection output E2, and M selection inputs E1 corresponding one-to-one with the first delay output B2. The selection inputs E1 of the second delay selector 50 are connected to the corresponding first delay output B2. The selection output E2 of the second delay selector 50 is connected to the commutation output F5. The selection receiver E3 of the second delay selector 50 is connected to the fifth receiver F4.

[0095] The fifth receiving terminal F4 is used to receive the third selection signal. The second delay selector 50 is used to control the signals of each selection input terminal E1 of the second delay selector 50 to arrive at the selection output terminal E2 of the second delay selector 50 at the same time. It is also used to control the selection output terminal E2 of the second delay selector 50 to output the corresponding selection input terminal E1 signal according to the third selection signal.

[0096] Specifically, the n delay input terminals B1 of the first multi-process-angle delay circuit are connected together and used as commutation input terminal F1. Thus, the signal output by the first delay output terminal B2 of the first multi-process-angle delay circuit is the signal after the delay signal has undergone the first delay T of the corresponding process angle or the second delay 2T of the corresponding process angle.

[0097] The n second delay outputs B3 of the (m-1)th multi-process-angle delay circuit 10 are connected one-to-one with the n delay inputs B1 of the m-th multi-process-angle delay circuit 10. Thus, the second multi-process-angle delay circuit 10 applies a first or second delay to the signal from the second delay output B3 of the first multi-process-angle delay circuit 10 corresponding to the process angle. The signal output from the first delay output B2 of the second multi-process-angle delay circuit 10 is the signal after the delay signal has undergone 3T or 4T of the corresponding process angle. The third multi-process-angle delay circuit 10 applies a first or second delay to the signal from the second delay output B3 of the second multi-process-angle delay circuit 10 corresponding to the process angle. The signal output from the first delay output terminal B2 of the third multi-process-angle delay circuit 10 is the signal after the delay signal has undergone 5T or 6T of the corresponding process angle. The fourth multi-process-angle delay circuit 10 performs a first or second delay on the signal from the second delay output terminal B3 of the third multi-process-angle delay circuit 10 corresponding to the process angle. The signal output from the first delay output terminal B2 of the fourth multi-process-angle delay circuit 10 is the signal after the delay signal has undergone 7T or 8T of the corresponding process angle... Similarly, the signal output from the first delay output terminal B2 of the Mth multi-process-angle delay circuit 10 is the signal after the delay signal has undergone (2M-1)T or 2MT of the corresponding process angle. As mentioned above, the value of T is determined by the process angle, specifically by the length of the signal transmission line between the input terminal of the first buffer 21 and the input terminal of the corresponding second buffer 22 in the delay unit 20.

[0098] The M selection inputs E1 of the second delay selector 50 correspond one-to-one with the first delay outputs B2 of the M multi-process corner delay circuits 10, and the selection inputs E1 of the second delay selector 50 are connected to the corresponding first delay outputs B2, so that the selection inputs E1 of the second delay selector 50 receive the signals output by the corresponding first delay outputs B2. For example, the first selection input E1 of the second delay selector 50 receives the signal output by the first delay output B2 of the first multi-process corner delay circuit 10, the second selection input E1 of the second delay selector 50 receives the signal output by the first delay output B2 of the second multi-process corner delay circuit 10, and so on. Similarly, the Mth selection input E1 of the second delay selector 50 receives the signal output by the first delay output B2 of the Mth multi-process corner delay circuit 10.

[0099] Based on its own structural features, the second delay selector 50 controls the signals of each selection input terminal E1 of the second delay selector 50 to reach the selection output terminal E2 of the second delay selector 50 at the same time. That is, the signals of the first selection input terminal E1, the second selection input terminal E1, ... and the Mth selection input terminal E1 of the second delay selector 50 reach the selection output terminal E2 of the second delay selector 50 with the same delay, thereby ensuring the relative accuracy of the output signal of the second delay selector 50.

[0100] Furthermore, when the second delay selector 50 receives the third selection signal, the second delay selector 50 controls the selection output terminal E2 of the second delay selector 50 to output the corresponding signal of the M selection input terminals E1 according to the third selection signal, thereby realizing that the signal to be delayed will have 2M phase shifts under any one of the n process angles, where the accuracy of the phase shift is T, and the magnitude of the phase shift can be (2u-1)T or uT, M≥u≥1.

[0101] The purpose of setting the delay unit 20 to include the second signal output terminal b3 in this embodiment of the invention is to realize the series connection of 2M buffers in the phase adjustment circuit, thereby realizing the maximum delay of 2MT and 2M phase shifts in the phase adjustment circuit, wherein the accuracy of the phase shift is T, and the first buffer and the second buffer are collectively referred to as buffers.

[0102] In one embodiment of the present invention, optionally, the selection receiving end E3 of the second delay selector 50 includes X selection sub-receiving ends, where X is a positive integer, and the fifth selection signal includes X fifth sub-selection signals. The xth selection sub-receiving end of the second delay selector 50 is used to receive the xth fifth sub-selection signal, where x is a positive integer.

[0103] The second delay selector 50 includes: X rows of selection units 40 arranged in sequence, each selection unit 40 including a second sub-receiver a2, a first input d2, a second input d3, and a selection sub-output d4;

[0104] The first input terminal d2 and the second input terminal d3 of all selection units 40 in the first row are used as the M selection input terminals E1 of the second delay selector 50;

[0105] The number of selection units 40 in the (x-1)th row is k, and the number of selection units 40 in the xth row is s, where s = int(k / 2) + mod(k,2), where x, k, and s are all positive integers. The xth row has one selection unit 40, and 2 ≤ x ≤ x. In the same row direction, the selector outputs d4 of the 2p-1th and 2pth selection units 40 in the (x-1)th row are connected to the first input d2 and the second input of the pth selection unit 40 in the xth row, respectively, where p is a positive integer and 1 ≤ p ≤ s. The selector outputs d4 of the 2(p+1)-1th and 2(p+1)th selection units 40 in the (y-1)th row are connected to the first input d2 and the second input of the (p+1)th selection unit 40 in the xth row, respectively.

[0106] The selector output terminal d4 of the selection unit 40 in row X is used as the selection output terminal E2 of the second delay selector 50;

[0107] The second sub-receiver a2 of all selection units 40 in the xth row is connected to the xth selection sub-receiver of the second delay selector 50; the selection unit 40 is used to control the corresponding selection sub-output to output the signal of the corresponding first input or second input according to the corresponding fifth sub-selection signal.

[0108] Specifically, the second delay selector 50 is structurally similar to the first delay selector 30, except that it contains the same number of rows of selection units 40. The first delay selector 30 includes Y rows of selection units 40, while the second delay selector 50 includes X rows of selection units 40. If M = n, then X = Y. The structure of the selection units 40 in the second delay selector 50 is the same as that in the first delay selector 30, i.e., both are... Figure 2 The selection unit 40 shown is configured such that the output signal of the second delay selector 50 is also configured to have relatively high accuracy because the selection unit 40 has relatively high accuracy.

[0109] This invention also provides a clock control circuit, also known as a clock phase control circuit, for controlling the phase of a clock signal. The clock control circuit includes: a clock distribution module and multiple phase adjustment circuits as provided in any of the above embodiments;

[0110] The clock distribution module includes an equidistant distribution unit, an anti-interference unit, a clock receiver, and multiple clock transmitters. The clock receivers are connected to each clock transmitter via the equidistant distribution unit. The equidistant distribution unit distributes the clock signal received by the clock receiver into multiple branch clock signals transmitted from each clock transmitter, and controls the total length of the signal transmission lines between the clock receiver and each clock transmitter to be the same. The anti-interference unit extends in the same direction as the signal transmission lines and is located on at least two opposite sides of the signal transmission lines. The anti-interference unit absorbs interference signals distributed on the outer surface of the signal transmission lines. A phase adjustment circuit corresponds one-to-one with each clock transmitter, and the commutation input of the phase adjustment circuit is connected to the corresponding clock transmitter.

[0111] Specifically, the clock distribution module distributes the original single clock signal into multiple high-precision phase-synchronized branch clock signals, each transmitted from a corresponding clock transmitter. A phase adjustment circuit corresponds one-to-one with each clock transmitter, and the commutation input of the phase adjustment circuit is connected to the corresponding clock transmitter. Thus, the branch clock signal from the clock transmitter serves as the delay signal for the corresponding commutation input. When the delay signal passes through the corresponding phase adjustment circuit, it can undergo 2M phase shifts at any of the n process angles. The magnitude of the phase shift can be (2u-1)T or uT, where M≥u≥1. The signal that has undergone this phase shift is output to the corresponding operator unit, which then activates the corresponding operator unit. Based on this, the embodiment of the invention achieves fine-grained phase control with multiple operator units.

[0112] This invention also provides a chip that includes the phase adjustment circuit provided in any of the above embodiments. The chip, the phase adjustment circuit, and the multi-process angle delay circuit provided in this invention all belong to the same inventive concept and can achieve the same technical effects; therefore, repeated details will not be described here.

[0113] In one embodiment of the present invention, optionally, the chip includes multiple phase adjustment circuits and multiple operator units, with each phase adjustment circuit corresponding to one of the operator units, and the commutation output terminal of the phase adjustment circuit connected to the corresponding operator unit. Thus, each operator unit is activated according to the clock signal output from its corresponding commutation output terminal; when the clock signals at the commutation output terminals of each operator unit have different delays, each operator unit is activated in a time-division multiplexing manner as a group. This embodiment of the present invention thereby achieves fine-grained phase control of multiple operator units.

[0114] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A multi-process corner delay circuit, characterized by, The first receiving end, the second receiving end, the n delay input ends, the first delay output end, the first delay selector and the n delay units, n is a positive integer, one of the delay units corresponds to a process angle, each of the delay units corresponds to a different process angle, the delay unit includes a first sub-receiving end, a signal input end, a first signal output end and a second signal output end; The first sub-receiving end of the n delay units is connected with the first receiving end, and the signal input end of the n delay units is used as the n delay input ends; The delay input end is used for receiving a to-be-delayed signal, the first receiving end is used for receiving a first selection signal; the delay unit is used for controlling the corresponding first signal output end to output a first delay signal according to the first selection signal, the first delay signal is a signal after the to-be-delayed signal is delayed by a corresponding first delay or a corresponding second delay of the process angle, the corresponding first delay of the process angle is half of the corresponding second delay of the process angle; the second signal output end is used for outputting a signal after the to-be-delayed signal is delayed by the corresponding second delay of the process angle; The first delay selector includes a selection receiving end, a selection output end and n selection input ends corresponding to the first signal output ends one by one, the selection input end of the first delay selector is connected with the corresponding first signal output end, the selection output end of the first delay selector is connected with the first delay output end, and the selection receiving end of the first delay selector is connected with the second receiving end; The second receiving end is used for receiving a second selection signal; the first delay selector is used for controlling the time when the signal of each selection input end of the first delay selector reaches the selection output end of the first delay selector to be equal, and is used for controlling the selection output end of the first delay selector to output the signal of the corresponding selection input end according to the second selection signal. The selection receiving end of the first delay selector includes Y selection sub-receiving ends, Y is a positive integer, the second selection signal includes Y second sub-selection signals, and the yth selection sub-receiving end of the first delay selector is used for receiving the yth second sub-selection signal; 2. The multi-process corner delay circuit of claim 1, wherein, The first delay selector includes Y rows of selection units distributed in sequence, and each selection unit includes a second sub-receiving end, a first input end, a second input end and a selection sub-output end; The first input end and the second input end of all the selection units in the first row are used as the n selection input ends of the first delay selector; ​ The number of the selection units in the y-1th row is k, the number of the selection units in the yth row is s, s = int(k / 2) + mod(k, 2), y, k and s are positive integers, the yth row has one selection unit, 2 ≤ y ≤ Y; in the same row direction, the selection sub-output terminals of the 2p-1th and the 2pth selection units in the y-1th row are connected with the first input terminal and the second input terminal of the pth selection unit in the yth row respectively, p is a positive integer and 1 ≤ p ≤ s; the selection sub-output terminals of the 2(p+1)-1th and the 2(p+1)th selection units in the y-1th row are connected with the first input terminal and the second input terminal of the (p+1)th selection unit in the yth row respectively; The selection sub-output terminals of the selection units in the Yth row are the selection output terminals of the first delay selector; The second sub-receiving terminals of all the selection units in the yth row are connected with the yth selection sub-receiving terminal of the first delay selector; the selection units are used for controlling the selection sub-output terminals to output the signals of the first input terminals or the second input terminals according to the corresponding second sub-selection signals.

3. The multi-process corner delay circuit according to claim 1 or 2, characterized by, The delay unit comprises a first buffer, a second buffer and the selection unit, the selection unit comprises a second sub-receiving terminal, a first input terminal, a second input terminal and a selection sub-output terminal; The input terminal of the first buffer is the signal input terminal, the output terminal of the first buffer is connected with the first input terminal of the selection unit, the input terminal of the second buffer is connected with the output terminal of the first buffer, the output terminal of the second buffer is connected with the second input terminal of the selection unit, the second sub-receiving terminal of the selection unit is the first sub-receiving terminal, and the selection sub-output terminal of the selection unit is the first signal output terminal; the output terminal of the second buffer is the second signal output terminal; The delay size of the first buffer and the characteristic information of the signal transmission line between the input terminal of the first buffer and the input terminal of the second buffer jointly determine the first delay corresponding to the process angle, and the characteristic information comprises the length of the signal transmission line.

4. The multi-process corner delay circuit of claim 3, wherein, The selection unit comprises a first selection element, a second selection element, a third selection element, a fourth selection element and an inverting element; The first sub-input terminal of the first selection element is the first input terminal of the selection unit, the second sub-input terminal of the first selection element is the second input terminal of the selection unit, the third sub-input terminal of the first selection element is the second sub-receiving terminal of the selection unit, and the output terminal of the first selection element is the selection sub-output terminal of the selection unit; The first sub-input terminal of the second selection element is connected with the second sub-input terminal of the first selection element, the second sub-input terminal of the second selection element is connected with the first sub-input terminal of the first selection element, and the third sub-input terminal of the second selection element is connected with the third sub-input terminal of the first selection element; The first sub-input end of the third selection element is connected with the first sub-input end of the first selection element, the second sub-input end of the third selection element is connected with the second sub-input end of the first selection element, and the third sub-input end of the third selection element is connected with the third sub-input end of the first selection element through the inverting element; The first sub-input end of the fourth selection element is connected with the second sub-input end of the first selection element, the second sub-input end of the fourth selection element is connected with the first sub-input end of the first selection element, and the third sub-input end of the fourth selection element is connected with the third sub-input end of the first selection element through the inverting element.

5. A phase adjustment circuit, characterized by, The multi-process angle delay circuit comprises a third receiving end, a fourth receiving end, a fifth receiving end, a commutation input end, a commutation output end, a second delay selector and M multi-process angle delay circuits as claimed in any one of claims 1-4, wherein M is a positive integer. The number of the delay units arranged in each of the multi-process angle delay circuits is the same, and each of the multi-process angle delay circuits further comprises n second delay output ends, and the delay unit further comprises a second signal output end, and the second signal output ends of the n delay units serve as the n second delay output ends, wherein the second signal output end of the delay unit is used for outputting a signal after the second delay of the corresponding process angle of the to-be-delayed signal. The M multi-process angle delay circuits are connected in series one by one, wherein the n delay input ends of the first multi-process angle delay circuit are connected to serve as the commutation input end, the n second delay output ends of the m-1 multi-process angle delay circuit are connected with the n delay input ends of the m multi-process angle delay circuit one by one, M≥m≥2, the first receiving ends of the M multi-process angle delay circuits are connected to serve as the third receiving end, the second receiving ends of the M multi-process angle delay circuits are connected to serve as the fourth receiving end, and m is a positive integer. The second delay selector comprises a selection receiving end, a selection output end and M selection input ends corresponding to the first delay output ends one by one, the selection input end of the second delay selector is connected with the corresponding first delay output end, the selection output end of the second delay selector is connected with the commutation output end, and the selection receiving end of the second delay selector is connected with the fifth receiving end. The fifth receiving end is used for receiving a third selection signal, the second delay selector is used for controlling the time when the signals of each selection input end of the second delay selector reach the selection output end of the first delay selector to be equal, and is used for controlling the selection output end of the second delay selector to output the signal of the corresponding selection input end according to the third selection signal.

6. The phase adjustment circuit of claim 5, wherein, The selection receiving end of the second delay selector comprises X selection sub-receiving ends, X is a positive integer, the third selection signal comprises X third sub-selection signals, the xth selection sub-receiving end of the second delay selector is used for receiving the xth third sub-selection signal, x is a positive integer; The second delay selector comprises X rows of selection units distributed in sequence, the selection unit comprises a second sub-receiving end, a first input end, a second input end and a selection sub-output end; The first input end and the second input end of all the selection units in the first row serve as M selection input ends of the second delay selector; The number of the selection units in the x-1th row is k, the number of the selection units in the xth row is s, s=int(k / 2)+mod(k,2), x, k and s are all positive integers, the Xth row has one selection unit, 2≤x≤X; in the same row direction, the selection sub-output ends of the 2p-1th and 2pth selection units in the x-1th row are connected with the first input end and the second input end of the pth selection unit in the xth row respectively, p is a positive integer and 1≤p≤s; the selection sub-output ends of the 2(p+1)-1th and 2(p+1)th selection units in the x-1th row are connected with the first input end and the second input end of the (p+1)th selection unit in the xth row respectively; The selection sub-output end of the selection unit in the Xth row serves as the selection output end of the second delay selector; The second sub-receiving end of all the selection units in the xth row is connected with the xth selection sub-receiving end of the second delay selector; the selection unit is used for controlling the corresponding selection sub-output end to output the signal of the corresponding first input end or second input end according to the corresponding third sub-selection signal.

7. The phase adjustment circuit of claim 6, wherein, The selection unit comprises a first selection element, a second selection element, a third selection element, a fourth selection element and an inverting element; The first sub-input end of the first selection element serves as the first input end of the selection unit, the second sub-input end of the first selection element serves as the second input end of the selection unit, the third sub-input end of the first selection element serves as the second sub-receiving end of the selection unit, and the output end of the first selection element serves as the selection sub-output end of the selection unit; The first sub-input end of the second selection element is connected with the second sub-input end of the first selection element, the second sub-input end of the second selection element is connected with the first sub-input end of the first selection element, and the third sub-input end of the second selection element is connected with the third sub-input end of the first selection element; The first sub-input end of the third selection element is connected with the first sub-input end of the first selection element, the second sub-input end of the third selection element is connected with the second sub-input end of the first selection element, and the third sub-input end of the third selection element is connected with the third sub-input end of the first selection element through the inverting element; The first sub-input end of the fourth selection element is connected with the second sub-input end of the first selection element, the second sub-input end of the fourth selection element is connected with the first sub-input end of the first selection element, and the third sub-input end of the fourth selection element is connected with the third sub-input end of the first selection element through the inverting element.

8. A clock control circuit for controlling the phase of a clock signal, characterized by The phase adjustment circuit comprises a clock distribution module and a plurality of phase adjustment circuits as claimed in any one of claims 5 to 7. The clock distribution module comprises an equidistant distribution unit, an anti-interference unit, a clock receiving end and a plurality of clock sending ends. The clock receiving end is connected with each clock sending end through the equidistant distribution unit, the equidistant distribution unit is used to distribute the clock signal received by the clock receiving end into a plurality of branch clock signals respectively sent from each clock sending end, and is used to control the total length of the signal transmission line between the clock receiving end and each clock sending end to be the same; The extension direction of the anti-interference unit is the same as the extension direction of the signal transmission line, the anti-interference unit is arranged on at least two opposite sides of the signal transmission line, and the anti-interference unit is used to absorb the interference signal distributed on the outer surface of the signal transmission line; The phase adjustment circuit corresponds to the clock sending end one by one, and the commutation input end of the phase adjustment circuit is connected with the corresponding clock sending end.

9. A chip, characterized by The phase adjustment circuit comprises a clock distribution module and a plurality of phase adjustment circuits as claimed in any one of claims 5 to 7.

10. The chip of claim 9, wherein, Further comprising a plurality of operator units; The phase adjustment circuit is a plurality of phase adjustment circuits, the phase adjustment circuit corresponds to the operator unit one by one, and the commutation output end of the phase adjustment circuit is connected with the corresponding operator unit.

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