Method of calibrating output current, current control system and voltage control system

Abstract

The method for calibrating output current includes a first sorting operation of a plurality of first current sources according to the current intensity output by the first current sources, a second sorting operation of a plurality of second current sources according to the current intensity output by the second current sources, establishing a first switching sequence of the first current sources according to the result of the first sorting operation, and establishing a second switching sequence of the second current sources according to the result of the second sorting operation and the first switching sequence. The first current sources have the same first target current intensity, and the second current sources have the same second target current intensity.

Description

TECHNICAL FIELD

[0001] The present application relates to a method, in particular, to a method for calibrating output current and related current and voltage control system. BACKGROUND

[0002] A digital to analog converter (DAC) can convert an input signal in digital form to an output signal in analog form. For example, a digital to analog converter can generate a current of corresponding size as an output signal according to the value of a digital signal. In the prior art, a digital to analog converter can include a plurality of current sources, and can enable a corresponding number of current sources according to the desired output current value. However, due to process differences, different current sources, even with the same target current value, may actually have different current sizes, and this difference results in poor linearity between the analog output current signal and the digital input value signal.

[0003] In addition, in the application of communication transmission, the signal transceiver circuit often uses a digital to analog converter to convert a digital signal to a current signal output. Since the signal transmitted by the signal transceiver circuit itself will generate echo noise in the transmission channel, in order to reduce the influence of echo noise on signal transmission quality, an echo canceller is often used to detect echo noise in the transmission channel, and output an inverse echo compensation signal to weaken the echo noise in the transmission channel. However, if the digital to analog converters used by the signal transceiver circuit and the echo canceller are not matched, for example, they have different integral non-linearity (INL) trends when outputting a step current, which will cause the waveform of the echo compensation signal to be different from the waveform of the echo noise, resulting in poor echo cancellation effect, or even new noise. Therefore, how to properly calibrate different current sources to improve the matching degree of their output currents is still a problem to be solved. SUMMARY

[0004] An embodiment of the present application provides a method for calibrating output current, including performing a first sorting operation on a plurality of first current sources according to the current size output by the first current sources, performing a second sorting operation on a plurality of second current sources according to the current size output by the second current sources, formulating a first switching sequence of the first current sources according to the result of the first sorting operation, and formulating a second switching sequence of the second current sources according to the result of the second sorting operation and the first switching sequence. Wherein the first current sources have the same first target current intensity, and the second current sources have the same second target current intensity.

[0005] Another embodiment of the present application provides a current control system. The current control system includes a first current output circuit, a second current output circuit, and a control circuit. The first current output circuit includes a plurality of first current sources having a same first target current intensity. The second current output circuit includes a plurality of second current sources having a same second target current intensity. The control circuit is coupled to the first current output circuit and the second current output circuit. The control circuit is configured to perform a first sorting operation on the first current sources according to current intensities output by the first current sources, perform a second sorting operation on the second current sources according to current intensities output by the second current sources, determine a first switching sequence of the first current sources according to a result of the first sorting operation, and determine a second switching sequence of the second current sources according to a result of the second sorting operation and the first switching sequence.

[0006] Another embodiment of the present application provides a voltage control system. The voltage control system includes a first voltage output circuit, a second voltage output circuit, and a control circuit. The first voltage output circuit includes a plurality of first voltage dividing units having a same first target voltage dividing value. The second voltage output circuit includes a plurality of second voltage dividing units having a same second target voltage dividing value. The control circuit is coupled to the first voltage output circuit and the second voltage output circuit. The control circuit is configured to perform a first sorting operation on the first voltage dividing units according to voltage dividing values output by the first voltage dividing units, perform a second sorting operation on the second voltage dividing units according to voltage dividing values output by the second voltage dividing units, determine a first switching sequence of the first voltage dividing units according to a result of the first sorting operation, and determine a second switching sequence of the second voltage dividing units according to a result of the second sorting operation and the first switching sequence.

[0007] The method of calibrating output current, the current control system, and the voltage control system of the present application can make the integral nonlinear curves of two current output circuits or two voltage output circuits have similar variation trends, thereby improving the matching degree of the two current output circuits. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to make the above and other purposes, features, advantages and embodiments of the present application more apparent, the following describes the drawings:

[0009] Figure 1 FIG. 1 is a schematic diagram of a current control system according to an embodiment of the present application.

[0010] Figure 2 FIG. 2 is a schematic diagram of the first current output circuit and the second current output circuit of FIG. 1 under a certain switching sequence. Figure 1 FIG. 3 is a schematic diagram of the first current output circuit and the second current output circuit of FIG. 1 under another switching sequence. FIG. 4 is a schematic diagram of a voltage control system according to an embodiment of the present application.

[0011] Figure 3 are integral non-linear plots of the first current output circuit and the second current output circuit under the same specific switching sequence. Figure 2

[0012] Figure 4 is a flowchart of a method of calibrating an output current according to an embodiment of the present application.

[0013] Figure 5 Figure 6 and Figure 7 are integral non-linear plots of the first current output circuit and the second current output circuit under different switching sequences.

[0014] Figure 8 is a schematic diagram of a current control system according to another embodiment of the present application.

[0015] Figure 9 is a schematic diagram of a voltage control system according to another embodiment of the present application. DETAILED DESCRIPTION

[0016] Figure 1 is a schematic diagram of a current control system 100 according to an embodiment of the present application. The current control system 100 can include a first current output circuit 110, a second current output circuit 120, and a control circuit 130. The control circuit 130 can be coupled to the first current output circuit 110 and the second current output circuit 120.

[0017] In this embodiment, the first current output circuit 110 can include N first current sources CSA1-CSAN (some of which are omitted in the figure), and the second current output circuit 120 can include N second current sources CSB1-CSBN (some of which are omitted in the figure), where N can be an integer greater than 1. Although the first current sources CSA1-CSAN have the same target current strength, process errors can cause the actual currents generated by the first current sources CSA1-CSAN to deviate from their target current strength by different amounts. Similarly, although the second current sources CSB1-CSBN have the same target current strength, process errors can cause the actual currents generated by the second current sources CSB1-CSBN to deviate from their target current strength by different amounts.

[0018] ​​In this case, the sequence of switching the first current sources CSA1-CSAN by the first current output circuit 110 and the sequence of switching the second current sources CSB1-CSBN by the second current output circuit 120 affect the matching degree of the two in outputting currents. For the convenience of understanding, in this embodiment, the first current sources CSA1-CSAN are numbered in sequence according to the currents outputted thereby from small to large, that is, the current outputted by the first current source CSA2 can be greater than the current outputted by the first current source CSA1, the current outputted by the first current source CSA3 can be greater than the current outputted by the first current source CSA2, and the current outputted by the first current source CSAN can be greater than the currents outputted by all the first current sources CSA1-CSA(N-1) (omitted in the figure). Similarly, the second current sources CSB1-CSBN are also numbered in sequence according to the currents outputted thereby from small to large.

[0019] Figure 2 In some embodiments, the first current output circuit 110 and the second current output circuit 120 output the current sizes corresponding to each step encoding according to a certain switching sequence, and Figure 3 In some embodiments, according to the certain switching sequence, Figure 2 the integral non-linear curve INL1 of the first current output circuit 110 and the integral non-linear curve INL2 of the second current output circuit 120.

[0020] In Figure 2 , the dashed line represents the current intensity outputted by the first current output circuit 110 corresponding to each step encoding; the dash-dot line represents the current intensity outputted by the second current output circuit 120 corresponding to each step encoding; and the solid line represents the target current intensity that the first current output circuit 110 and the second current output circuit 120 should output under ideal conditions corresponding to each step encoding. In Figure 2 , the target current intensity of the first current sources CSA1-CSAN is the same as the target current intensity of the second current sources CSB1-CSBN, but the present application is not limited thereto.

[0021] In Figure 2 , corresponding to each step encoding, the first current output circuit 110 sequentially enables the first current sources CSAN, CSA(N-1), …, CSA3, CSA2 to CSA1 to gradually increase the total amount of the outputted currents, in which case, the difference between the total amount of the currents outputted by the first current output circuit 110 corresponding to each step encoding and the current intensity that should be outputted under ideal conditions corresponding to each step encoding gradually increases and then gradually decreases, as shown in Figure 3the integral non-linear curve INL1 in FIG. 1. In contrast, the second current output circuit 120 sequentially enables the second current sources CSB1, CSB2, CSB3,..., CSBN to gradually increase the total current output corresponding to each step code, so the difference between the total current output by the second current output circuit 120 corresponding to each step code and the ideal current intensity corresponding to each step code gradually increases and then gradually decreases in a negative direction, as shown by the integral non-linear curve INL2 in FIG. 1. Figure 3

[0022] According to Figure 3 It can be seen that, under a specific switching sequence, the integral non-linear curve INL1 of the first current output circuit 110 and the integral non-linear curve INL2 of the second current output circuit 120 will have a reverse variation trend. That is, as the step code changes, the difference between the total current output by the first current output circuit 110 and the second current output circuit 120 will also increase and decrease, resulting in a mismatch. In some embodiments, the first current output circuit 110 and the second current output circuit 120 can be applied to different but related circuits, for example, the first current output circuit 110 can be applied to a digital-to-analog conversion circuit in a signal transceiver, and the second current output circuit 120 can be applied to a digital-to-analog conversion circuit in a echo canceller. In this case, if the signal transceiver uses the first current output circuit 110 to generate a signal output, and the echo canceller uses the second current output circuit 120 to generate an echo compensation signal, even if the echo canceller can accurately detect echo noise, the effect of the echo compensation signal generated by the second current output circuit 120 will be very unstable, and there will be overcompensation or undercompensation. In this way, not only can the echo noise not be effectively eliminated, but even additional and uncontrollable noise can be generated.

[0023] To solve this problem, the control circuit 130 can control the switching sequence of the current sources in the first current output circuit 110 and the second current output circuit 120, so that the currents output by the first current output circuit 110 and the second current output circuit 120 can be more matched. Figure 4 FIG. 2 is a flowchart of a method 200 for calibrating an output current according to an embodiment of the present application. In some embodiments, the method 200 can be applied to the current control system 100. The method 200 can include steps S210-S240.

[0024] S210: performing a first sorting operation on the first current sources CSA1-CSAN according to the current size output by the first current sources CSA1-CSAN;

[0025] ​S220: performing a second sorting operation on the second current sources CSB1-CSBN according to the current magnitudes outputted by the second current sources CSB1-CSBN;

[0026] S230: formulating a first switching sequence of the first current sources CSA1-CSAN according to the result of the first sorting operation; and

[0027] S240: formulating a second switching sequence of the second current sources CSB1-CSBN according to the result of the second sorting operation and the first switching sequence.

[0028] Although in this embodiment, the first current sources CSA1-CSAN and the second current sources CSB1-CSBN are numbered sequentially according to the current magnitudes outputted by them, in actual applications of the current control system 100, the current magnitudes outputted by the current sources in the first current output circuit 110 and the second current output circuit 120 are generally unknown and unpredictable, thus the control circuit 130 can first perform the first sorting operation on the first current sources CSA1-CSAN and the second sorting operation on the second current sources CSB1-CSBN in steps S210 and S220. Then, the control circuit 130 can formulating the switching sequence of the first current sources CSA1-CSAN according to the result of the first sorting operation in step S230, and formulating the switching sequence of the second current sources CSB1-CSBN according to the result of the second sorting operation and the switching sequence of the first current sources CSA1-CSAN in step S240.

[0029] In some embodiments, the control circuit 130 can arbitrarily formulating the switching sequence of the first current sources CSA1-CSAN, and apply the sorting of the current magnitudes outputted by the first current sources CSA1-CSAN and their corresponding switching sequence to the second current sources CSB1-CSBN. In this way, the integral nonlinear curve of the first current output circuit 110 and the integral nonlinear curve of the second current output circuit 120 will have quite similar variation trends, thus improving the matching degree of the first current output circuit 110 and the second current output circuit 120.

[0030] For example, in the first sub-embodiment of the present application, in step S230, the control circuit 130 can set the first switching sequence of the first current source CSA1~CSAN whose current size is ranked in the median of the median current source, and set the switching sequence of other first current sources in a symmetrical manner with the median current source as a reference. For the convenience of the reader, the first sub-embodiment is described with N=7. In this case, the control circuit 130 can set the first switching sequence of the first current source CSA4 whose current size is ranked in the median of the first current sources CSA1~CSA7. Furthermore, the control circuit 130 can set the second switching sequence of the first current source CSA5 whose output current size is closest to and greater than the current outputted by the first current source CSA4, and set the third switching sequence of the first current source CSA3 whose output current size is closest to and less than the current outputted by the first current source CSA4, and so on. That is, the first current output circuit 110 will enable the first current sources CSA1~CSA7 in the order of CSA4, CSA5, CSA3, CSA6, CSA2, CSA7 and CSA1. In this way, in the process of gradually increasing the step current, the error value of the first current source CSA5 greater than the first target current can be compensated by the error value of the first current source CSA3 less than the first target current, and the error value of the first current source CSA6 greater than the first target current can be compensated by the error value of the first current source CSA2 less than the first target current, so that the integral non-linear error value of the first current output circuit 110 can be suppressed without continuously accumulating upward.

[0031] Similarly, the control circuit 130 can arrange the second current sources CSB2-CSB7 in order of the current magnitude according to the result of the second sorting operation and the switching order of the first current sources CSA1-CSA7. The second median current source CSB4, which outputs a current magnitude closest to the second median, is set to have a first switching order. Further, the control circuit 130 can cause the second current source CSB5, which outputs a current magnitude closest to and greater than the current outputted by the second median current source CSB4, to have a second switching order, and cause the second current source CSB3, which outputs a current magnitude closest to and less than the current outputted by the second median current source CSB4, to have a third switching order, and so on. That is, the second current output circuit 120 enables the second current sources CSB1-CSB7 in the order of CSB4, CSB5, CSB3, CSB6, CSB2, CSB7, and CSB1. In this way, during the gradual increase of the step current, the error value of the second current source CSB5, which is greater than the second target current, can be compensated by the error value of the second current source CSB3, which is less than the second target current, and the error value of the second current source CSB6, which is greater than the second target current, can be compensated by the error value of the second current source CSB2, which is less than the second target current, and so on, so that the integral nonlinearity error value of the second current output circuit 120 can be suppressed.

[0032] Further, in some embodiments, the first current output circuit 110 can enable the first current sources CSA1-CSA7 in the order of CSA4, CSA3, CSA5, CSA2, CSA6, CSA1, and CSA7, and the second current output circuit 120 can correspondingly enable the second current sources CSB1-CSB7 in the order of CSB4, CSB3, CSB5, CSB2, CSB6, CSB1, and CSB7.

[0033] Figure 5 is the integral nonlinearity curve INL1 of the first current output circuit 110 and the integral nonlinearity curve INL2 of the second current output circuit 120 obtained according to the first sub-embodiment. Figure 5 Although the error degrees of the first current sources CSA1-CSA7 and the second current sources CSB1-CSB7 can be different, by the method 200, the integral nonlinearity curve of the first current output circuit 110 and the integral nonlinearity curve of the second current output circuit 120 can have similar variation trends, so that the matching degree of the first current output circuit 110 and the second current output circuit 120 can be improved.

[0034] In the first sub-embodiment, the control circuit 130 sets the switching sequences of the first current sources in a symmetrical manner with respect to the first median current source. However, the present application is not limited thereto. In some other embodiments, the control circuit 130 can set the switching sequences of the current sources according to other rules. For example, in the second sub-embodiment of the present application, after the first median current source CSA4 is set to have the first switching sequence, the control circuit 130 can set the switching sequences of the first current sources CSA5-CSA7 in order of their current values from small to large, for the first current sources CSA5-CSA7 whose output currents are greater than that of the first median current source CSA4. Then, the control circuit 130 can set the switching sequences of the first current sources CSA1-CSA3 in order of their current values from small to large, for the remaining first current sources CSA1-CSA3. That is, the first current output circuit 110 will enable the first current sources CSA1-CSA7 in the order of CSA4, CSA5, CSA6, CSA7, CSA1, CSA2 and CSA3.

[0035] Similarly, the control circuit 130 can set the switching sequences of the second current sources according to the same rule. For example, after the second median current source CSB4 is set to have the first switching sequence, the control circuit 130 can set the switching sequences of the second current sources CSB5-CSB7 in order of their current values from small to large, for the second current sources CSB5-CSB7 whose output currents are greater than that of the second median current source CSB4. Then, the control circuit 130 can set the switching sequences of the second current sources CSB1-CSB3 in order of their current values from small to large, for the remaining second current sources CSB1-CSB3. That is, the second current output circuit 120 will enable the second current sources CSB1-CSB7 in the order of CSB4, CSB5, CSB6, CSB7, CSB1, CSB2 and CSB3.

[0036] Figure 6 The integral non-linearity curves INL1 and INL2 of the first current output circuit 110 and the second current output circuit 120, respectively, obtained according to the second sub-embodiment. In Figure 6 the integral non-linearity curve of the first current output circuit 110 first increases gradually and then decreases gradually, and the integral non-linearity curve of the second current output circuit 120 also has a similar trend, so that the matching degree of the first current output circuit 110 and the second current output circuit 120 is improved.

[0037] In some embodiments, the control circuit 130 can also arrange the switching sequence of the first current sources CSA5-CSA7 after the switching sequence of the first current sources CSA1-CSA3, and can arrange the switching sequence of the second current sources CSB5-CSB7 after the switching sequence of the second current sources CSB1-CSB3. For example, in the third sub-embodiment of the present application, the control circuit 130 can arrange the switching sequence of the first current sources CSA1-CSA3 in descending order of their current ranks after arranging the first middle current source CSA4 to have the first switching sequence. Then, the control circuit 130 can also arrange the switching sequence of the remaining first current sources CSA5-CSA7 in descending order of their current ranks. That is, the first current output circuit 110 will enable the first current sources CSA1-CSA7 in the order of the first current sources CSA4, CSA3, CSA2, CSA1, CSA7, CSA6 and CSA5. Similarly, the second current output circuit 120 will enable the second current sources CSB1-CSB7 in the order of the second current sources CSB4, CSB3, CSB2, CSB1, CSB7, CSB6 and CSB5.

[0038] Figure 7 The integral non-linearity curve INL1 of the first current output circuit 110 and the integral non-linearity curve INL2 of the second current output circuit 120 obtained according to the third sub-embodiment. In the third sub-embodiment, the integral non-linearity curve INL1 of the first current output circuit 110 will first gradually decrease and then gradually increase, and the integral non-linearity curve INL2 of the second current output circuit 120 will also have a similar trend, so that the matching degree of the first current output circuit 110 and the second current output circuit 120 can be improved. Figure 7 That is, the control circuit 130 can arrange the switching sequence of the first current sources CSA1-CSA7 according to different rules as required, as long as after the switching sequence of the first current sources CSA1-CSA7 is determined, the control circuit 130 also arranges the switching sequence of the second current sources CSB1-CSB7 according to similar rules, so that the integral non-linearity curves of the first current output circuit 110 and the second current output circuit 120 have similar trends, thereby improving the matching degree of the first current output circuit 110 and the second current output circuit 120.

[0039] Figure 8 is a schematic diagram of a current control system 300 according to an embodiment of the present application. The current control system 300 can include a first current output circuit 310, a second current output circuit 320 and a control circuit 330. The current control system 300 is similar to the current control system 100 of the first embodiment of the present application, and the difference between the current control system 300 and the current control system 100 is that the control circuit 330 of the current control system 300 can arrange the switching sequence of the first current sources CSA1-CSA7 and the second current sources CSB1-CSB7 according to different rules. Figure 1The current control system 100 has a similar structure and can also operate according to the method 200, however, in the current control system 300, the first current output circuit 310 can further include first current sources ACSA1-ACSA M and a first unit current source UCSA1, and the second current output circuit 320 can further include second current sources ACSB1-ACSBM and a second unit current source UCSB1, where M is an integer greater than 1.

[0040] In this embodiment, the first current sources ACSA1-ACSA M and the second current sources ACSB1-ACSBM can be used to provide more step current segment selections. For example, the target current intensity of the first current sources ACSA1-ACSA M can be less than the target current intensity of the first current source CSA1, and the target current intensity of the second current sources ACSB1-ACSBM can be less than the target current intensity of the second current source CSB1. In this way, the first current output circuit 310 and the second current output circuit 320 can provide smaller step currents using the first current sources ACSA1-ACSA M and the second current sources ACSB1-ACSBM.

[0041] Furthermore, in some embodiments, to accommodate the step encoding used by the current control system 300, the first current sources ACSA1-ACSAmand the first unit current source UCSA1may have the same sub-target current strength, and the target current strength of the first reference current collectively output by the first current sources ACSA1-ACSAmand the first unit current source UCSA1may be equal to the first target current strength of each of the first current sources CSA1-CSAN. Similarly, the second current sources ACSB1-ACSBmand the second unit current source UCSB1may have the same sub-target current strength, and the target current strength of the second reference current collectively output by the second current sources ACSB1-ACSBmand the second unit current source UCSB1may be equal to the second target current strength of the second current sources CSB1-CSBN. For example, if M is 7, the first target current strength of the first current source CSA1may be 8 times the first current source ACSA1(i.e., the first target current strength of a current source CSA1is 8 times the unit current), and thus when the step encoding is 7, if the first current sources ACSA1-ACSAmare all enabled, when the step encoding is 8, the first current sources ACSA1-ACSAmay all be disabled, and one of the first current sources CSA1-CSANis enabled to continue to increase the output current, and maintain the linearity of the step current. That is, in the first current output circuit 310, the first current sources CSA1-CSANmay be used to provide the most significant bits of current, and the first current sources ACSA1-ACSAmay be used to provide the least significant bits of current. Similarly, in the second current output circuit 320, the second current sources CSB1-CSBNmay be used to provide the most significant bits of current, and the second current sources ACSB1-ACSBmay be used to provide the least significant bits of current.

[0042] Since in this embodiment, the first current output circuit 310 switches between the first current sources CSA1-CSAN and the first current sources ACSA1-ACSAM when ramping up the step current, how the first current sources CSA1-CSAN with the first switch order are selected will affect the integral nonlinearity error value generated during the switching. For example, if the total current output by the first current sources ACSA1-ACSAM is less than the target current, but the first current sources CSA1-CSAN with the first switch order output more than the first target current, a large jump will be generated between the two current steps when the first current sources ACSA1-ACSAM are switched from all enabled to all disabled, and the first current sources CSA1-CSAN with the first switch order are switched from disabled to enabled to increase the output current. Conversely, if the total current output by the second current sources ACSB1-ACSBM is more than the target current, but the second current sources CSB1-CSBN with the first switch order output less than the first target current, a less noticeable jump will be generated between the two current steps when the second current sources ACSB1-ACSBM are switched from all enabled to all disabled, and the second current sources CSB1-CSBN with the first switch order are switched from disabled to enabled to increase the output current. Since the current jumps generated by the first current output circuit 310 and the second current output circuit 320 are very different when increasing the output current steps, the integral nonlinearity errors of the two circuits will also show different trends, causing the currents output by the first current output circuit 310 and the second current output circuit 320 to be mismatched.

[0043] In this case, the method 200 can cause the first current sources ACSA1-ACSAM and the first unit current source UCSA1 to jointly generate a first reference current, and in the first sorting operation of step S210, the first reference current is sorted together with the currents output by the first current sources CSA1-CSAN. Similarly, the method 200 can also cause the second current sources ACSB1-ACSBM and the second unit current source UCSB1 to jointly generate a second reference current, and in the second sorting operation of step S220, the second reference current is sorted together with the currents output by the second current sources CSB1-CSBN.

[0044] Then, in step S230, the control circuit 330 can use the first reference current as a reference to determine the switch order of the first current sources CSA1-CSAN, and in step S240, the control circuit 330 can use the second reference current as a reference according to the result of the second sorting operation, and determine the switch order of the second current sources CSB1-CSBN according to the switch order of the first current sources CSA1-CSAN.

[0045] For example, if N is 7, and the first reference current is greater than the current outputted by the first current source CSA4 and less than the current outputted by the first current source CSA5, in step S230, the control circuit 330 can make the first current source CSA5 with the output current size closest to and greater than the first reference current have the first switch order, make the first current source CSA4 with the output current size closest to and less than the first reference current have the second switch order, and so on. In this case, the first current output circuit 310 can enable the first current sources CSA1-CSA7 in the order of CSA5, CSA4, CSA6, CSA3, CSA7, CSA2 and CSA1.

[0046] Next, in step S240, if the second reference current is greater than the current outputted by the second current source CSB3 and less than the current outputted by the second current source CSB4, the control circuit 330 can make the second current source CSB4 with the output current size closest to and greater than the second reference current have the first switch order, make the second current source CSB3 with the output current size closest to and less than the second reference current have the second switch order, and so on. In this case, the second current output circuit 320 can enable the second current sources CSB1-CSB7 in the order of CSB4, CSB3, CSB5, CSB2, CSB6, CSB1 and CSB7.

[0047] In this way, in the process of the first current output circuit 310 switching between the first current sources CSA1-CSAN and the first current sources ACSA1-ACSAM and the second current output circuit 320 switching between the second current sources CSB1-CSBN and the second current sources ACSB1-ACSBM, the integral nonlinear curves of the first current output circuit 310 and the second current output circuit 320 also have similar change trends, thereby improving the matching degree of the first current output circuit 310 and the second current output circuit 320.

[0048] In the foregoing embodiment, the control circuit 330 is based on the first reference current and sets the switching order of the first current sources CSA1-CSA7 in a symmetrical manner. However, the present application is not limited thereto. In some other embodiments, the control circuit 330 can also be based on the first reference current and set the switching order of the current sources according to other rules. For example, for the first current sources CSA1-CSA7, the first current sources CSA5-CSA7 whose output currents are greater than the first reference current, the control circuit 330 can set the switching order of the first current sources CSA5-CSA7 in order from small to large according to the current order, and for the remaining first current sources CSA1-CSA4, the control circuit 330 can set the switching order of the first current sources CSA1-CSA4 in order from small to large according to the current order. That is, the first current output circuit 310 will enable the first current sources CSA1-CSA7 in the order of CSA5, CSA6, CSA7, CSA1, CSA2, CSA3, and CSA4.

[0049] Similarly, for the second current sources CSB1-CSB7, the second current sources CSB4-CSB7 whose output currents are greater than the second reference current, the control circuit 330 can set the switching order of the second current sources CSA4-CSA7 in order from small to large according to the current order, and for the remaining second current sources CSB1-CSB3, the control circuit 330 can set the switching order of the second current sources CSB1-CSB3 in order from small to large according to the current order. That is, the second current output circuit 320 will enable the second current sources CSB1-CSB7 in the order of CSB4, CSB5, CSB6, CSB7, CSB1, CSB2, and CSB3. In this case, the integral nonlinear curve of the first current output circuit 310 will first gradually rise and then gradually fall, and the integral nonlinear curve of the second current output circuit 320 will also have a similar change trend, so that the matching degree of the first current output circuit 310 and the second current output circuit 320 is improved.

[0050] However, in some other embodiments, for the first current sources CSA1-CSA7, the first current sources CSA1-CSA4 whose output currents are less than the first reference current, the control circuit 330 can set the switching order of the first current sources CSA1-CSA4 in order from large to small according to the current order, and for the remaining first current sources CSA5-CSA7, the control circuit 330 can set the switching order of the first current sources CSA5-CSA7 in order from large to small according to the current order. That is, the first current output circuit 310 will enable the first current sources CSA1-CSA7 in the order of CSA4, CSA3, CSA2, CSA1, CSA7, CSA6, and CSA5.

[0051] Similarly, for the second current sources CSB1-CSB7, the control circuit 330 can sequentially set the switch order of the second current sources CSB1-CSB3 in descending order of their current ranks, and sequentially set the switch order of the second current sources CSB4-CSB7 in descending order of their current ranks. That is, the second current output circuit 320 can enable the second current sources CSB1-CSB7 in the order of CSB3, CSB2, CSB1, CSB7, CSB6, CSB5 and CSB4. In this case, the integral non-linear curve of the first current output circuit 310 can first gradually decrease and then gradually increase, and the integral non-linear curve of the second current output circuit 320 can also have a similar change trend, so that the matching degree of the first current output circuit 310 and the second current output circuit 320 is improved.

[0052] In addition, the operation principle of the current control system 100 in the foregoing embodiments for controlling the first current output circuit 110 and the second current output circuit 120 can also be applied to a voltage output circuit. Figure 9 FIG. 4 is a schematic diagram of a voltage control system 400 according to an embodiment of the present application. The voltage control system 400 can include a first voltage output circuit 410, a second voltage output circuit 420, and a controller 430 coupled to the first voltage output circuit 410 and the second voltage output circuit 420.

[0053] In this embodiment, the first voltage output circuit 410 can include N first voltage dividing units VSA1-VSAN (some of which are omitted in the figure), and the second voltage output circuit 420 can include N second voltage dividing units VSB1-VSBN (some of which are omitted in the figure), where N can be an integer greater than 1. Although the first voltage dividing units VSA1-VSAN have the same target voltage dividing value, process errors can cause the actual voltage dividing values of the first voltage dividing units VSA1-VSAN to deviate from the target voltage dividing value to different degrees. Similarly, although the second voltage dividing units VSB1-VSBN have the same target voltage dividing value, process errors can cause the actual voltage dividing values of the second voltage dividing units VSB1-VSBN to deviate from the target voltage dividing value to different degrees.

[0054] In Figure 9In one embodiment, each of the first voltage dividing units VSA1-VSAN and each of the second voltage dividing units VSB1-VSBN can have the same structure. For example, the first voltage dividing unit VSA1 can include a voltage dividing resistor RA1 and can be coupled to other first voltage dividing units VSA2-VSAN through switch circuits S1 and S2. In addition, the voltage dividing resistor RA1 can be selectively coupled to the operating voltage VDD and the reference voltage VSS through switches. In this case, the controller 430 can control whether the first voltage dividing unit VSA1 of the first voltage dividing units VSA1-VSAN needs to be connected to the operating voltage VDD and the reference voltage VSS and can control the switch circuits S1 and S2 to set a series connection order of the voltage dividing resistors RA1-RAN in the first voltage dividing units VSA1-VSAN between the operating voltage VDD and the reference voltage VSS, so that the first voltage dividing units VSA1-VSAN can provide stepped voltages in a desired order. For example, the controller 430 can cause the voltage dividing resistor RAN to receive the operating voltage VDD and the voltage dividing resistor RA1 to receive the reference voltage VSS and can control the switch circuits S1 and S2 in the first voltage dividing units VSA1-VSAN so that the voltage dividing resistors RA1-RAN are connected in the order of RA1, RA2, RA3,..., and RAN. In this case, the first voltage dividing unit VSA1 will have a first series connection order, and the voltage dividing resistor RA1 can be used to provide a first stepped voltage between the operating voltage VDD and the reference voltage VSS, the first voltage dividing unit VSA2 will have a second series connection order, and the voltage dividing resistor RA2 can be used to provide a second stepped voltage between the operating voltage VDD and the reference voltage VSS, and so on.

[0055] However, the controller 430 can cause the voltage dividing resistor RAN to receive the operating voltage VSS and the voltage dividing resistor RA1 to receive the operating voltage VDD and can control the switch circuits S1 and S2 in the first voltage dividing units VSA1-VSAN so that the voltage dividing resistors RA1-RAN are connected in the order of RAN, RA2,..., and RA1. In this case, the first voltage dividing unit VSA1 will have a first series connection order, and the voltage dividing resistor RAN can be used to provide a first stepped voltage between the operating voltage VDD and the reference voltage VSS, the first voltage dividing unit VSA2 will have a second series connection order, and the voltage dividing resistor RA2 can be used to provide a second stepped voltage between the operating voltage VDD and the reference voltage VSS, and so on. In this case, the first voltage dividing unit VSA1 will have an Nth series connection order, and the voltage dividing resistor RA1 can be used to provide an Nth stepped voltage between the operating voltage VDD and the reference voltage VSS.

[0056] Similarly, the controller 430 can control whether the second voltage dividing units VSB1-VSBN are connected to the operating voltage VDD and the reference voltage VSS, and can control the switch circuits S1 and S2 to set the series connection order of the voltage dividing resistors RB1-RBN in the second voltage dividing units VSB1-VSBN between the operating voltage VDD and the reference voltage VSS, so that the second voltage dividing units VSB1-VSBN can provide stepped voltage division in the desired order.

[0057] Although the voltage dividing resistors RA1-RAN can have the same target resistance value, in practice, the voltage dividing resistors RA1-RAN can still have some differences, resulting in some differences in the voltage division provided by each of the first voltage dividing units VSA1-VSAN. Similarly, there can be some differences in the voltage division provided by each of the second voltage dividing units VSB1-VSBN.

[0058] In this case, the series connection order of the first voltage dividing units VSA1-VSAN in the first voltage output circuit 410 and the series connection order of the second voltage dividing units VSB1-VSBN in the second voltage output circuit 42 affect the degree of matching between the two in the output voltage. For ease of understanding, in this embodiment, the first voltage dividing units VSA1-VSAN are numbered in order from small to large according to the voltage division they output, that is, the voltage division output by the first voltage dividing unit VSA2 can be greater than the voltage division output by the first voltage dividing unit VSA1, the voltage division output by the first voltage dividing unit VSA3 can be greater than the voltage division output by the first voltage dividing unit VSA2, and the voltage division output by the first voltage dividing unit VSAN can be greater than the voltage division output by all of the first voltage dividing units VSA1-VSA(N-1) (omitted in the figure). Similarly, the second voltage dividing units VSB1-VSBN are also numbered in order from small to large according to the voltage division they output.

[0059] After the controller 430 performs the first sorting operation on the first voltage dividing units VSA1-VSAN according to the voltage division values output by the first voltage dividing units VSA1-VSAN, the controller 430 can determine the first series connection order of the first voltage dividing units VSA1-VSAN according to the result of the first sorting operation. In addition, the controller 430 can perform a second sorting operation on the second voltage dividing units VSB1-VSBN according to the voltage division values output by the second voltage dividing units VSB1-VSBN, and determine the second series connection order of the second voltage dividing units VSB1-VSBN according to the result of the second sorting operation and the first series connection order.

[0060] In the fourth sub-embodiment of the present invention, if N is 7, the control circuit 430 can set the first median voltage divider unit VSA4, whose voltage division magnitude is the median among the first voltage divider units VSA1 to VSA7, to have a first series connection order. Furthermore, the control circuit 430 can assign a second series connection order to the first voltage divider unit VSA5, whose output voltage division magnitude is closest to and greater than that output by the first median voltage divider unit VSA4, and a third series connection order to the first voltage divider unit VSA3, whose output voltage division magnitude is closest to and less than that output by the first median voltage divider unit VSA4, and so on. That is, the first voltage output circuit 410 will connect the first voltage divider units VSA1 to VSA7 in series according to the order of the first voltage divider units VSA4, VSA5, VSA3, VSA6, VSA2, VSA7, and VSA1. In this way, as the step voltage gradually increases, the first voltage divider units VSA4, VSA5, VSA3, VSA6, VSA2, VSA7 and VSA1 will sequentially provide voltage division. Therefore, the error value of the first voltage divider unit VSA5 being greater than the first target voltage can compensate for the error value of the first voltage divider unit VSA3 being less than the first target voltage, and the error value of the first voltage divider unit VSA6 being greater than the first target voltage can compensate for the error value of the first voltage divider unit VSA2 being less than the first target voltage. This allows the integral nonlinearity error value of the first voltage output circuit 410 to be suppressed and not to continue to accumulate and increase.

[0061] Similarly, the control circuit 430 can, based on the result of the second sorting operation and the series sequence of the first voltage divider units VSA1 to VSA7, set the second median voltage divider unit VSB4, whose voltage division value is the median among the second voltage divider units VSB2 to VSB7, to have a first series sequence. Furthermore, the control circuit 430 can assign a second series sequence to the second voltage divider unit VSB5, whose output voltage division value is closest to and greater than the output voltage of the second median voltage divider unit VSB4, and assign a third series sequence to the second voltage divider unit VSB3, whose output voltage division value is closest to and less than the output voltage of the second median voltage divider unit VSB4, and so on. In other words, the second voltage output circuit 120 will connect the second voltage divider units VSB1 to VSB7 in series according to the order of the second voltage divider units VSB4, VSB5, VSB3, VSB6, VSB2, VSB7, and VSB1. In this way, as the step voltage gradually increases, the error value of the second voltage divider unit VSB5 being greater than the second target voltage can compensate for the error value of the second voltage divider unit VSB3 being less than the second target voltage. Similarly, the error value of the second voltage divider unit VSB6 being greater than the second target voltage can compensate for the error value of the second voltage divider unit VSB2 being less than the second target voltage, and so on, so that the integral nonlinearity error value of the second voltage output circuit 420 can be suppressed.

[0062] In the fourth sub-embodiment, the integral non-linear curve of the first voltage output circuit 410 and the integral non-linear curve of the second voltage output circuit 420 are similar. That is, by the aforementioned operation manner, the voltage output system 400 can make the integral non-linear curve of the first voltage output circuit 410 and the integral non-linear curve of the second voltage output circuit 420 have similar variation trends, thereby improving the matching degree of the first voltage output circuit 410 and the second voltage output circuit 420. In addition, in some embodiments, the first voltage output circuit 410 can also connect the first voltage dividing units VSA1-VSA7 in the order of the first voltage dividing units VSA4, VSA3, VSA5, VSA2, VSA6, VSA1 and VSA7, and the second voltage output circuit 120 can also correspondingly connect the second voltage dividing units VSB1-VSB7 in the order of the second voltage dividing units VSB4, VSB3, VSB5, VSB2, VSB6, VSB1 and VSB7.

[0063] In the fourth embodiment, the control circuit 430 can take the first median voltage dividing unit VS4 as a reference and set the connection order of each first voltage dividing unit in a symmetrical manner, but the present application is not limited thereto. In some other embodiments, the control circuit 130 can set the connection order of each voltage dividing unit according to other rules. For example, in the fifth sub-embodiment of the present application, after the first median voltage dividing unit VSA4 is made to have the first connection order, for the first voltage dividing units VSA5-VSA7 whose output voltages are greater than the output voltage of the first median voltage dividing unit VSA4, the control circuit 430 can set the connection order of the first voltage dividing units VSA5-VSA7 in order from small to large according to the voltage dividing order. Then, for the remaining first voltage dividing units VSA1-VSA3, the control circuit 430 can also set the connection order of the first voltage dividing units VSA1-VSA3 in order from small to large according to the voltage dividing order. That is, the first voltage output circuit 410 will connect the first voltage dividing units VSA1-VSA7 in the order of the first voltage dividing units VSA4, VSA5, VSA6, VSA7, VSA1, VSA2 and VSA3.

[0064] Similarly, the control circuit 430 can determine the series connection order of the second voltage dividing units VSB1-VSB7 according to the same rule. For example, the control circuit 430 can set the series connection order of the second voltage dividing units VSB5-VSB7 in order from small to large according to the voltage ranking of the second voltage dividing units VSB5-VSB7 after the second middle voltage dividing unit VSB4 has the first switch order. Then, the control circuit 430 can also set the series connection order of the second voltage dividing units VSB1-VSB3 in order from small to large according to the voltage ranking of the second voltage dividing units VSB1-VSB3. That is, the second voltage output circuit 420 will connect the second voltage dividing units VSB1-VSB7 in the order of VSB4, VSB5, VSB6, VSB7, VSB1, VSB2, and VSB3.

[0065] In the fifth embodiment, the integral non-linear curve of the first voltage output circuit 410 and the integral non-linear curve of the second voltage output circuit 420 can have similar variation trends as the integral non-linear curve INL1 of the first current output circuit 110 and the integral non-linear curve INL2 of the second current output circuit 120 in the first embodiment. Figure 6

[0066] ​In some embodiments, the control circuit 430 can also arrange the series order of the first voltage dividing units VSA5 to VSA7 after the series order of the first voltage dividing units VSA1 to VSA3, and can arrange the series order of the second voltage dividing units VSB5 to VSB7 after the series order of the second voltage dividing units VSB1 to VSB3. For example, in the sixth sub-embodiment of the present application, the control circuit 430 can arrange the series order of the first voltage dividing units VSA1 to VSA3 in descending order of their output voltages after arranging the first voltage dividing unit VSA4 to have the first series order. Then, the control circuit 430 can also arrange the series order of the remaining first voltage dividing units VSA5 to VSA7 in descending order of their output voltages. That is, the first voltage output circuit 410 will connect the first voltage dividing units VSA1 to VSA7 in the order of VSA4, VSA3, VSA2, VSA1, VSA7, VSA6 and VSA5. Similarly, the second voltage output circuit 420 will connect the second voltage dividing units VSB1 to VSB7 in the order of VSB4, VSB3, VSB2, VSB1, VSB7, VSB6 and VSB5.

[0067] In the fifth embodiment, the integral non-linearity curve of the first voltage output circuit 410 and the integral non-linearity curve of the second voltage output circuit 420 will have similar variation trends as the integral non-linearity curve INL1 of the first current output circuit 110 and the integral non-linearity curve INL2 of the second current output circuit 120 in the first embodiment. Figure 7 That is, the control circuit 430 can arrange the series order of the first voltage dividing units VSA1 to VSA7 according to different rules as required, as long as the control circuit 430 also arranges the series order of the second voltage dividing units VSB1 to VSB7 according to similar rules after the series order of the first voltage dividing units VSA1 to VSA7 is determined, so that the integral non-linearity curves of the first voltage output circuit 410 and the second voltage output circuit 420 have similar variation trends, thereby improving the matching degree of the first voltage output circuit 410 and the second voltage output circuit 420.

[0068] That is, the control circuit 430 can arrange the series order of the first voltage dividing units VSA1 to VSA7 according to different rules as required, as long as the control circuit 430 also arranges the series order of the second voltage dividing units VSB1 to VSB7 according to similar rules after the series order of the first voltage dividing units VSA1 to VSA7 is determined, so that the integral non-linearity curves of the first voltage output circuit 410 and the second voltage output circuit 420 have similar variation trends, thereby improving the matching degree of the first voltage output circuit 410 and the second voltage output circuit 420.

[0069] In summary, the current control system and the method for calibrating output current provided by the embodiments of the present application can perform sequencing operation on the current sources in the two current output circuits, and first determine the switching sequence of the current sources in one of the current output circuits according to the result of the sequencing operation, and then set the switching sequence of the current sources in the other current output circuit according to the switching sequence of the current sources in the one of the current output circuits, so that the integral nonlinear curves of the two current output circuits can have similar variation trends, thereby improving the matching degree of the two current output circuits.

[0070] BRIEF DESCRIPTION OF DRAWINGS

[0071] 100: current control system

[0072] 110: first current output circuit

[0073] 120: second current output circuit

[0074] 130: control circuit

[0075] 200: method

[0076] 300: current control system

[0077] 310: first current output circuit

[0078] 320: second current output circuit

[0079] 330: control circuit

[0080] 400: voltage control system

[0081] 410: first voltage output circuit

[0082] 420: second voltage output circuit

[0083] 430: control circuit

[0084] ACSA1: first current source

[0085] ACSA1: first current source

[0086] ACSB1: second current source

[0087] ACSB1: second current source

[0088] CSA1: first current source

[0089] CSA2: first current source

[0090] CSAN: first current source

[0091] CSB1: second current source

[0092] CSB2: second current source

[0093] CSBN: second current source

[0094] INL1: integral non-linear curve

[0095] INL2: integral non-linear curve

[0096] RA1: voltage dividing resistor

[0097] RA2: voltage dividing resistor

[0098] RAN: voltage dividing resistor

[0099] RB1: voltage dividing resistor

[0100] RB2: voltage dividing resistor

[0101] RBN: voltage dividing resistor

[0102] S1: switching circuit

[0103] S2: switching circuit

[0104] S210: step

[0105] S220: step

[0106] S230: step

[0107] S240: step

[0108] UCSA1: first unit current source

[0109] UCSB1: first unit current source

[0110] VDD: operating voltage

[0111] VSA1: first voltage dividing unit

[0112] VSA2: first voltage dividing unit

[0113] VSAN: first voltage dividing unit

[0114] VSB1: second voltage dividing unit

[0115] VSB2: second voltage dividing unit

[0116] VSBN: second voltage dividing unit

[0117] VSS: reference voltage

Claims

1. A method for calibrating output current, comprising: performing a first sorting operation on a plurality of first current sources according to current intensity outputted by the first current sources; performing a second sorting operation on a plurality of second current sources according to current intensity outputted by the second current sources; establishing a first switching sequence of the first current sources according to a result of the first sorting operation; and establishing a second switching sequence of the second current sources according to a result of the second sorting operation and the first switching sequence; wherein: each of the first current sources has a same first target current intensity; and each of the second current sources has a same second target current intensity; establishing the first switching sequence of the first current sources according to the result of the first sorting operation comprises: causing a first current source having a current intensity ranked as a median or closest to a reference current among the first current sources to have a first switching order, and then causing other first current sources among the first current sources to have switching orders symmetrically arranged on two sides of the first current source having the first switching order according to the current intensity; the second switching sequence is established according to the same rule as the first switching sequence. further comprising:

2. The method of calibrating an output current of claim 1, wherein, causing a first reference current to be generated by a first unit current source and a plurality of first current sources; and causing a second reference current to be generated by a second unit current source and a plurality of second current sources; wherein: a target current intensity of the first reference current is equal to the first target current intensity; a target current intensity of the second reference current is equal to the second target current intensity; the first unit current source and the first current sources have a same first secondary target current intensity; the second unit current source and the second current sources have a same second secondary target current intensity; performing the first sorting operation on the first current sources according to current intensity outputted by the first current sources comprises performing the first sorting operation on the first current sources according to current intensity outputted by the first current sources and the first reference current; and performing the second sorting operation on the second current sources according to current intensity outputted by the second current sources comprises performing the second sorting operation on the second current sources according to current intensity outputted by the second current sources and the second reference current.

3. The method for calibrating output current according to claim 2, wherein: establishing the first switching sequence of the first current sources according to the result of the first sorting operation comprises: causing a first current source having an output current closest to and greater than the first reference current to have a first switching order, and causing a first current source having an output current closest to and less than the first reference current to have a second switching order; or causing the first current source having an output current closest to and less than the first reference current to have the first switching order, and causing the first current source having an output current closest to and greater than the first reference current to have the second switching order. ​ ​ The second switch sequence of the second current source is determined according to the result of the second sorting operation and the first switch sequence, and includes: when the first current source whose output current is closest to and greater than the first reference current has the first switch sequence, a second current source whose output current is closest to and greater than the second reference current has the first switch sequence, and a second current source whose output current is closest to and less than the second reference current has the second switch sequence; or when the first current source whose output current is closest to and less than the first reference current has the first switch sequence, the second current source whose output current is closest to and less than the second reference current has the first switch sequence, and the second current source whose output current is closest to and greater than the second reference current has the second switch sequence.

4. The method of claim 1, wherein: The first switch sequence of the first current source is determined according to the result of the first sorting operation, and includes: a first median current source whose current intensity is sorted as a median value in the first current source has a first switch sequence; and The second switch sequence of the second current source is determined according to the result of the second sorting operation and the first switch sequence, and includes: a second median current source whose current intensity is sorted as a median value in the second current source has a first switch sequence.

5. The method of claim 4, wherein: The first switch sequence of the first current source is determined according to the result of the first sorting operation, and further includes: a first current source whose output current intensity is closest to and greater than a first median current output by the first median current source has a second switch sequence, and a first current source whose output current intensity is closest to and less than the first median current has a third switch sequence; or the first current source whose output current intensity is closest to and less than the first median current has the second switch sequence, and the first current source whose output current intensity is closest to and greater than the first median current has the third switch sequence; and The second switch sequence of the second current source is determined according to the result of the second sorting operation and the first switch sequence, and further includes: when the first current source whose output current intensity is closest to and greater than the first median current has the second switch sequence, a second current source whose output current intensity is closest to and greater than a second median current output by the second median current source has a second switch sequence, and a second current source whose output current intensity is closest to and less than the second median current has a third switch sequence; or the first current source whose output current intensity is closest to and less than the first median current has the second switch sequence, and the first current source whose output current intensity is closest to and greater than the first median current has the third switch sequence; and When the first current source whose output current intensity is closest to and less than the first median current has the second switch order, the second current source whose output current intensity is closest to and less than the second median current has the second switch order, and the second current source whose output current intensity is closest to and greater than the second median current has the third switch order.

6. A current control system, comprising: a first current output circuit comprising a plurality of first current sources, the first current sources having a same first target current intensity; a second current output circuit comprising a plurality of second current sources, the second current sources having a same second target current intensity; and a control circuit coupled to the first current output circuit and the second current output circuit, to: perform a first sorting operation on the first current sources according to the current intensities output by the first current sources perform a second sorting operation on the second current sources according to the current intensities output by the second current sources; determine a first switch order of the first current sources according to a result of the first sorting operation; and determine a second switch order of the second current sources according to a result of the second sorting operation and the first switch order; wherein determining the first switch order of the first current sources according to the result of the first sorting operation comprises: arranging a first current source whose current intensity is closest to a median number or a reference current in the first current sources to have a first switch order, and then arranging other first current sources in the first current sources to have switch orders symmetrically arranged on both sides of the first current source having the first switch order according to the current intensities of the first current sources; the second switch order is determined according to the same rule as the first switch order. the control circuit is:

7. The current control system of claim 6, wherein, when determining the first switch order of the first current sources: arranging a first median current source whose current intensity is closest to a median number in the first current sources to have a first switch order; for at least one first current source in the first current sources whose output current is less than the output current of the first median current source, sequentially arranging at least one switch order of the at least one first current source according to the current intensities of the at least one first current source from large to small; and for at least one remaining first current source in the first current sources other than the at least one first current source, sequentially arranging at least one switch order of the at least one remaining first current source according to the current intensities of the at least one remaining first current source from large to small; and when determining the second switch order of the second current sources: arranging a second median current source whose current intensity is closest to a median number in the second current sources to have a first switch order; for at least one second current source in the second current sources whose output current is less than the output current of the second median current source, sequentially arranging at least one switch order of the at least one second current source according to the current intensities of the at least one second current source from large to small; and for at least one remaining second current source in the second current sources other than the at least one second current source, sequentially arranging at least one switch order of the at least one remaining second current source according to the current intensities of the at least one remaining second current source from large to small. ​ ​ For the second current source, at least one remaining second current source other than the at least one second current source, a first serial order of the at least one remaining second current source is sequentially set according to a descending order of a current of the at least one remaining second current source.

8. A voltage control system, comprising: a first voltage output circuit including a plurality of first voltage dividing units having a same first target voltage dividing value; a second voltage output circuit including a plurality of second voltage dividing units having a same second target voltage dividing value; and a control circuit coupled to the first voltage output circuit and the second voltage output circuit, configured to: perform a first sorting operation on the first voltage dividing units according to voltage dividing values output by the first voltage dividing units; perform a second sorting operation on the second voltage dividing units according to voltage dividing values output by the second voltage dividing units; determine a first serial order of the first voltage dividing units according to a result of the first sorting operation; and determine a second serial order of the second voltage dividing units according to a result of the second sorting operation and the first serial order; wherein determining the first serial order of the first voltage dividing units according to the result of the first sorting operation comprises: when determining the first serial order of the first voltage dividing units, a first median voltage dividing unit having a median voltage dividing value in the first voltage dividing units has a first serial order; for at least one first voltage dividing unit of the first voltage dividing units, having a voltage dividing value less than a voltage dividing value output by the first median voltage dividing unit, at least one serial order of the at least one first voltage dividing unit is sequentially set according to a descending order of the voltage dividing value of the at least one first voltage dividing unit; and for at least one remaining first voltage dividing unit of the first voltage dividing units other than the at least one first voltage dividing unit, at least one serial order of the at least one remaining first voltage dividing unit is sequentially set according to a descending order of the voltage dividing value of the at least one remaining first voltage dividing unit. The determining rule of the second serial order is the same as the determining rule of the first serial order.

9. The voltage control system of claim 8, wherein, The control circuit is configured to: when determining the second serial order of the second voltage dividing units, a second median voltage dividing unit having a median voltage dividing value in the second voltage dividing units has a first serial order.

10. The voltage control system of claim 9, wherein, The control circuit is configured to: when determining the second serial order of the second voltage dividing units: for at least one second voltage dividing unit of the second voltage dividing units, having a voltage dividing value less than a voltage dividing value output by the second median voltage dividing unit, at least one serial order of the at least one second voltage dividing unit is sequentially set according to a descending order of the voltage dividing value of the at least one second voltage dividing unit; and for at least one remaining second voltage dividing unit of the second voltage dividing units other than the at least one second voltage dividing unit, at least one serial order of the at least one remaining second voltage dividing unit is sequentially set according to a descending order of the voltage dividing value of the at least one remaining second voltage dividing unit.

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