An R-2R type digital-to-analog converter

Abstract

The present invention discloses an R-2R type digital-to-analog converter, comprising a level conversion module, an enabling module, a first enabled module, a second enabled module, a thermometer decoding module, a delay circuit module, an inverter chain, a resistor combination circuit, a digital signal input terminal, a first power interface, a second power interface, a third power interface, a ground terminal, and an analog signal output terminal, wherein the high four-bit output terminal of the level conversion module is sequentially connected to the high four-bit input terminal of the inverter chain through the first enabled module and the thermometer decoding module, and the low eight-bit output terminal of the level conversion module is sequentially connected to the low eight-bit input terminal of the inverter chain through the delay circuit module and the second enabled module. While ensuring the characteristics of low power consumption and small area, the present invention further reduces power consumption, and improves conversion speed and conversion accuracy, and can be widely used in the technical field of digital-to-analog converters.

Description

Technical Field

[0001] The invention relates to the technical field of digital-to-analog converters, in particular to an R-2R type digital-to-analog converter. Background Art

[0002] With the advent of the 5G era, the communication system has developed rapidly, making the communication and interaction between people and electronic devices more and more frequent. The signals in nature need to be converted from analog signals to digital signals when processed by computers, and the digital signals transmitted in binary form need to be converted into analog signals when received by the next level. Therefore, the digital-to-analog converter is particularly important in the process of processing signals, and its performance directly affects the quality of the entire information transmission.

[0003] There are many structures of digital-to-analog converters (DACs), the common structures are series resistor type, R-2R inverted T type, current steering type and capacitor type. The series resistor type DAC has high precision and good output linearity, but it is not suitable for DACs with higher resolution, and its circuit area will double with the increase of resolution. The current steering type DAC has a fast conversion rate, but has problems such as high power consumption and low precision. The capacitor type DAC has a higher resolution, but the requirements for capacitor matching in the layout are high and the area is larger.

[0004] In the prior art, although the R-2R inverted-T type digital-to-analog converter has the advantages of low power consumption and small area, its conversion speed and conversion accuracy still need to be improved. Summary of the invention

[0005] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0006] To this end, an object of an embodiment of the present invention is to provide an R-2R type digital-to-analog converter, which further reduces power consumption and improves conversion speed and conversion accuracy while ensuring the characteristics of low power consumption and small area.

[0007] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0008] An embodiment of the present invention provides an R-2R type digital-to-analog converter, comprising a level conversion module, an enabling module, a first enabled module, a second enabled module, a thermometer decoding module, a delay circuit module, an inverter chain, a resistor combination circuit, a digital signal input terminal, a first power supply interface, a second power supply interface, a third power supply interface, a ground terminal, and an analog signal output terminal, wherein the first input terminal of the level conversion module is used to input a digital signal through the digital signal input terminal, the second input terminal of the level conversion module is connected to the first output terminal of the enabling module, and the high four-bit output terminal of the level conversion module is connected to the first enabled module, the thermometer decoding module, and the ground terminal through the first enabled module and the thermometer decoding module. The high four-bit input end of the inverter chain, the low eight-bit output end of the level conversion module is connected to the low eight-bit input end of the inverter chain through the delay circuit module and the second enabled module in sequence, the input end of the first enabled module and the input end of the second enabled module are both connected to the second output end of the enabling module, the output end of the inverter chain is connected to the analog signal output end through the resistor combination circuit, the analog signal output end is used to output an analog signal, the first power supply interface is used to access a reference voltage, the second power supply interface is used to access an analog power supply, the third power supply interface is used to access a converted level, and the grounding end is used to access a ground level.

[0009] Furthermore, in one embodiment of the present invention, the R-2R type digital-to-analog converter also includes a plurality of enable control ports, each of which is used to input a different external control signal to the enable module, so that the enable module is in a different control state, and outputs a corresponding first control signal to the level conversion module, and outputs a corresponding second control signal to the first enabled module and the second enabled module.

[0010] Furthermore, in one embodiment of the present invention, the second input end of the level conversion module is used to receive the first control signal, the first control signal is used to control the working state of the level conversion module, and output the corresponding level conversion result to the first enabled module through the high four-bit output end of the level conversion module, and output the corresponding level conversion result to the delay circuit module through the low eight-bit output end of the level conversion module.

[0011] Further, in one embodiment of the present invention, the second control signal is used to control the working status of the first enabled module and the second enabled module. When the second control signal is at a high level, the first enabled module and the second enabled module work normally. When the second control signal is at a low level, the first enabled module and the second enabled module are in sleep mode.

[0012] Furthermore, in one embodiment of the present invention, the thermometer decoding module is used to convert the 4-bit binary code outputted from the upper four-bit output terminal of the level conversion module into a 15-bit thermometer code.

[0013] Furthermore, in one embodiment of the present invention, the inverter chain is used to adjust the phases of output signals of the thermometer decoding module and the second enabled module.

[0014] Furthermore, in one embodiment of the present invention, the resistor combination circuit includes four first resistors, eight second resistors, one third resistor and seven fourth resistors, the high four-bit output ends of the inverter chain are respectively connected to the first end of each of the first resistors, the low eight-bit output ends of the inverter chain are respectively connected to the first end of each of the second resistors, the ground end is connected to the first end of the third resistor, the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are all connected to the analog signal output end, and the fourth resistor is connected in series between the second ends of two adjacent second resistors.

[0015] Further, in one embodiment of the present invention, the resistance value of the first resistor is equal to the resistance value of the fourth resistor, the resistance value of the second resistor is equal to the resistance value of the third resistor, and the resistance value of the second resistor is twice the resistance value of the first resistor.

[0016] The advantages and beneficial effects of the present invention will be partly given in the following description, partly become apparent from the following description, or be understood through the practice of the present invention:

[0017] The R-2R digital-to-analog converter of the embodiment of the present invention introduces thermometer decoding and segmented design on the basis of the traditional digital-to-analog converter. The lower eight bits use binary code and the upper four bits use thermometer decoding, which improves the conversion speed and conversion accuracy of the digital-to-analog converter. The enabling module controls the working states of the level conversion module, the first enabled module and the second enabled module, so as to realize the switching between sleep and work, and further reduce the power consumption of the digital-to-analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution in the embodiments of the present invention, the following introduction is made to the drawings required for use in the embodiments of the present invention. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solution of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of the structure of an R-2R type digital-to-analog converter provided in an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of the structure of an enabling module provided in an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the structure of a level conversion module provided by an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of the structure of a first enabled module and a second enabled module provided in an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the structure of a thermometer decoding module provided by an embodiment of the present invention;

[0024] Figure 6 A resistor combination circuit and its equivalent schematic diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0026] In the description of the present invention, the meaning of "a plurality" is two or more than two. If there is a description of "a first" or "a second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. In addition, unless otherwise defined, all technical and scientific terms used in this document have the same meaning as those commonly understood by those skilled in the art.

[0027] Reference Figure 1The embodiment of the present invention provides an R-2R type digital-to-analog converter, including a level conversion module, an enabling module, a first enabled module, a second enabled module, a thermometer decoding module, a delay circuit module, an inverter chain, a resistor combination circuit, a digital signal input terminal, a first power supply interface, a second power supply interface, a third power supply interface, a ground terminal and an analog signal output terminal. The first input terminal of the level conversion module is used to input a digital signal through the digital signal input terminal, the second input terminal of the level conversion module is connected to the first output terminal of the enabling module, and the high four-bit output terminal of the level conversion module is sequentially connected through the first enabled module, the thermometer decoding module, the delay circuit module, the inverter chain, the resistor combination circuit, the digital signal input terminal, the first power supply interface, the second power supply interface, the third power supply interface, the ground terminal and the analog signal output terminal. The meter decoding module is connected to the high four-bit input end of the inverter chain, the low eight-bit output end of the level conversion module is connected to the low eight-bit input end of the inverter chain through the delay circuit module and the second enabled module in sequence, the input end of the first enabled module and the input end of the second enabled module are both connected to the second output end of the enabling module, the output end of the inverter chain is connected to the analog signal output end through a resistor combination circuit, the analog signal output end is used to output an analog signal, the first power supply interface is used to access a reference voltage, the second power supply interface is used to access an analog power supply, the third power supply interface is used to access a converted level, and the grounding end is used to access a ground level.

[0028] Specifically, Figure 1 As shown, the R-2R type digital-to-analog converter of the embodiment of the present invention includes a level conversion module, an enabling module, a first enabled module, a second enabled module, a thermometer decoding module, a delay circuit module, an inverter chain, a resistor combination circuit, and a digital signal input terminal D <0> To D <11> , a first power supply interface VREF, a second power supply interface VDDA, a third power supply interface VP_1P5V, a ground terminal GNDA and an analog signal output terminal VOUT. Digital signal input terminal D <0> To D <11> Used to receive binary digital signals from external devices, the first power supply interface VREF is used to access the reference voltage 3.3V, the second power supply interface VDDA is used to access the analog power supply 3.3V, the third power supply interface VP_1P5V is used to access the converted level 1.5V, the ground terminal GNDA is used to access the ground level 0V, and the analog signal output terminal VOUT is used to output the analog signal after digital-to-analog conversion. It can be connected to an external device for testing or to the next-stage operational amplifier circuit to realize different functions.

[0029] Reference Figure 1 As an optional implementation, the R-2R type digital-to-analog converter also includes a plurality of enable control ports, each of which is used to input a different external control signal to the enable module, so that the enable module is in a different control state, and outputs a corresponding first control signal to the level conversion module, and outputs a corresponding second control signal to the first enabled module and the second enabled module.

[0030] Specifically, the R-2R type digital-to-analog converter of the embodiment of the present invention is provided with three enable control ports G, G1 and G2, and through different external inputs, the enable module is in different control states, thereby controlling the entire digital-to-analog converter to be in different working modes. The first output end of the enable module is used to output the first control signal G_en to the level conversion module, and the second output end is used to output the second control signal EN to the first enabled module and the second enabled module.

[0031] like Figure 2 The schematic diagram of the structure of the enabling module provided by the embodiment of the present invention is shown. The enabling module includes a first enabling unit and a second enabling unit, the second control signal EN is composed of the output signal OUT1 of the first enabling unit and the output signal OUT2 of the second enabling unit, M1, M2, M6, M7, M8, M9 and M12 represent NMOS tubes, M3, M4, M5, M9, M10 and M11 represent PMOS tubes, when the G port is connected to a low level, the first enabling unit does not work, the pull-up PMOS tube M5 and the pull-down NMOS tube M6 are turned on, a high level is provided for the gate voltage of the NMOS tube M1, and a low level is provided for the gate voltage of the NMOS tube M2, so that M1 is turned on, M2 is turned off, the OUT1 voltage value is pulled down to 0, the PMOS tube M4 is turned on, and the G_en voltage value is pulled up to start the second enabling unit to work. At this time, the second control signal EN=OUT2 output by the enable module is determined by the high and low levels of the G2 port input. If the G2 input is high level 1.5V, the OUT2 output is 3.3V, and EN is high level 3.3V. At this time, the DAC is in working state; if the G2 input is low level 0V, the OUT2 output is 0V, and EN is low level 0V. At this time, the DAC is in the state where the input signal is latched to the first enabled module and the second enabled module but not output to the resistor combination circuit.

[0032] When the G port is connected to a high level, the first enabling unit works, and the output of OUT1 is determined by the high and low levels of the G2 port input, and the state of G_en is opposite to that of OUT1. If the G1 input is a low level of 0V, the OUT1 output is 0V, G_en is 3.3V, and the second enabling unit works; if the G2 input is a high level of 1.5V, the OUT2 output is 3.3V, and EN is a high level of 3.3V. At this time, the DAC is in a working state; if the G2 input is a low level of 0V, the OUT2 output is 0V, and EN is a low level of 0V. At this time, the DAC is in a state where the input signal is latched to the first enabled module and the second enabled module but not output to the resistor combination circuit; if the G1 input is a high level of 1.5V, the OUT1 output is 3.3V, G_en is 0V, and the second enabling unit does not work. The pull-up PMOS tube M11 and the pull-down NMOS tube M12 are turned on to provide a high level for the gate voltage of the NMOS tube M7. After M7 is turned on, OUT2 is pulled to a low level of 0V. At this time, EN=OUT1 is 3.3V, and the first enabled module and the second enabled module transmit their latched data backward to the resistor, but do not receive the input signal.

[0033] Reference Figure 1 , further as an optional implementation, the second input end of the level conversion module is used to receive a first control signal, the first control signal is used to control the working state of the level conversion module, and output the corresponding level conversion result to the first enabled module through the high four-bit output end of the level conversion module, and output the corresponding level conversion result to the delay circuit module through the low eight-bit output end of the level conversion module.

[0034] Specifically, Figure 3 The figure shows a schematic diagram of the structure of the level conversion module provided in an embodiment of the present invention, M21, M22 and M26 represent NMOS tubes, M23, M24 and M25 represent PMOS tubes, the first input end of the level conversion module is used to receive a binary digital signal D input by an external device, the second input end is used to receive a first control signal G_en output by an enabling module to control the working state of the level conversion circuit, and the output interface DO outputs the result of the level conversion to the lower eight-bit delay circuit module and the upper four-bit first enabled unit.

[0035] When the first control signal G_en is at a low level, the level conversion module does not work, the pull-up PMOS tube M25 and the pull-down NMOS tube M26 are turned on, providing bias voltage for the gates of the NMOS tubes M21 and M22, and M21 is turned on to pull DO to a low level; when the first control signal G_en is at a high level, the level conversion module works, and when the input D is at a low level of 0V, M21 is turned on through the left transmission gate input, and DO is pulled to a low level; when the input D is at a high level, M22 is turned on through the right transmission gate input, and the gate voltage of the PMOS tube M23 is pulled down. After M23 is turned on, the analog power connected to VDDA will be transmitted to the DO port for output. At this time, the level conversion module completes the level conversion work.

[0036] Further as an optional implementation, the second control signal is used to control the working status of the first enabled module and the second enabled module. When the second control signal is at a high level, the first enabled module and the second enabled module work normally. When the second control signal is at a low level, the first enabled module and the second enabled module are in sleep mode.

[0037] Specifically, Figure 4 The figure shows a schematic diagram of the structure of the first enabled module and the second enabled module provided by an embodiment of the present invention. It can be understood that the first enabled module and the second enabled module adopt the same structure. The module is constructed by a simple XNOR gate. Port A is used to receive the second control signal EN, and port B is used to receive the output of the previous stage (the output of the high four bits of the level conversion module or the output of the delay circuit module). Only when the second control signal is at a high level, the module will work normally, otherwise it will be in sleep mode. The calculation formula is:

[0038]

[0039] Wherein, ZN represents the output signal of the enabled module.

[0040] As a further optional implementation, the thermometer decoding module is used to convert the 4-bit binary code output by the upper four-bit output terminal of the level conversion module into a 15-bit thermometer code.

[0041] Specifically, in the digital-to-analog conversion structure of the embodiment of the present invention, a thermometer decoding module is added, and the circuit is designed in segments, wherein the upper four bits are decoded by thermometers to ensure that when two adjacent binary codes change, multiple branches will not change at the same time, so that the output branch only changes by one bit, thereby well ensuring the output accuracy.

[0042] like Figure 5The structure diagram of the thermometer decoding module provided by the embodiment of the present invention is shown, wherein abcd represents a 4-bit binary code, and T1 to T15 represent a 15-bit thermometer code. The comparison table of converting a 4-bit binary code to a 15-bit thermometer code is shown in Table 1 below.

[0043] Binary Code Thermometer code abcd T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 0000 000000000000000 0001 000000000000001 0010 000000000000011 0011 000000000000111 0100 000000000001111 0101 000000000011111 0110 000000000111111 0111 000000001111111 1000 000000011111111 1001 000000111111111 1010 000001111111111 1011 000011111111111 1100 000111111111111 1101 001111111111111 1110 011111111111111 1111 111111111111111

[0044] Table 1

[0045] According to Table 1, the corresponding relationship between the 4-bit binary code and the 15-bit thermometer code is:

[0046] T15=abcd

[0047] T14=bcd

[0048] T13=(c+d)ab

[0049] T12=ab

[0050] T11=(cd+b)a

[0051] T10=(b+c)a

[0052] T9=(b+c+d)a

[0053] T8=(a+b)a

[0054] T7=(cd+a)(a+b)

[0055] T6=(a+c)(a+b)

[0056] T5=(a+b)(a+c+d)

[0057] T4=a+b

[0058] T3=a+b+cd

[0059] T2=a+b+c

[0060] T1=a+b+c+d

[0061] As a further optional implementation, the inverter chain is used to adjust the phase of the output signal of the thermometer decoding module and the second enabled module.

[0062] Specifically, since the traditional thermometer decoding structure only considers the logical relationship between input and output and ignores the characteristics of PMOS tubes and NMOS tubes, in actual applications, the AND gate and the OR gate will have different delays in transmitting the same data. To prevent this phenomenon from occurring, an inverter chain is added in the embodiment of the present invention for improvement.

[0063] Reference Figure 1, further as an optional implementation, the resistor combination circuit includes four first resistors R1, eight second resistors R2, one third resistor R3 and seven fourth resistors R4, the high four-bit output ends of the inverter chain are respectively connected to the first end of each first resistor, the low eight-bit output ends of the inverter chain are respectively connected to the first end of each second resistor, the ground end is connected to the first end of the third resistor, the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are all connected to the analog signal output terminal VOUT, and the fourth resistor is connected in series between the second ends of two adjacent second resistors.

[0064] As a further optional implementation, the resistance value of the first resistor is equal to the resistance value of the fourth resistor, the resistance value of the second resistor is equal to the resistance value of the third resistor, and the resistance value of the second resistor is twice the resistance value of the first resistor.

[0065] Specifically, Figure 6 The figure shows a resistor combination circuit and an equivalent schematic diagram thereof provided by an embodiment of the present invention, wherein the resistance values ​​of the first resistor and the fourth resistor are both R, and the resistance values ​​of the second resistor and the third resistor are both 2R. According to the Thevenin equivalent theorem, it can be concluded that the digital-to-analog conversion output is:

[0066]

[0067] Wherein, k represents the number of 1s in the 15-bit thermometer code T15~T1, VREF represents the reference voltage, Di (i=0,1,2,…,7) represents the binary code output by the lower eight-bit output terminal of the inverter chain, Figure 6 R5 is equivalent to k resistors with a resistance value of R connected to the reference level VREF, R6 is equivalent to 15-k resistors with a resistance value of R connected to the ground, and D8 to D11 represent the thermometer code output by the high four-bit output end of the inverter chain. In the above formula, each binary bit has its corresponding weight, so the resistor combination circuit can realize the conversion from digital level to analog voltage.

[0068] The structure of the embodiment of the present invention is described above. It can be recognized that the R-2R type digital-to-analog converter of the embodiment of the present invention introduces thermometer decoding and segmented design on the basis of the traditional digital-to-analog converter. The lower eight bits use binary code and the upper four bits use thermometer decoding, which improves the conversion speed and conversion accuracy of the digital-to-analog converter. By controlling the working states of the level conversion module, the first enabled module and the second enabled module through the enabling module, the switching between sleep and work can be realized, which further reduces the power consumption of the digital-to-analog converter.

[0069] In addition, the structure of the embodiment of the present invention can not only realize the basic functions of the digital-to-analog converter, but also has good linearity. Through temperature and process angle simulation, it can be known that the embodiment of the present invention can be compatible with the changes of temperature from -40°C to 120°C and process angles ff, tt, and ss. Its DNL and INL have good characteristics, DNL<0.5LSB, INL<0.5LSB, and the occupied area is only 0.091mm 2 .

[0070] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0071] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0072] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. An R-2R type digital-to-analog converter, characterized in that: The invention comprises a level conversion module, an enabling module, a first enabled module, a second enabled module, a thermometer decoding module, a delay circuit module, an inverter chain, a resistor combination circuit, a digital signal input terminal, a first power interface, a second power interface, a third power interface, a ground terminal and an analog signal output terminal, wherein the first input terminal of the level conversion module is used to input a digital signal through the digital signal input terminal, the second input terminal of the level conversion module is connected to the first output terminal of the enabling module, and the high four-bit output terminal of the level conversion module is connected to the high four-bit input terminal of the inverter chain through the first enabled module and the thermometer decoding module in sequence. The lower eight-bit output end of the level conversion module is connected to the lower eight-bit input end of the inverter chain through the delay circuit module and the second enabled module in sequence, the input end of the first enabled module and the input end of the second enabled module are both connected to the second output end of the enabling module, the output end of the inverter chain is connected to the analog signal output end through the resistor combination circuit, the analog signal output end is used to output an analog signal, the first power supply interface is used to access a reference voltage, the second power supply interface is used to access an analog power supply, the third power supply interface is used to access a converted level, and the grounding end is used to access a ground level.

2. The R-2R type digital-to-analog converter according to claim 1, characterized in that: The R-2R type digital-to-analog converter also includes a plurality of enable control ports, each of which is used to input different external control signals to the enable module, so that the enable module is in different control states, and outputs a corresponding first control signal to the level conversion module, and outputs a corresponding second control signal to the first enabled module and the second enabled module.

3. The R-2R type digital-to-analog converter according to claim 2, characterized in that: The second input end of the level conversion module is used to receive the first control signal, and the first control signal is used to control the working state of the level conversion module, and output the corresponding level conversion result to the first enabled module through the high four-bit output end of the level conversion module, and output the corresponding level conversion result to the delay circuit module through the low eight-bit output end of the level conversion module.

4. The R-2R type digital-to-analog converter according to claim 2, characterized in that: The second control signal is used to control the working status of the first enabled module and the second enabled module. When the second control signal is at a high level, the first enabled module and the second enabled module work normally. When the second control signal is at a low level, the first enabled module and the second enabled module are in sleep mode.

5. The R-2R type digital-to-analog converter according to claim 1, characterized in that: The thermometer decoding module is used to convert the 4-bit binary code output by the upper four-bit output terminal of the level conversion module into a 15-bit thermometer code.

6. The R-2R digital-to-analog converter according to claim 1, characterized in that: The inverter chain is used to adjust the phases of the output signals of the thermometer decoding module and the second enabled module.

7. An R-2R type digital-to-analog converter according to any one of claims 1 to 6, characterized in that: The resistor combination circuit includes four first resistors, eight second resistors, one third resistor and seven fourth resistors. The four high-bit output ends of the inverter chain are respectively connected to the first end of each of the first resistors, the eight low-bit output ends of the inverter chain are respectively connected to the first end of each of the second resistors, the ground end is connected to the first end of the third resistor, the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are all connected to the analog signal output end, and the fourth resistor is connected in series between the second ends of two adjacent second resistors.

8. The R-2R type digital-to-analog converter according to claim 7, characterized in that: The resistance value of the first resistor is equal to the resistance value of the fourth resistor, the resistance value of the second resistor is equal to the resistance value of the third resistor, and the resistance value of the second resistor is twice the resistance value of the first resistor.

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