Methods, systems, and computer-readable media for displaying pwm duty cycle compensation

Abstract

The frame generation subsystem renders a sequence of frames, and the display control subsystem provides a brightness control signal configured to control brightness of frames displayed at the display panel via pulse width modulation (PWM) of the brightness control signal, and the display control subsystem determines a deviation of a duty cycle of a first PWM cycle of the brightness control signal from a default duty cycle resulting from the delayed rendering of the frames. The display control subsystem adjusts the duty cycle of at least a second PWM cycle to compensate for the deviation in the duty cycle of the first PWM cycle. The average duty cycle of the brightness control signal over the two frame cycles is approximately equal to the default duty cycle, and thus mitigates visible flicker resulting from the variation in the duty cycle caused by the delayed rendering.

Description

BACKGROUND

[0001] Some video display systems utilize a pulse width modulation (PWM) scheme to control the luminance of a display panel displaying corresponding video frames. A digital control signal that controls a backlight in a transmissive display panel or directly controls pixel intensity in an emissive display panel is pulse width modulated such that the resulting luminance of the display panel is proportional to the duty cycle of the resulting PWM signal. Thus, any change in the effective duty cycle of the control signal between two consecutive frame periods will introduce a corresponding change in luminance at the display panel between the two consecutive frame periods. In display systems that employ variable refresh rates, delays in the rendering or other generation of video frames can cause misalignment of the display of a delayed frame or subsequent frames relative to the PWM control signal. As a result, the effective duty cycle of the PWM control signal can change between consecutive frames. Thus, this change in the effective duty cycle of the PWM control signal can cause one frame to have a lower or greater luminance than the next frame (depending on whether the effective duty cycle increases or decreases between the two frames). This change in luminance between consecutive frames is often perceptible to a viewer as flicker, which detracts from the viewing experience. BRIEF DESCRIPTION OF DRAWINGS

[0002] The present disclosure will be better understood by reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure and which are made a part of this disclosure. Like reference numbers used in different drawings indicate similar or identical items.

[0003] Figure 1 is a block diagram illustrating a display system employing a PWM duty cycle compensation technique in accordance with at least one embodiment.

[0004] Figure 2 is a timing diagram illustrating an example comparison of a conventional approach to PWM-based display luminance control in the presence of a rendered delayed frame versus an example implementation of a PWM duty cycle compensation technique in the same situation.

[0005] Figure 3 is a flowchart illustrating a method for PWM duty cycle compensation for display luminance control in accordance with some embodiments.

[0006] Figure 4 is a timing diagram illustrating an example of the method of Figure 3 in accordance with some embodiments.

[0007] Figure 5 is a timing diagram illustrating an example technique for determining a compensating adjustment to the PWM duty cycle of a luminance control signal for one or more PWM periods of a frame period that follows a frame period affected by a rendered delayed frame in accordance with some embodiments. DETAILED DESCRIPTION

[0008] Figure 1 A display system 100 employing a PWM duty cycle compensation scheme to mitigate PWM duty cycle distortion in a brightness control signal due to frame latency presentation is illustrated. The display system 100 can comprise any of a variety of systems for presenting, decoding, or otherwise generating a sequence of video frames for display, such as a desktop computer, a notebook computer, a tablet computer, a computing-enabled cellular telephone, a server, a game console, a television, and a computing-enabled watch or other wearable device, etc. The display system 100 includes a frame generation subsystem 102, a display control subsystem 104, and a display panel 106. The frame generation subsystem 102 operates to generate a sequence of video frames (hereinafter simply “frames”) for display and includes a system memory 108 storing one or more software applications 110 and a set of one or more processors, such as one or more central processing units (CPUs) 112, one or more graphics processing units (GPUs) 114, and one or more display processing units (DPUs) 116.

[0009] In one embodiment, the display control subsystem 104 includes a graphics random access memory (GRAM) 118 or other memory operating as a frame buffer, pixel drivers 120, a timing controller 122, one or more clock sources 124, and one or more counters 126. The pixel drivers 120 and the timing controller 122 are implemented via hardwired logic (e.g., integrated circuits), programmable logic (e.g., programmable logic devices), one or more processors executing software instructions, or a combination thereof. In the illustrated embodiment, the components of the frame generation subsystem 102 are implemented together in a host system on a chip (SoC) 128, while the components of the display control subsystem 104 are implemented on a separate display driver integrated circuit (DDIC) 130. However, in other embodiments, the components of the two subsystems 102, 104 are implemented on the same IC or the same SoC, or different combinations of components are implemented on different ICs or SoCs. The display panel 106 can comprise any of a variety of display panels configurable to provide brightness control via PWM duty cycle control, such as a liquid crystal display (LCD) panel, a light emitting diode (LED) panel, an organic LED (OLED) panel, and an active matrix OLED (AMOLED) panel, etc.

[0010] As a general operational overview, CPU 112 executes software application 110, which may represent a video game, virtual reality (VR), or augmented reality (AR) application, or other software applications executed to generate a series of frames for display. As part of this execution process, CPU 112 instructs GPU 114 to render or otherwise generate each frame in the sequence, and DPU 116 performs one or more post-rendering processes on the frames, such as gamma correction or other filtering and color format conversion. Frame data 131 of the generated frames 132 is then transmitted to display control subsystem 104 for buffering in GRAM 118.

[0011] In the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, a brightness control signal 138, and a vertical blanking (VSYNC) signal and a scan start signal. Figure 1 (Not shown in the image). The TE signal 136 is used to synchronize the transmission of the next frame 132 from the frame generation subsystem 102 to the GRAM 118 to mitigate screen tearing artifacts caused by the last line of the current frame being overwritten before the display panel 106 is displayed. The brightness control signal 138 is a pulse-width modulated digital signal for controlling the brightness of the display panel 106. In embodiments where the display panel 106 is implemented as an LCD panel or other transmissive display panel, the brightness control signal 138 represents a PWM control signal for activating the backlight of the transmissive display panel. For emission display panels (such as OLED and AMOLED display panels), the emission control (EM) signal provided to each active pixel is pulse-width modulated with a certain duty cycle to control the brightness of the corresponding pixel, and in such cases, the brightness control signal 138 represents this EM signal. Since the following description primarily relates to OLED-based or AMOLED-based embodiments of the display panel 106, the brightness control signal 138 is also referred to herein as "EM signal 138," but the reference to EM signal also applies to other forms of PWM-based brightness control unless otherwise stated.

[0012] The timing controller 122 uses timing signaling and other control signaling 140 to control the pixel drivers 120 to drive the display panel 106 by scanning frame data 131 from the frames 132 of the GRAM 118 into the pixel array (not shown) of the display panel 106 having row line addressing to display the frames 132 from the GRAM 118, the transfer of pixel data from the pixel drivers 120 to the display panel 106 being represented by the SCAN signals 142. The pixels of each row are activated to emit display light according to the corresponding pixel values for that row, the luminance of the emitted display light being controlled at least in part by the PWM duty cycle of the EM signal 138 during the frame period for which the corresponding frame 132 is displayed. In some embodiments, the amplitude of the EM signal 138 can also be adjusted to further control the intensity of the emitted light.

[0013] In at least one embodiment, the display system 100 supports a variable refresh rate, such that the frame rate can be modified to accommodate frames that can take different amounts of time to render, rather than requiring a fixed frame rate for rendering and displaying a sequence of frames. To illustrate, the complexity of a frame to be rendered, or the current resources available to render a given frame, can cause the preparation of a rendered frame to take more time than is available at a nominal current frame rate, and so the system can instead dynamically utilize and temporarily adjust the frame period for which a rendered delayed frame is presented. However, because in a variable refresh rate configuration the frame period for a first frame can be different than the frame period for a second frame that is adjacent to the first frame, it is possible that the effective duty cycle of the EM signal 138 during the frame period for the first frame is different than the effective duty cycle of the EM signal 138 during the frame period for the second frame, which in turn causes a luminance change from the first frame to the second frame that can be detected by a viewer as a distracting flicker.

[0014] Accordingly, in at least one embodiment, the timing controller 122 employs a PWM duty cycle compensation scheme 144 in which a deviation of the PWM duty cycle of the EM signal 138 relative to a nominal PWM duty cycle is determined for a frame period affected by a rendered delayed frame (hereinafter, a “rendered delayed frame period”), and then the effective PWM duty cycle of the EM signal 138 is compensatorily adjusted in one or more PWM periods in a frame period that follows the rendered delayed frame period (this frame period is referred to herein as a “compensation frame period”) in an opposite manner. By adjusting the effective duty cycle of the EM signal 138 for the compensation frame period to compensate for the deviation in the effective PWM duty cycle introduced for the rendered delayed frame period, the timing controller 122 can provide an EM signal 138 that, over the two frame periods, has an average effective PWM duty cycle that is approximately equal to the default or nominal PWM duty cycle intended for the two frame periods. This results in an average effective luminance output at the display panel 106 that is relatively consistent with the nominal PWM duty cycle and corresponding nominal luminance level intended for the two frame periods in the absence of the rendered delayed frame.

[0015] Figure 2 A timing diagram 200 illustrating a general example operation of the PWM duty cycle compensation scheme 144 (represented by timing portion 202 of timing diagram 200) in accordance with some embodiments, and a comparison to a conventional approach lacking duty cycle bias compensation (represented by timing portion 204 of timing diagram 200). Timing diagram 200 illustrates two successive frame periods: a presentation delayed frame period 206 (for which the completion of presentation is delayed to the extent that the duration of frame period 206 has been extended) contemporaneous with a presented frame; and a subsequent frame period 208 (and for which a concurrent frame is presented in time) following the presentation delayed frame period 206. An EM signal 210 provided for controlling display luminance in the conventional approach, and the above-mentioned EM signal 138, both have the same nominal PWM duty cycle, for example represented by a PWM period 212 of EM signal 210.

[0016] In this example, the delayed presentation of the frame during the presentation delayed frame period 206 causes the conventional timing controller to extend the high voltage level portion 214 of the last PWM period 216 in frame period 206 for EM signal 210, resulting in a modified duty cycle for PWM period 216 that is higher than the nominal duty cycle for EM signal 210. Then, for the PWM periods of subsequent frame period 208, EM signal 210 maintains the nominal PWM duty cycle. As shown by line 218 of timing portion 204, which represents the luminance level of the corresponding display panel perceived by an observer over time and produced by EM signal 210, the increase in effective duty cycle in PWM period 216 results in a relatively significant increase in perceived luminance over a relatively short period of time. This is typically perceived by the viewer as a visible or otherwise noticeable flicker, and thus detracts from the viewer's experience.

[0017] Turning to the example operation of the PWM duty cycle compensation scheme 144 in the same scenario, the EM signal 138 again experiences an increase in its effective duty cycle for the last PWM period 226 of the presentation-delayed frame 206, as the delayed presentation of the frame causes the high voltage level portion 224 of this PWM period 226 to stretch. However, as described in greater detail below, in accordance with the PWM duty cycle compensation scheme 144, the timing controller 122 detects the change in effective duty cycle from the PWM period 226 caused by the delayed presentation and then adjusts the effective duty cycle in the first PWM period 228 of the subsequent frame period 208 in the opposite manner to compensate for the deviation of the duty cycle of the PWM period 226 from the nominal duty cycle. In this particular example, because the high voltage level portion 224 is increased by an amount AL (= L2- Li, where L2represents the duration of the high voltage level portion of the PWM period 226, and Li represents the duration of the high voltage level portion of a nominal or default PWM period), the high voltage level portion 230 of the PWM period 228 is decreased by the amount AL. That is, the + AL deviation in the duty cycle of the PWM period 226 results in a corresponding adjustment of + AL in the duty cycle of the subsequent PWM period 228. As a result, the effective PWM duty cycle averaged over the PWM period 226 and the PWM period 228 matches the nominal duty cycle. Thus, as shown by line 232 of the timing portion 202, which represents the brightness level of the display 106 perceived by the observer and produced by the EM signal 138, the instantaneous increase in brightness caused by the increase in effective PWM duty cycle in the PWM period 226 is offset by a corresponding compensatory instantaneous decrease in brightness caused by the decrease in effective PWM duty cycle in the PWM period 228, which in turn results in a negligible flicker being presented to the viewer.

[0018] Figure 3 FIG. 1 illustrates a display system 100 in accordance with some embodiments. Figure 1 The display system 100 of FIG. 1 operates in accordance with a method 300 of operation in presenting and displaying a stream or other sequence of frames using the PWM duty cycle compensation scheme 144. In the illustrated example, the method 300 consists of two concurrent processes: a presentation / display process 302 for generating and displaying the sequence of frames; and, a PWM duty cycle configuration process 304 (representative of the PWM duty cycle compensation scheme 144) for setting and dynamically changing the PWM duty cycles of the PWM periods of the EM signal 138, and, in the case of a presentation-delayed frame, compensating for any PWM duty cycle changes introduced in one or more PWM periods of the frame period by inversely adjusting the PWM duty cycles of one or more PWM periods in a subsequent frame period.

[0019] The iteration of the rendering / display process 302 begins at block 306, whereby the frame generation subsystem 102 renders the frame 132 and buffers the frame 132 in the GRAM 118. At block 308, the timing controller 122 and the pixel drivers 120 coordinate to transfer the pixel data of the frame 132 from the GRAM 118 to the display panel 106 via the SCAN signals 142, and at block 310, the display panel 106 displays the selected frame 132 with luminance at least partially controlled in the active PWM duty cycle of the EM signal 138 during the frame period. In some embodiments, the display panel 106 begins displaying the pixel rows of the selected frame 132 that have been received while subsequent rows are still being transferred. In other embodiments, the entire selected frame 132 is transferred to the display panel 106 before the display of the frame 132 begins.

[0020] Each iteration of the rendering / display process 302 includes a configuration of the PWM duty cycle implemented by each PWM period of the EM signal 138 based at least in part on detection of a prior deviation of the duty cycle from a specified nominal duty cycle. In one embodiment, this aspect is controlled by the timing controller 122 of the display control subsystem 104 in accordance with a PWM duty cycle compensation scheme 144 represented by the duty cycle configuration sub-process 304. As a general overview of the scheme 144, the PWM duty cycle periods are configured to default to a nominal duty cycle corresponding to an expected luminance during the display of the corresponding frame during the frame period. However, when a delayed rendering of a frame results in a deviation of the PWM duty cycle of one or more consecutive PWM periods from the nominal duty cycle, the timing controller 122 operates to compensate for this deviation by adjusting the duty cycle of one or more subsequent PWM periods in an opposite manner, resulting in an average PWM duty cycle of all of the affected PWM periods approximately equal to the nominal PWM duty cycle.

[0021] Thus, at block 308, the timing controller 122 monitors the frame rendering and transfer process of blocks 306 and 308 for an indication that the rendering of the current frame is being or will be “delayed”; that is, the rendering of the current frame is taking long enough that the current frame can or will not be ready for scanning to the display panel 106 by the time the frame period of the current frame (i.e., the frame that is currently being displayed) ends and the frame period of the next frame to be displayed begins (block 308). To illustrate, in some embodiments, a specified signal is provided by the frame generation subsystem 102 to signify completion of the rendering of a frame, such as by transfer of a 2C data packet. For a given frame rate, this specified signal is provided within a specified delay after assertion of the TE signal 136. Thus, failure to receive this specified signal within the corresponding delay after assertion of the TE signal 136 indicates that the rendering of the frame is delayed.

[0022] In the absence of any indication of delayed / delayed rendering of the current frame being rendered (e.g., in response to determining that the current frame has been rendered before a certain time or threshold associated with the target frame rate), in block 314, timing controller 122 sets the PWM duty cycle of one or more PWM cycles of the EM signal 138 for the next frame cycle (i.e., the frame cycle following the current frame cycle) to the default or nominal PWM duty cycle for the corresponding indicated brightness level used to display the frame. Returning to block 312, if timing controller 122 alternatively detects delayed rendering of the current frame, in block 316, timing controller 122 starts a counter (e.g., Figure 1 The timing controller 122 determines a measurement of the delay caused by the delayed presentation of the current frame, which reaches such a level that it causes the duty cycle of one or more PWM cycles in the current frame period to deviate from the default duty cycle set for the indicated brightness level. As the current frame terminates, in block 318, the timing controller 122 then determines an adjustment for one or more initial PWM cycles in subsequent frame periods to compensate for the deviation in the effective PWM duty cycle of the last frame period caused by the delayed presentation. The timing controller 122 then stores the determined adjustment value or other indicator, or the resulting adjusted duty cycle implemented for the next frame period, into a register, table, or other storage element, and then, at an iteration of the display process in block 310 for the subsequent frame period, retrieves the indicator to configure the EM signal 138 to provide the adjusted PWM duty cycle for one or more PWM cycles during the next frame period.

[0023] In at least one embodiment, the compensation adjustment implemented at block 318 is based on a change in the PWM duty cycle, such that an opposite change in the PWM duty cycle is introduced in one or more PWM cycles of the next frame period. That is, an increase in the duty cycle of one or more PWM cycles in the presentation delay frame period results in a corresponding decrease in the adjustment of the duty cycle of one or more PWM cycles in the subsequent compensation frame period, and conversely, a decrease in the duty cycle of one or more PWM cycles in the presentation delay frame period results in a corresponding decrease in the adjustment of the duty cycle of one or more PWM cycles in the subsequent compensation frame period. See the following reference... Figure 5 More specifically, when the effective high voltage level of the EM signal 138 remains constant between two frame periods, the net change in the total duration of the effective high voltage of the EM signal 138 during the presentation-delayed frame period relative to the total duration of the default duty cycle results in an equal and opposite change in the total duration of the effective high voltage of the EM signal 138 during the subsequent frame period. In embodiments where the effective high voltage level of the EM signal varies between frame periods, the adjustment of the duty cycle in subsequent frame periods is scaled based on the ratio of the high voltage level of the presentation-delayed frame period to the high voltage level of the subsequent frame period.

[0024] Figure 4 The illustration is based on Figure 3 The timing diagram 400 shows an example operation of system 100 in method 300. In timing diagram 400, the horizontal axis represents time (increasing from left to right). Timing row 402 represents GPU 114 (…). Figure 1 The rendering process for each corresponding frame begins with frame N-1 and ends with frame N+2. Timing line 404 indicates the buffering process for transferring the rendering frame data from frame generation subsystem 102 to GRAM 118. Timing line 406 indicates the state of TE signal 136, whereby, in this example, a valid high pulse in TE signal 136 signals frame generation subsystem 102 to begin transferring the next rendering frame to GRAM 118. Timing line 408 indicates the state of SCAN signal 142 to control the scanning of frames from GRAM 118 to display panel 106 for display, where timing line 410 represents the actual scan of each frame. Timing line 412 indicates the state of vertical sync (VSYNC) signal, which in turn indicates the timing for each frame period. In this example, the VSYNC signal is synchronized with the active high pulse in the SCAN signal 142, thereby responding to the corresponding pulse in the SCAN signal 142, the VSYNC signal is pulsed to an active low, and this pulse in the VSYNC signal initiates the start of the frame period for the corresponding frame scanned and displayed on the display panel 106. Timing line 414 represents the PWM-based EM signal 138. In this example, the default configuration is three PWM cycles of the EM signal 138 per nominal frame period, and the default or nominal PWM duty cycle is, for example, shown by PWM cycle 416.

[0025] The timing diagram 400 begins with the pixel data for frame N-2 being transferred to the GRAM 118 in response to the first pulse (pulse 418) in the TE signal 136. At the same time, the GPU 114 begins rendering frame N-l. At the end of the first pulse (pulse 420) in the VSYNC signal, the timing controller 122 and the pixel driver 120 begin scanning out and displaying frame N-2 for frame period 461. Note that the delay between the end of the first pulse 420 in the TE signal 136 and the end of the first pulse 420 in the VSYNC signal represents the delay between when frame 132 is buffered in the GRAM 118 and when the same frame 132 can begin to be scanned out to the display panel 106. As shown, the end of the first pulse 420 in the VSYNC signal, and thus the beginning of the frame period 461, is aligned with the indicated edge of the corresponding PWM period 416 of the EM signal 138. Similarly, as shown in the timing diagram 400, the rendering of frame N-l is completed on time, and thus for the second pulse 422 in the TE signal 136, the pixel data for frame N-l is transferred to the GRAM 118, and the VSYNC signal is pulsed a second pulse 424 to begin the next frame period 462 for scanning out and displaying frame N-l, which is aligned with the edge of the fifth PWM period 426.

[0026] However, as shown by the "stretching" of the third pulse 428 of the TE signal 136 used to trigger the third frame period 463, the rendering of frame N is not completed on time; that is, frame N is a render-delayed frame. Thus, rather than the third pulse 428 of the TE signal 136 terminating at point 430 (which is where the pulse in the TE signal 136 would terminate in the absence of a delayed frame), the third pulse 428 is extended to point 432, which represents the point in time at which the rendering of frame N is ultimately completed. This difference between point 430 and point 432 (i.e., the difference between the time at which the VBLANK signal is expected to be pulsed and the time at which it is actually pulsed due to the render delay) represents the "frame start delay"; that is, the amount by which the frame 462 is extended and the start of the subsequent frame 463 is delayed due to the rendering of frame N not being completed on time. It will be appreciated that the frame start delay is typically less than the frame render delay, as the default frame period is typically longer than the expected duration of the expected rendering of a typical frame.

[0027] In response to detecting a presentation delay (e.g., by detecting that the TE signal 136 is not pulsed at the expected time), the timing controller 122 starts the counter 126 and measures the duration 434 between when the end of the expected frame period 462 is signaled and when the actual signaling ends. During this same duration, the timing controller 122 configures the EM signal 138 to cause the current PWM period 436 to remain at the high voltage level, such that the high voltage level portion 438 of the PWM period 436 is longer than the duration of the high voltage level of the nominal or default PWM period 426, resulting in a net increase in the effective PWM duty cycle of the PWM period 436. Thus, to compensate for this deviation, for the first PWM period 440 of the subsequent frame period 463, the timing controller 122 configures the EM signal 138 to shorten the length of the high voltage level of the PWM period 440 by a duration 444 equal to the measured duration 434, resulting in a shortened high voltage level portion 442, which in turn results in a net decrease in the effective PWM duty cycle of the PWM period 440, which offsets the net increase in the effective PWM duty cycle of the previous PWM period 436.

[0028] In this example, the timing controller 122 configures the subsequent PWM periods of the frame period 463 to have the default duty cycle. However, in other embodiments, rather than implementing all of the compensation adjustment in just the first PWM period of the subsequent frame period, each of a number of initial PWM periods of the subsequent frame period can be configured to implement a portion of the compensation adjustment, where the portion of the compensation adjustment applied to each PWM period can be based on, for example, the number of PWM periods. To illustrate, if the low voltage level portion of the PWM period during the presentation delay frame period is lengthened by 6 milliseconds (ms) due to the delayed presentation, then the high voltage level portion of the first two PWM periods in the subsequent frame period can both be lengthened by 3 ms (= 6 ms divided by two PWM periods) to compensate.

[0029] Figure 5 A timing diagram 500 is depicted for an embodiment of the EM signal 138 to illustrate the adjustment calculation process employed by the timing controller 122 to determine the appropriate compensation adjustment based on the measured duration of the frame start delay caused by a frame with a presentation delay. As shown, the EM signal 138 has a default or nominal PWM period, which has a duration represented as t p , and is composed of a high voltage level portion with a duration of t on , and a low voltage portion with a duration of t p -t on , thus resulting in a default duty cycle DC orig = t on / t pAs further shown in timing diagram 500, the high voltage level can differ between frame periods, such as in cases where the brightness of display panel 106 is controlled not only by the PWM duty cycle but also by the voltage level of EM signal 138. Thus, EM signal 138 has a high voltage level of LI for the frame period in which the presentation is delayed and a high voltage level of L2 for the subsequent frame period, where LI can be greater than, equal to, or less than L2.

[0030] Thus, in response to detecting the delayed presentation of the frame, timing controller 122 starts counter 126 to measure the duration of the last PWM period in which the delayed presentation has caused the presentation of the delayed frame period to deviate from the default duration, denoted as t delay , resulting in a duty cycle DC delay = [(t on + t delay ) / (t p + t delay )], and then adjusts the first PWM period of the subsequent period by a corresponding duration, denoted as t comp , the high voltage level of the first PWM period of the subsequent period is denoted as t on_c , and thus has a duty cycle DC comp = t on_c / t p . In view of this, timing controller 122 can use logic configured to implement the following expressions to determine the compensations t comp and t on_c to implement:

[0031]

[0032] The following provides several examples of the above aspects:

[0033] Example 1. A method comprising:

[0034] controlling brightness of a frame displayed at a display panel via pulse width modulation (PWM) of a brightness control signal provided to the display panel;

[0035] determining a deviation of a duty cycle of a first PWM period of the brightness control signal from a default duty cycle resulting from a delay in presentation of the frame; and

[0036] adjusting a duty cycle of at least a second PWM period following the first PWM period to compensate for the deviation in the duty cycle of the first PWM period.

[0037] Example 2. The method of example 1, wherein:

[0038] the deviation in the duty cycle of the first PWM period is an increase in the duty cycle of the first PWM period relative to the default duty cycle; and

[0039] Adjusting the duty cycle of at least the second PWM cycle includes decreasing the duty cycle of at least the second PWM cycle.

[0040] Example 3. The method of example 1, wherein:

[0041] the deviation in the duty cycle of the first PWM cycle is a decrease in the duty cycle of the first PWM cycle relative to the default duty cycle; and

[0042] Adjusting the duty cycle of at least the second PWM cycle includes increasing the duty cycle of at least the second PWM cycle.

[0043] Example 4. The method of any of examples 1-3, wherein:

[0044] determining the deviation in the duty cycle of the first PWM cycle includes measuring a duration of the first PWM cycle that is longer than a duration of a default PWM cycle having the default duty cycle; and

[0045] Adjusting the duty cycle of at least the second PWM cycle includes adjusting the duty cycle of at least the second PWM cycle based on the measured duration.

[0046] Example 5. The method of example 4, wherein:

[0047] the brightness control signal has a first high voltage level for the first PWM cycle and a second high voltage level for the second PWM cycle, the second high voltage level being different than the first high voltage level; and

[0048] Adjusting the duty cycle of at least the second PWM cycle includes adjusting the duty cycle of at least the second PWM cycle further based on a ratio of the first high voltage level to the second high voltage level.

[0049] Example 6. The method of any of examples 1-5, wherein adjusting the duty cycle of at least the second PWM cycle to compensate for the deviation in the duty cycle of the first PWM cycle includes adjusting the duty cycle of at least the second PWM cycle such that an average duty cycle of the brightness control signal for the first PWM cycle and at least the second PWM cycle is approximately equal to the default duty cycle.

[0050] Example 7. The method of any of examples 1-5, wherein adjusting the duty cycle of at least the second PWM cycle includes adjusting the duty cycle of a plurality of PWM cycles following the first PWM cycle based on the deviation, the plurality of PWM cycles including the second PWM cycle, and wherein the duty cycle of each of the plurality of PWM cycles is adjusted based on the deviation and based on a number of PWM cycles in the plurality of PWM cycles.

[0051] Example 8. A display system configured to perform the method of any of the preceding examples.

[0052] Example 9. A non-transitory computer-readable medium storing a set of executable instructions configured to manipulate at least one processor to perform the method of any of examples 1-8.

[0053] Example 10. A system comprising:

[0054] a frame generation subsystem configured to present a sequence of frames; and

[0055] a display control subsystem coupled to the frame generation subsystem and couplable to a display panel, the display control subsystem configured to:

[0056] provide a luminance control signal configured to control luminance of frames displayed on the display panel by pulse width modulation (PWM) of the luminance control signal;

[0057] determine a deviation of a duty cycle of a first PWM period of the luminance control signal from a default duty cycle resulting from a delay in the presentation of the frames; and

[0058] adjust a duty cycle of at least a second PWM period following the first PWM period to compensate for the deviation in the duty cycle of the first PWM period.

[0059] Example 11. The system of example 10, wherein:

[0060] the deviation in the duty cycle of the first PWM period is an increase in the duty cycle of the first PWM period relative to the default duty cycle; and

[0061] the display control subsystem is configured to adjust the duty cycle of the at least the second PWM period by decreasing the duty cycle of the at least the second PWM period.

[0062] Example 12. The system of example 10, wherein:

[0063] the deviation in the duty cycle of the first PWM period is a decrease in the duty cycle of the first PWM period relative to the default duty cycle; and

[0064] the display control subsystem is configured to adjust the duty cycle of the at least the second PWM period by increasing the duty cycle of the at least the second PWM period.

[0065] Example 13. The system of any of examples 10-12, wherein:

[0066] The display control subsystem is configured to determine the deviation in the duty cycle of the first PWM cycle by measuring a duration of the first PWM cycle that is longer than a duration of a default PWM cycle having a default duty cycle; and

[0067] The display control subsystem is configured to adjust the duty cycle of at least the second PWM cycle based on the measured duration.

[0068] Example 14. The system of example 13, wherein:

[0069] The brightness control signal has a first high voltage level for the first PWM cycle and a second high voltage level for the second PWM cycle, the second high voltage level being different than the first high voltage level; and

[0070] The display control subsystem is configured to further adjust the duty cycle of at least the second PWM cycle based on a ratio of the first high voltage level to the second high voltage level.

[0071] Example 15. The system of any of examples 10 to 14, wherein the display control subsystem is configured to adjust the duty cycle of at least the second PWM cycle to compensate for the deviation in the duty cycle of the first PWM cycle such that an average duty cycle of the brightness control signal of the first PWM cycle and at least the second PWM cycle is approximately equal to the default duty cycle.

[0072] Example 16. The system of any of examples 10 to 14, wherein the display control subsystem is configured to adjust the duty cycle of a plurality of PWM cycles following the first PWM cycle, the plurality of PWM cycles including the second PWM cycle, and wherein the duty cycle of each of the plurality of PWM cycles is adjusted based on the deviation and based on a number of PWM cycles in the plurality of PWM cycles.

[0073] Example 17. The system of any of examples 10 to 16, further comprising:

[0074] A display panel.

[0075] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer- readable storage medium. The software can include the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium can include, for example, a magnetic or optical disk storage such as a compact disk (CD) or digital versatile disk (DVD), solid state storage such as flash memory, cache memory, random access memory (RAM) and / or one or more other non-transitory machine-readable storage devices. The executable instructions described above can be implemented using source code, assemblies, instructions generated by a compiler, or other instructions derived from a programming language.

[0076] A computer readable storage medium includes any storage medium, or combination of storage media, accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but is not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash), or microelectromechanical systems (MEMS)-based storage media. The computer readable storage medium can be embedded in the computing system (e.g., system RAM or ROM), fixedly attached to the computing system (e.g., a magnetic hard drive), removably attached to the computing system (e.g., an optical disc or Universal Serial Bus (USB)-based Flash memory), or coupled to the computer system via a wired or wireless network (e.g., network accessible storage (NAS)).

[0077] Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device can not be required, and that one or more other activities or devices can be employed. Further, the order in which activities are listed are not necessarily the order in which they are performed. Also, the concepts have been described with reference to particular embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

[0078] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems and any feature(s) that can cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims. Furthermore, the particular embodiments disclosed above are illustrative only as to a possible implementation and are not intended to limit the claimed subject matter in any way, nor is the claimed subject matter in any way limited to the precise embodiments disclosed in the specification. Thus, it is contemplated that the claimed subject matter can also be implemented in different ways than those specifically set forth herein, without departing from the spirit or scope of the claimed subject matter. Accordingly, it is apparent that the specific embodiments disclosed above can be altered or modified in various ways without departing from the scope or spirit of the disclosure. Accordingly, it is submitted that the scope of the disclosure should not be limited by the specific disclosed embodiments, but should be given the broadest possible interpretation in accordance with the principles and features disclosed herein.

Claims

1. A method comprising: controlling a luminance of a frame displayed at a display panel via pulse width modulation (PWM) of a luminance control signal provided to the display panel; measuring a frame start delay associated with a deviation of a duty cycle of a first PWM period of the luminance control signal from a default duty cycle; and adjusting a duty cycle of at least a second PWM period following the first PWM period to compensate for the measured frame start delay.

2. The method of claim 1, wherein: the deviation in the duty cycle of the first PWM period is an increase in the duty cycle of the first PWM period from the default duty cycle; and adjusting the duty cycle of at least the second PWM period comprises decreasing the duty cycle of at least the second PWM period.

3. The method of claim 1, wherein: the deviation in the duty cycle of the first PWM period is a decrease in the duty cycle of the first PWM period from the default duty cycle; and adjusting the duty cycle of at least the second PWM period comprises increasing the duty cycle of at least the second PWM period.

4. The method of claim 1, wherein: determining the deviation in the duty cycle of the first PWM period comprises measuring an extended duration of the first PWM period compared to a duration of a default PWM period having the default duty cycle; and adjusting the duty cycle of at least the second PWM period comprises adjusting the duty cycle of at least the second PWM period by the measured frame start delay.

5. The method of claim 4, wherein: the luminance control signal has a first high voltage level for the first PWM period and a second high voltage level for the second PWM period, the second high voltage level being different from the first high voltage level; and adjusting the duty cycle of at least the second PWM period comprises adjusting the duty cycle of at least the second PWM period further based on a ratio of the first high voltage level to the second high voltage level. adjusting the duty cycle of at least the second PWM period to compensate for the deviation in the duty cycle of the first PWM period comprises adjusting the duty cycle of at least the second PWM period such that an average duty cycle of the luminance control signal for the first PWM period and at least the second PWM period is approximately equal to the default duty cycle. adjusting the duty cycle of at least the second PWM period comprises adjusting the duty cycle of a plurality of PWM periods following the first PWM period based on the deviation, the plurality of PWM periods including the second PWM period, and wherein the duty cycle of each of the plurality of PWM periods is adjusted based on the deviation and based on a number of PWM periods in the plurality of PWM periods.

8. A display system configured to perform the method of any of claims 1-7. ​ 6. The method of any one of claims 1 to 5, wherein, ​ 7. The method of any one of claims 1 to 5, wherein, ​ ​ 9. A non-transitory computer-readable medium storing a set of executable instructions that, when executed by at least one processor, cause the at least one processor to perform the method of any one of claims 1-7.

10. A system comprising: a frame generation subsystem configured to present a sequence of frames; and a display control subsystem coupled to the frame generation subsystem and couplable to a display panel, the display control subsystem configured to: provide a brightness control signal configured to control a brightness of a frame displayed at the display panel via a pulse width modulation (PWM) of the brightness control signal; measure a frame start delay associated with a deviation of a duty cycle of a first PWM period of the brightness control signal from a default duty cycle; and adjust a duty cycle of at least a second PWM period following the first PWM period to compensate for the measured frame start delay.

11. The system of claim 10, wherein: the deviation in the duty cycle of the first PWM period is an increase of the duty cycle of the first PWM period from the default duty cycle; and the display control subsystem is configured to adjust the duty cycle of at least the second PWM period by decreasing the duty cycle of at least the second PWM period.

12. The system of claim 10, wherein: the deviation in the duty cycle of the first PWM period is a decrease of the duty cycle of the first PWM period from the default duty cycle; and the display control subsystem is configured to adjust the duty cycle of at least the second PWM period by increasing the duty cycle of at least the second PWM period.

13. The system of claim 10, wherein: the display control subsystem is configured to determine the deviation in the duty cycle of the first PWM period by measuring an extended duration of the first PWM period compared to a duration of a default PWM period having the default duty cycle; and the display control subsystem is configured to adjust the duty cycle of at least the second PWM period by the measured frame start delay.

14. The system of claim 13, wherein: the brightness control signal has a first high voltage level for a first of the PWM periods and a second high voltage level for the second PWM period, the second high voltage level being different from the first high voltage level; and the display control subsystem is configured to adjust the duty cycle of at least the second PWM period further based on a ratio of the first high voltage level to the second high voltage level. the display control subsystem is configured to adjust the duty cycle of at least the second PWM period to compensate for the deviation in the duty cycle of the first PWM period such that an average duty cycle of the brightness control signal for the first PWM period and at least the second PWM period is approximately equal to the default duty cycle. ​ ​ 15. The system of any one of claims 10 to 14, wherein, ​ 16. The system of any one of claims 10 to 14, wherein, The display control subsystem is configured to adjust the duty cycle for a plurality of PWM cycles after the first PWM cycle, the plurality of PWM cycles including the second PWM cycle, and wherein the duty cycle for each of the plurality of PWM cycles is adjusted based on the deviation and based on a number of PWM cycles in the plurality of PWM cycles.

17. The system of any of claims 10 to 14, further comprising: the display panel.

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