Substrate integrated with passive device and method of manufacturing the same
By integrating passive devices on a transparent dielectric layer, using laser modification and HF etching to form interconnect vias, and combining electroplating and patterning processes to fabricate coil structures for inductors and capacitors, the problems of large size and high power consumption of passive devices on RF PCBs are solved, achieving high-performance, miniaturized and low-power passive device integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2021-04-23
- Publication Date
- 2026-05-19
AI Technical Summary
The discrete passive devices on existing RF PCBs are large in size, have high power consumption, many solder joints, and large variations in parasitic parameters, making it difficult to meet the requirements of miniaturization, thinness, and high performance. In addition, Si-based integrated passive devices have high microwave loss, and GaAs-based devices are expensive.
Passive devices are integrated using a transparent dielectric layer (such as a glass substrate). Vias are formed by laser modification and HF etching, and coil structures of inductors and capacitors are fabricated by electroplating and patterning processes, thus achieving the integration of passive devices.
It achieves high-performance integration of passive components, and has the advantages of miniaturization, lightweight and low power consumption, making it suitable for mobile communication terminals such as 5G mobile phones.
Smart Images
Figure CN115516761B_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of radio frequency device technology, specifically relating to a substrate integrating passive devices and its fabrication method. Background Technology
[0002] In contemporary times, the consumer electronics industry is developing rapidly, with mobile communication terminals, especially 5G phones, evolving quickly. Phones need to process an increasing number of signal frequency bands, leading to a surge in the number of radio frequency (RF) chips required. Meanwhile, the preferred form factors for mobile phones are miniaturization, thinness, and long battery life. Traditional mobile phones contain numerous discrete components on their RF PCBs, such as resistors, capacitors, inductors, and filters. These components suffer from drawbacks such as large size, high power consumption, numerous solder joints, and significant parasitic parameter variations, making them unsuitable for future demands. The interconnection and matching of RF chips require small-area, high-performance, and highly consistent integrated passive devices. Currently, integrated passive devices on the market are mainly based on Si (silicon) and GaAs (gallium arsenide) substrates. Si-based integrated passive devices are inexpensive, but trace impurities in Si (poor insulation) result in higher microwave losses and generally lower performance. GaAs-based integrated passive devices offer superior performance but are expensive. Summary of the Invention
[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a substrate integrating passive devices and a method for fabricating the same.
[0004] In a first aspect, embodiments of this disclosure provide a method for fabricating a substrate integrating passive devices, comprising:
[0005] A transparent dielectric layer is provided, and the transparent dielectric layer is processed to obtain the transparent dielectric layer having a first connection via; the transparent dielectric layer includes a first surface and a second surface disposed opposite to each other along the thickness direction;
[0006] Passive devices are integrated on the transparent dielectric layer; the passive devices include at least an inductor; wherein,
[0007] Integrating the passive device on the transparent dielectric layer includes:
[0008] A first substructure is formed on the first surface of the transparent dielectric layer, a second substructure is formed on the second surface, and a first connection electrode is formed in the first connection via; the first substructure, the first connection electrode and the second substructure are connected to form an inductor coil structure.
[0009] The preparation method includes:
[0010] A transparent dielectric layer is provided, and the transparent dielectric layer is etched to form a first blind via;
[0011] Through patterning processes, a first connecting electrode and a first substructure are formed within the first blind hole;
[0012] The transparent dielectric layer is thinned on the side opposite to the first substructure to expose the first connection electrode and form the first connection via.
[0013] A pattern including the second substructure is formed on the second surface of the transparent dielectric layer; the second substructure, the first connecting electrode, and the first substructure are connected to form an inductor coil structure.
[0014] The provision of a transparent dielectric layer and the etching of the transparent dielectric layer to form a first blind via includes:
[0015] The transparent dielectric layer is modified by laser, and the first blind hole is formed by HF etching.
[0016] The first connecting electrode and the first substructure are formed within the first blind hole through a patterning process.
[0017] A first metal material is sequentially substrateed on the transparent dielectric layer on which the first blind hole is formed, and the first metal material is electroplated to form a first metal film layer;
[0018] A first protective layer and a first planarization layer are sequentially formed on the side of the first metal film layer away from the transparent dielectric layer, and a pattern including the first connecting electrode and the first substructure is formed by a patterning process.
[0019] The preparation method includes:
[0020] A first substrate is provided, and the transparent dielectric layer is attached to the first substrate; the transparent dielectric layer has a first connection via.
[0021] A first metal material is deposited on the first and second surfaces of the transparent dielectric layer, respectively. Through an electroplating process, the first metal material at least covers the sidewall of the first connection via and forms a first metal film layer on the first surface.
[0022] The first metal film layer is patterned to form a pattern including a first substructure;
[0023] A pattern including the second substructure is formed on the second surface of the transparent dielectric layer; the second substructure, the first connecting electrode, and the first substructure are connected to form an inductor coil structure.
[0024] The method includes providing a first substrate and attaching the transparent dielectric layer onto the first substrate, comprising:
[0025] The first and second surfaces of the transparent dielectric layer are laser modified respectively, and the first connection via is formed by HF etching.
[0026] The first metal film layer covers the sidewall of the first connection via, and the method further includes the following steps before forming the first metal film layer:
[0027] A first planarization layer is formed on the side of the first metal material opposite to the transparent dielectric layer, so that the first planarization layer fills the first connection via.
[0028] The process of forming the first substructure also includes:
[0029] A second protective layer and a second planarization layer are sequentially formed on the side of the first substructure opposite to the transparent dielectric layer.
[0030] The passive device further includes a capacitor; while forming the second substructure on the second surface, a first electrode plate of the capacitor is also formed; the fabrication method further includes:
[0031] A first interlayer dielectric layer is formed on the side of the first plate of the capacitor that is away from the transparent dielectric layer.
[0032] The second electrode of the capacitor is formed on the side of the first interlayer dielectric layer opposite to the transparent dielectric layer;
[0033] A second interlayer dielectric layer is formed on the side of the second plate of the capacitor away from the transparent dielectric layer, and a second connection via is formed through the first interlayer dielectric layer and the second interlayer dielectric layer, and a third connection via is formed through the second interlayer dielectric layer;
[0034] A second interlayer dielectric layer is formed on the side opposite to the transparent dielectric layer, and a pattern including a second connection electrode and a connection pad is formed by a patterning process; the second connection electrode connects the second substructure and the second plate of the capacitor through the second connection via and the third connection via.
[0035] Specifically, in the layer where the second connection electrode and the connection pad are located, away from the transparent dielectric layer, a first buffer layer and a third planarization layer are deposited sequentially, and a fourth connection via is formed through the first buffer layer and the third planarization layer, and the fourth connection via exposes the connection pad.
[0036] The transparent medium layer includes a glass substrate.
[0037] This disclosure provides a substrate integrating passive devices, comprising: a transparent dielectric layer and passive devices integrated on the dielectric layer; wherein,
[0038] The transparent dielectric layer includes a first surface and a second surface disposed opposite to each other along its thickness direction; the transparent dielectric layer has a first connecting via hole penetrating along its thickness direction.
[0039] The passive device includes at least an inductor; the inductor includes a first substructure disposed on the first surface and a second substructure disposed on the second surface, and a first connection electrode disposed in the first connection via to connect the first substructure and the second substructure in series.
[0040] The passive device further includes a capacitor; wherein the first electrode of the capacitor is disposed on the same layer as the second substructure of the inductor; the substrate further includes a first interlayer dielectric layer located on the side of the first electrode of the capacitor facing away from the transparent dielectric layer; and the second electrode of the capacitor is located on the side of the first interlayer dielectric layer facing away from the first electrode of the capacitor.
[0041] The transparent medium layer includes a glass substrate. Attached Figure Description
[0042] Figure 1 This is a top view of an inductor according to an embodiment of this disclosure.
[0043] Figure 2 This is a three-dimensional structural diagram of the LC oscillation circuit according to an embodiment of the present disclosure.
[0044] Figure 3 This is a cross-sectional view of a substrate integrating passive devices according to an embodiment of this disclosure.
[0045] Figure 4a This is a schematic diagram of the substrate formed in step S11 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0046] Figure 4b This is a schematic diagram of the substrate formed in step S12 (1) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0047] Figure 4c This is a schematic diagram of the substrate formed in step S12 (2) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0048] Figure 4d This is a schematic diagram of the substrate formed in steps (3) and (4) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0049] Figure 4eThis is a schematic diagram of the substrate formed in step S12 (5) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0050] Figure 4f This is a schematic diagram of the substrate formed in step S13 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0051] Figure 4g This is a schematic diagram of the substrate formed in step S14 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0052] Figure 4h This is a schematic diagram of the substrate formed in step S15 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0053] Figure 4i This is a schematic diagram of the substrate formed in step S16 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0054] Figure 4j This is a schematic diagram of the substrate formed in step S17 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0055] Figure 4k This is a schematic diagram of the substrate formed in step S18 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0056] Figure 5a This is a schematic diagram of the substrate formed in step S21 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0057] Figure 5b and 5c This is a schematic diagram of the substrate formed in step S22 (1) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0058] Figure 5d This is a schematic diagram of the substrate formed in step S22 (2) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0059] Figure 5e This is a schematic diagram of the substrate formed in step S22 (3) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0060] Figure 5f This is a schematic diagram of the substrate formed in step S22 (4) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0061] Figure 5g This is a schematic diagram of the substrate formed in step S23 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0062] Figure 5h This is a schematic diagram of the substrate formed in steps S24-S27 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0063] Figure 5i This is a schematic diagram of the substrate formed in step S28 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.
[0064] Figure 6a and 6b This is a schematic diagram of forming a first connecting electrode in another method for fabricating a substrate with integrated passive devices according to an embodiment of this disclosure. Detailed Implementation
[0065] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0067] This disclosure provides a substrate with integrated passive components and a method for fabricating the same. The passive components, such as capacitors, inductors, and resistors, are integrated on the substrate to form a circuit structure. This disclosure uses an LC oscillation circuit integrated on the substrate as an example. That is, at least inductors and capacitors are integrated on the substrate. It should be understood that, depending on the circuit function and performance, resistors and other components may also be integrated on the substrate.
[0068] Figure 1 This is a top view of the inductor according to an embodiment of the present disclosure, with reference to... Figure 1Each of the first substructures 211 of the inductor extends along a first direction and is arranged side by side along a second direction; each of the second substructures 212 of the inductor extends along a third direction and is arranged side by side along the second direction. The first direction, second direction, and third direction are all different directions. In this embodiment, the first direction and second direction are perpendicular to each other, and the first direction and third direction intersect but are not perpendicular, as an example. Of course, the extension directions of the first substructures 211 and second substructures 212 can also be interchanged, all within the protection scope of this embodiment. Furthermore, in this embodiment, an inductor comprising N first substructures 211 and N-1 second substructures 212 is used as an example, where N≥2 and N is an integer. The first end and the second end of the first substructure 211 respectively at least partially overlap with the orthographic projection of a first connection via 11 onto the glass substrate 10. Furthermore, the first end and the second end of one first substructure 211 correspond to different first connection vias 11, that is, the orthographic projection of one first substructure 211 onto two first connection vias 11 at least partially overlaps. At this time, the first end of the i-th second substructure 212 of the inductor is connected to the first end of the i-th first substructure 211 and the second end of the (i+1)-th first substructure 211 to form an inductor coil, where 1≤i≤N-1 and i is an integer.
[0069] It should be noted that, in this configuration, the first lead end 22 is connected to the second end of the first substructure 211 of the inductor coil, and the second lead end 23 is connected to the first end of the Nth substructure 211. Furthermore, the first lead end 22 and the second lead end 23 can be disposed on the same layer as the second substructure 212 and made of the same material. In this case, the first lead end 22 can be connected to the second end of the first substructure 211 through the first connecting via 11, and correspondingly, the second lead end 23 can be connected to the first end of the Nth substructure 211 through the first connecting via 11.
[0070] Figure 2 This is a three-dimensional structural diagram of the LC oscillation circuit according to an embodiment of the present disclosure; as shown Figure 2 As shown, the LC oscillation circuit includes an inductor and a capacitor 3; wherein the inductor includes multiple first substructures 211, multiple second substructures 212, and multiple first connecting electrodes 213; the first substructures 211 and second substructures 212 are disposed at opposite ends of the first connecting electrodes 213, and the first connecting electrodes 213 connect the first substructures 211 and second substructures 212 to each other, forming a three-dimensional inductor coil structure (hereinafter referred to as an inductor coil). Continuing to refer to... Figure 2The first lead 22 of the inductor coil is connected to the first connecting pad 41, the second lead 23 of the inductor coil is connected to the first plate 31 of the capacitor 3, the second plate 32 of the capacitor 3 is connected to the second connecting pad 42, and the first connecting pad 41 and the second connecting pad 42 are connected to the positive and negative terminals of the current source or voltage source, respectively.
[0071] Figure 3 This is a cross-sectional view of a substrate integrating passive devices according to an embodiment of this disclosure; as shown... Figure 3 As shown in the present embodiment, the LC oscillation circuit is integrated on a transparent dielectric layer, which includes a first surface and a second surface disposed opposite to each other along its thickness direction, and the transparent dielectric layer has a first connection via 11 extending through its thickness direction; a first connection electrode 213 of an inductor coil is formed in the first connection via 11, a first substructure 211 of the inductor coil is formed on the first surface of the transparent dielectric layer, and a second substructure 212 of the inductor coil is formed on the second surface of the transparent dielectric layer.
[0072] In this embodiment, the transparent dielectric layer includes, but is not limited to, any one of a glass substrate 10, a flexible substrate, and an interlayer dielectric layer including at least an organic insulating layer. Since integrating passive devices onto the glass substrate 10 offers advantages such as small size, light weight, high performance, and low power consumption, the transparent dielectric layer in this embodiment is preferably made of a glass substrate 10. The following description uses a glass substrate 10 as an example for the transparent dielectric layer.
[0073] Continue to refer to Figure 3 The first electrode 31 of capacitor 3 is disposed on the second surface of glass substrate 10 and is disposed in the same layer as the second substructure 212 of inductor coil. A first interlayer dielectric layer 9 is disposed on the side of the first electrode 31 of capacitor 3 away from glass substrate 10, and a second electrode 32 of capacitor 3 is disposed on the side of the first interlayer dielectric layer 9 away from the first electrode 31 of capacitor 3. A second interlayer dielectric layer 12 is disposed on the layer of the second electrode 32 of capacitor 3 away from glass substrate 10. A second connecting electrode 13 and a connecting pad 4 are disposed on the side of the second interlayer dielectric layer 12 away from glass substrate 10. The second connecting electrode 13 connects the second lead of inductor coil and the second electrode 32 of capacitor 3 through a second connecting via 121 penetrating the first interlayer dielectric layer 9 and the second interlayer dielectric layer 12, and a third connecting via 122 penetrating the second interlayer dielectric layer 12. The connecting pad 4 is connected to the first electrode 31 of capacitor 3.
[0074] Continuing with reference to point 3, a second protective layer 7 and a second planarization layer 8 can be formed on the side of the first substructure 211 facing away from the glass substrate 10 to protect the first substructure 211 from water and oxygen corrosion. Correspondingly, a first buffer layer 14 and a third planarization layer 15 can also be formed on the side of the second connecting electrode 13 and the connecting pad 4 facing away from the glass substrate 10 to protect the connecting electrode, the second substructure 212, the capacitor 3, and other devices. It should be noted that a fourth connecting via 16 is formed at the position corresponding to the connecting pad 4, penetrating the first buffer layer 14 and the third planarization layer 15, to facilitate signal loading.
[0075] The structural parameters of each device on the substrate integrating passive devices in the embodiments of this disclosure will be described one by one in the following preparation method, and therefore will not be described in detail here.
[0076] This disclosure provides a method for fabricating a substrate integrating passive devices. The substrate can be the substrate described above. The fabrication method includes the following steps:
[0077] A glass substrate 10 is provided and processed to obtain a glass substrate 10 having a first connecting via 11; the glass substrate 10 includes a first surface and a second surface disposed opposite to each other along the thickness direction.
[0078] Passive devices are integrated on the glass substrate 10; the passive devices include at least inductors.
[0079] Among them, the passive devices integrated on the glass substrate 10 include:
[0080] A first substructure 211 is formed on the first surface of the glass substrate 10, a second substructure 212 is formed on the second surface, and a first connecting electrode 213 is formed in the first connecting via 11; the first substructure 211, the first connecting electrode 213 and the second substructure 212 are connected to form an inductor coil.
[0081] To clarify the fabrication method in the embodiments of this disclosure, the fabrication method of the substrate integrating passive devices in the embodiments of this disclosure will be described below with reference to the accompanying drawings and specific embodiments.
[0082] The first example shows that the method for fabricating the substrate integrating passive devices specifically includes the following steps:
[0083] S11. Provide a transparent dielectric layer and etch the transparent dielectric layer to form a first blind via 110, such as... Figure 4a As shown.
[0084] In some examples, step S11 may specifically include the following steps:
[0085] (1) Cleaning: Glass substrate 10 is put into the cleaning machine for cleaning.
[0086] In some examples, the thickness of the glass substrate 10 is around 0.1mm-1.1mm.
[0087] (2) Laser drilling: A laser beam is used to modify the first surface of the glass substrate 10 by perpendicularly incident on the laser beam, thereby forming multiple first blind holes 110 on the glass substrate 10. Specifically, when the laser beam interacts with the glass substrate 10, the high energy of the laser photons ionizes the atoms in the glass substrate 10 and ejects them from the surface of the glass substrate 10. As time increases, the hole gradually deepens until the first blind hole 110 is formed. Among them, the laser wavelengths that can generally be selected are 532nm, 355nm, 266nm, 248nm, 197nm, etc., the laser pulse width can be selected as 1-100fs, 1-100ps, 1-100ns, etc., and the laser type can be a continuous laser, a pulsed laser, etc. The laser drilling methods can include, but are not limited to, the following two. In the first method, when the spot diameter is large, the relative position of the laser beam and the glass substrate 10 is fixed. High energy directly penetrates the glass substrate 10 to a preset depth. The resulting first blind hole 110 is shaped like an inverted frustum, with the diameter decreasing from top to bottom (from the second surface to the first surface). In the second method, when the spot diameter is small, the laser beam scans in a circle on the glass substrate 10. The focal point and focal depth of the laser beam continuously change, drawing a spiral from the lower surface (first surface) to the upper surface (second surface) of the glass substrate 10, with the spiral radius decreasing from bottom to top. The glass substrate 10 is thus laser-cut into a frustum shape to form the first blind hole 110, which is also shaped like a frustum.
[0088] (3) HF etching: During the laser drilling process, a stress zone is formed on the inner surface of the first blind hole 110 in an area of about 5-20 micrometers near the hole. In this area, the surface of the glass substrate 10 is uneven, exhibiting a molten state with many burrs, and contains a large number of microcracks and macrocracks, as well as residual stress. At this time, a 2%-20% HF etching solution is used to perform wet etching for a certain period of time at an appropriate temperature to etch away the glass in the stress zone, making the interior and surface of the first blind hole 110 and the area near the hole smooth and flat, free of microcracks and macrocracks, and completely etching away the stress zone.
[0089] S12. Through patterning process, the first connecting electrode 213 and the first substructure 211 located in the first blind hole 110 are formed.
[0090] In some examples, step S12 may specifically include the following steps:
[0091] (1) Seed layer growth: A first metallic material 200 is formed on the first surface of the glass substrate 10 by measurement and control sputtering as a seed layer, such as... Figure 4bAs shown.
[0092] In some examples, the first metal material 200 includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal film 201 is approximately 100 nm to 500 nm, and may further be 50 nm to 35 μm. In the following description, copper is used as an example as the material of the first metal film 201.
[0093] In some examples, to increase the adhesion between the first metal material 200 and the first surface of the glass substrate 10, an auxiliary metal film layer can be formed on the first surface of the glass substrate 10 by means including but not limited to magnetron sputtering before forming the first metal material 200. The material of the auxiliary metal film layer includes, but is not limited to, at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is about 2nm-20nm.
[0094] (2) Electroplating: The glass substrate 10 is placed on the electroplating machine carrier, and an electric soldering pad is pressed on. It is then placed in a hole-filling electroplating tank (using a special hole-filling electrolyte). Current is applied, and the electroplating solution remains continuously and rapidly flowing on the first surface of the glass substrate 10. Cations in the electroplating solution gain electrons on the inner wall of the first blind hole 110, becoming atoms and depositing on the inner wall. Using a specially formulated hole-filling electrolyte, high-speed deposition of metallic copper (deposition rate 0.5-3 μm / min) is achieved primarily within the first blind hole 110. Since the first surface of the glass substrate 10 is a flat area, the deposition rate of metallic copper on these two surfaces is extremely low (0.005-0.05 μm / min). Over time, the metallic copper on the inner wall of the first blind hole 110 gradually thickens, forming a first metal film layer 201. At this point, the first metal film layer 201 grows by more than 5 μm compared to the first metal material 200. Figure 4c As shown.
[0095] (3) Formation of the protective layer: A first protective layer 5 is formed on the side of the first metal film layer 201 facing away from the glass substrate 10, such as Figure 4d As shown. The material of the first protective layer 5 is an inorganic insulating material. For example, the first protective layer 5 can be an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a combination of several stacked films of SiNx inorganic insulating layer and SiO2 inorganic insulating layer.
[0096] (4) Formation of the first planarization layer 6: The first planarization layer 6 is formed on the surface of the first protective layer 5 away from the glass substrate 10, such as... Figure 4dThe first planarization layer 6 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, and other resin-based materials. Alternatively, the organic insulating material may include an elastic material, such as urethane or thermoplastic polyurethane (TPU).
[0097] (5) Patterning of the first surface film layer: The first planarization layer 6 on the second surface is exposed, developed, and then etched. After etching, the resist is stripped, and the patterning of the first protective layer 5, the first planarization layer 6, and the first metal film layer 201 on the first surface is completed. At this time, the first substructure 211 of the inductor coil and the first connecting electrode 213 located on the first surface are formed, as shown in the figure. Figure 4e As shown.
[0098] S13. A second protective layer 7 and a second planarization layer 8 are sequentially formed on the side of the first planarization layer 6 opposite to the glass substrate 10, such as... Figure 4f As shown. The second protective layer 7 can be made of the same material as the first protective layer 5, so it will not be described again here. The second planarization layer 8 can be made of the same material as the first planarization layer 6, so it will not be described again here.
[0099] S14. The first planarization layer 6 is bonded to the first substrate 101, the glass substrate 10 is flipped, and the side of the glass substrate 10 facing away from the first substructure 211 is thinned to expose the first connection electrode 213, and the first connection via 11 is formed. Figure 4g As shown.
[0100] S15. On the second surface of the glass substrate 10, a pattern including a second substructure 212 of an inductor coil and a first plate 31 of a capacitor 3 is formed by a patterning process, such as... Figure 4h As shown.
[0101] In some examples, step S15 may specifically include forming a second metal film layer by means including but not limited to magnetron sputtering, applying adhesive, exposure, development, followed by wet etching, stripping the adhesive after etching, to form a pattern including a second substructure 212 of an inductor coil and a first plate 31 of a capacitor 3.
[0102] S16. A first interlayer dielectric layer 9 is formed on the side of the second substructure 212 of the inductor coil and the first electrode 31 of the capacitor 3 facing away from the glass substrate 10, and a pattern including the second electrode 32 of the capacitor 3 is formed on the side of the first interlayer dielectric layer 9 facing away from the glass substrate 10, as shown. Figure 4i As shown.
[0103] In some examples, the material of the first interlayer dielectric layer 9 is an inorganic insulating material. For example, the first interlayer dielectric layer 9 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a combination of several stacked films of SiNx inorganic insulating layers and SiO2 inorganic insulating layers. Of course, this first interlayer dielectric layer 9 also serves as the intermediate dielectric layer of the capacitor 3.
[0104] In some examples, the second electrode 32 of capacitor 3 can be formed by magnetron sputtering to form a third metal film layer on the side of the first interlayer dielectric layer 9 away from the glass substrate 10, followed by resist coating, exposure, development, wet etching, and stripping after etching to form a pattern including the second electrode 32 of capacitor 3.
[0105] S17. A second interlayer dielectric layer 12 is formed on the side of the second electrode plate 32 of capacitor 3 facing away from the glass substrate 10, and a second connection via 121 penetrating the first dielectric layer and the second interlayer dielectric layer 12, and a third connection via 122 penetrating the second interlayer dielectric layer 12 are formed, as shown. Figure 4j As shown.
[0106] The material of the second interlayer dielectric layer 12 can be the same as that of the first interlayer dielectric layer 9, so it will not be described again here.
[0107] S18. On the side of the second interlayer dielectric layer 12 facing away from the glass substrate 10, a pattern including the second connecting electrode 13 and the connecting pad 4 is formed by a patterning process, such as... Figure 4k As shown.
[0108] In some examples, step S18 may include forming a fourth metal film layer by magnetron sputtering, applying resist, exposing, developing, followed by wet etching, and stripping the resist after etching to form a pattern including the second connecting electrode 13 and the connecting pad 4. The material of the fourth metal film layer can be the same as the material of the first metal film layer 201, so it will not be described further here.
[0109] S19. On the side of the layer containing the second connecting electrode 13 and the connecting pad 4 that is away from the glass substrate 10, a first buffer layer 14 and a third planarization layer 15 are deposited sequentially, and the first substrate 101 is peeled off. Figure 3 As shown.
[0110] In some examples, the material of the first buffer layer 14 can be the same as the material of the first protective layer 5, so it will not be described again here. The material of the third planarization layer 15 can be the same as the material of the first planarization layer 6, so it will not be described again here.
[0111] This completes the fabrication of the substrate for integrating passive devices.
[0112] The second example, the method for fabricating the substrate integrating passive devices, specifically includes the following steps:
[0113] S21. A glass substrate 10 is provided, and the first and second surfaces of the glass substrate 10 are laser-modified by laser, and a glass substrate 10 with a first connecting via 11 is formed by HF etching. Figure 5a As shown.
[0114] In some examples, step S21 may specifically include the following steps:
[0115] (1) Cleaning: Glass substrate 10 is put into the cleaning machine for cleaning.
[0116] In some examples, the thickness of the glass substrate 10 is around 0.1mm-1.1mm.
[0117] (2) Laser drilling: A laser is used to drill the first surface of the glass substrate 10 in a vertically incident manner to form a first sub-via on the first surface side of the glass substrate 10. Similarly, a laser is used to drill the second surface of the glass substrate 10 in a vertically incident manner to form a second sub-via on the second surface side of the glass substrate 10. The second sub-via is connected to the first sub-via to form a first connecting via 11.
[0118] Specifically, when the laser beam interacts with the glass substrate 10, the high energy of the laser photons ionizes the atoms in the glass substrate 10 and ejects them from the first surface of the glass substrate 10. As time increases, the hole gradually deepens until the first sub-via is formed. The glass substrate 10 is then flipped over, and the second sub-via is formed according to the same principle. Commonly used laser wavelengths include 532nm, 355nm, 266nm, 248nm, and 197nm. Laser pulse widths can be selected from 1-100fs, 1-100ps, and 1-100ns. Laser types can include continuous-wave lasers and pulsed lasers. Laser drilling methods can include, but are not limited to, the following two: In the first method, when the spot diameter is large, the relative position of the laser beam and the glass substrate 10 is fixed. High energy directly drills the 10 to a preset depth. The shape of the first sub-via formed in this case is an inverted frustum, with the diameter of the inverted frustum decreasing sequentially from top to bottom (from the second surface to the first surface). In the second method, when the spot diameter is small, the laser beam scans in a circle on the glass substrate 10. The focal point and focal depth of the spot continuously change. A spiral line is drawn from the lower surface (first surface) to the upper surface (second surface) of the glass substrate 10, and the spiral radius decreases from bottom to top. The glass substrate 10 is laser-cut into a frustum shape to form the first sub-via. The shape of this first blind hole 110 is the first sub-via. The second sub-via is formed in the same way as the first sub-via, so it will not be described again. It can be seen that the first connecting via 11 formed by the connection of the first and second sub-vias is hourglass-shaped.
[0119] (3) HF etching: During the laser drilling process, a stress zone is formed on the inner surface of the first connecting via 11 in an area of about 5-20 micrometers near the hole. In this area, the surface of the glass substrate 10 is uneven, exhibiting a molten state with many burrs, and contains a large number of microcracks and macrocracks, as well as residual stress. At this time, a 2%-20% HF etching solution is used to perform wet etching for a certain period of time at an appropriate temperature to etch away the glass in the stress zone, making the interior and surface of the first connecting via 11 and the area near the hole smooth and flat, free of microcracks and macrocracks, and completely etching away the stress zone.
[0120] S22. Through patterning process, the first connection electrode 213 and the first substructure 211 located in the first connection via 11 are formed.
[0121] In some examples, step S22 can specifically be the following steps:
[0122] (1) Seed layer growth: A first substrate 101 is provided, and the second surface of the glass substrate 10 is attached to the first substrate 101. A first metal material 200 is deposited on the second surface of the glass substrate 10 by magnetron sputtering. The glass substrate 10 is flipped over, and the first metal material 200 is deposited on the first surface by magnetron sputtering. At this time, the first metal material 200 is formed on the sidewall of the first connecting via 11, which serves as a seed layer. Figure 5b and 5c As shown.
[0123] In some examples, the first metal material 200 includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal material is approximately 100 nm to 500 nm, and may further be 50 nm to 35 μm. In the following description, copper is used as an example as the material of the first metal film layer 201.
[0124] In some examples, to increase the adhesion between the first metal material 200 and the first surface of the glass substrate 10, an auxiliary metal film layer can be formed on the first surface of the glass substrate 10 by means including but not limited to magnetron sputtering before forming the first metal material 200. The material of the auxiliary metal film layer includes, but is not limited to, at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is about 2nm-20nm.
[0125] (2) Electroplating: The glass substrate 10 is placed on the electroplating machine carrier, and an electric soldering pad is pressed on. It is then placed in a hole-filling electroplating tank (using a special hole-filling electrolyte). Current is applied, and the electroplating solution remains continuously and rapidly flowing on the first surface of the glass substrate 10. Cations in the electroplating solution gain electrons on the inner wall of the first connecting via 11, becoming atoms and depositing on the inner wall. Using a specially formulated special hole-filling electrolyte, high-speed deposition of metallic copper (deposition rate 0.5-3 μm / min) is achieved primarily within the first blind via 110. Since the first surface of the glass substrate 10 is a flat area, the deposition rate of metallic copper on these two surfaces is extremely low (0.005-0.05 μm / min). Over time, the metallic copper on the inner wall of the first connecting via gradually thickens, forming a first metal film layer 201. At this point, the first metal film layer 201 grows by more than 5 μm compared to the first metal material 200. The first metal film layer 201 then fills the first connecting via 11, as shown below. Figure 5d As shown.
[0126] (3) Formation of the first planarization layer 6: A first planarization layer 6 is formed on the surface of the glass substrate 10. At this time, the first planarization layer 6 fills the first connection via 11, such as... Figure 5eAs shown. The first planarization layer 6 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, and other resin-based materials. Alternatively, the organic insulating material may include an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc.
[0127] (4) Patterning of the first surface film layer: Exposure and development are performed on the first planarization layer 6 of the first surface, followed by etching. After etching, the resist is stripped, and the patterning of the first planarization layer 6 and the first metal film layer 201 on the first surface is completed. At this time, the first substructure 211 of the inductor coil located on the first surface is formed, as shown in the figure. Figure 5f As shown.
[0128] S23. A second planarization layer 8 is formed on the side of the first planarization layer 6 opposite to the glass substrate 10, and a second substrate 102 is attached to the side of the second planarization layer 8 opposite to the glass substrate 10. Figure 5g As shown.
[0129] The material of the second planarization layer 8 and the first planarization layer 6 can be the same, so it will not be repeated here.
[0130] S24. The glass substrate 10 is flipped over, and the first substrate 101 is peeled off onto the second surface of the glass substrate 10. A pattern including the second substructure 212 of the inductor coil and the first electrode 31 of the capacitor 3 is formed by a patterning process, such as... Figure 5h As shown.
[0131] In some examples, step S24 may specifically include forming a second metal film layer by means including but not limited to magnetron sputtering, applying adhesive, exposure, development, followed by wet etching, stripping the adhesive after etching, to form a pattern including a second substructure 212 of an inductor coil and a first plate 31 of a capacitor 3.
[0132] S25. A first interlayer dielectric layer 9 is formed on the side of the second substructure 212 of the inductor coil and the first electrode 31 of the capacitor 3 facing away from the glass substrate 10, and a pattern including the second electrode 32 of the capacitor 3 is formed on the side of the first interlayer dielectric layer 9 facing away from the glass substrate 10, as shown in the figure. Figure 5h As shown.
[0133] In some examples, the material of the first interlayer dielectric layer 9 is an inorganic insulating material. For example, the first interlayer dielectric layer 9 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a combination of several stacked films of SiNx inorganic insulating layers and SiO2 inorganic insulating layers. Of course, this first interlayer dielectric layer 9 also serves as the intermediate dielectric layer of the capacitor 3.
[0134] In some examples, the second electrode 32 of capacitor 3 can be formed by magnetron sputtering on the side of the first interlayer dielectric layer 9 away from the glass substrate 10, followed by resist coating, exposure, development, wet etching, and strip removal after etching to form a pattern including the second electrode 32 of capacitor 3.
[0135] S26. A second interlayer dielectric layer 12 is formed on the side of the second electrode plate 32 of capacitor 3 facing away from the glass substrate 10, and a second connection via 121 penetrating the first interlayer dielectric layer 9 and the second interlayer dielectric layer 12, and a third connection via 122 penetrating the second interlayer dielectric layer 12, as shown. Figure 5h As shown.
[0136] The material of the second interlayer dielectric layer 12 can be the same as that of the first interlayer dielectric layer 9, so it will not be described again here.
[0137] S27. On the side of the second interlayer dielectric layer 12 facing away from the glass substrate 10, a pattern including the second connecting electrode 13 and the connecting pad 4 is formed by a patterning process, such as... Figure 5h As shown.
[0138] In some examples, step S27 may include forming a fourth metal film layer by magnetron sputtering, applying resist, exposing, developing, followed by wet etching, and stripping the resist after etching to form a pattern including the second connecting electrode 13 and the connecting pad 4. The material of the fourth metal film layer can be the same as the material of the first metal film layer 201, and therefore will not be described further here.
[0139] S28. On the side of the layer containing the second connecting electrode 13 and the connecting pad 4 that is away from the glass substrate 10, a first buffer layer 14 and a third planarization layer 15 are deposited sequentially, and the second substrate 102 is peeled off. Figure 5i As shown.
[0140] In some examples, the material of the first buffer layer 14 can be the same as the material of the first protective layer 5, so it will not be described again here. The material of the third planarization layer 15 can be the same as the material of the first planarization layer 6, so it will not be described again here.
[0141] This completes the fabrication of the substrate for integrating passive devices.
[0142] In the third example, the fabrication method of the substrate integrating passive devices is largely the same as that in the second example, such as... Figure 6a and 6bAs shown, the only difference is in step S22. In this method, during electroplating, the first connecting electrode 213 formed fills the first connecting via 11, so there is no need to form the first planarization layer 6. The remaining steps are the same as the method in the second example, so they will not be repeated here.
[0143] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A method for fabricating a substrate integrating passive devices, comprising: A transparent dielectric layer is provided, and the transparent dielectric layer is processed to obtain the transparent dielectric layer having a first connection via. The transparent dielectric layer includes a first surface and a second surface disposed opposite to each other along the thickness direction; The process of processing the transparent dielectric layer to obtain the transparent dielectric layer having a first connection via includes: The first surface of the transparent dielectric layer is modified and etched to form a first blind hole; Passive devices are integrated on the transparent dielectric layer; the passive devices include at least an inductor; wherein, Integrating the passive device on the transparent dielectric layer includes: A first substructure is formed on the first surface of the transparent dielectric layer, a second substructure is formed on the second surface, and a first connection electrode is formed in the first connection via; the first substructure, the first connection electrode and the second substructure are connected to form an inductor coil structure. The step of forming a first substructure on the first surface of the transparent dielectric layer, forming a second substructure on the second surface, and forming a first connection electrode within the first connection via includes: Through patterning processes, a first connecting electrode and a first substructure are formed within the first blind hole; The transparent dielectric layer is thinned on the side opposite to the first substructure to expose the first connection electrode and form the first connection via. A pattern including the second substructure is formed on the second surface of the transparent dielectric layer.
2. The preparation method according to claim 1, wherein, The provision of a transparent dielectric layer and the etching of the transparent dielectric layer to form a first blind via includes: The transparent dielectric layer is modified by laser, and the first blind hole is formed by HF etching.
3. The preparation method according to claim 1, wherein, The process of forming a first connecting electrode and a first substructure within a first blind hole through a patterning process includes: A first metal material is deposited on the transparent dielectric layer in which the first blind hole is formed, and the first metal material is electroplated to form a first metal film layer; A first protective layer and a first planarization layer are sequentially formed on the side of the first metal film layer away from the transparent dielectric layer, and a pattern including the first connecting electrode and the first substructure is formed by a patterning process.
4. The preparation method according to claim 3, wherein, The first metal film layer covers the sidewall of the first connection via, and the method further includes the following steps before forming the first metal film layer: A first planarization layer is formed on the side of the first metal material opposite to the transparent dielectric layer, so that the first planarization layer fills the first connection via.
5. The preparation method according to any one of claims 1-4, wherein, After the first substructure is formed, the following is also included: A second protective layer and a second planarization layer are sequentially formed on the side of the first substructure opposite to the transparent dielectric layer.
6. The preparation method according to any one of claims 1-4, wherein, The passive device further includes a capacitor; while forming the second substructure on the second surface, a first electrode plate of the capacitor is also formed; the fabrication method further includes: A first interlayer dielectric layer is formed on the side of the first plate of the capacitor that is away from the transparent dielectric layer. The second electrode of the capacitor is formed on the side of the first interlayer dielectric layer opposite to the transparent dielectric layer; A second interlayer dielectric layer is formed on the side of the second plate of the capacitor away from the transparent dielectric layer, and a second connection via is formed through the first interlayer dielectric layer and the second interlayer dielectric layer, and a third connection via is formed through the second interlayer dielectric layer; A pattern including a second connection electrode and a connection pad is formed on the side of the second interlayer dielectric layer opposite to the transparent dielectric layer by a patterning process; the second connection electrode connects the second substructure and the second plate of the capacitor through the second connection via and the third connection via.
7. The preparation method according to claim 6, wherein, On the side of the layer containing the second connection electrode and the connection pad that is away from the transparent dielectric layer, a first buffer layer and a third planarization layer are deposited in sequence, and a fourth connection via is formed through the first buffer layer and the third planarization layer, and the fourth connection via exposes the connection pad.
8. The preparation method according to any one of claims 1-4, wherein, The transparent dielectric layer comprises a glass substrate.