Imaging device and electronic device

Abstract

To provide an imaging device capable of operating at a higher speed and lower power consumption for a column signal processing system including a successive approximation type analog-digital converter. The imaging device is provided with: a pixel array unit formed by arranging pixels including a photoelectric conversion element; a column amplifier unit that acquires a difference between a reset component and a signal component input from each pixel of the pixel array unit through a signal line, and outputs the difference as a pixel signal; a capacitance unit that holds the pixel signal input from the column amplifier unit; and a successive approximation type analog-digital converter unit that converts an analog signal input from the capacitance unit into a digital signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging device and an electronic apparatus. BACKGROUND

[0002] An imaging device is equipped with an analog-digital converter that converts an analog signal (pixel signal) output from a pixel into a digital signal, and uses a successive approximation register (SAR) type analog-digital converter as the analog-digital converter (see, for example, Patent Literature 1).

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2019-092143 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] A successive approximation register type analog-digital converter is superior to a so-called single slope analog-digital converter in that it can operate at a higher speed and with lower power consumption. It is desirable for a column signal processing system including such a successive approximation register type analog-digital converter to operate at a higher speed and with lower power consumption.

[0008] An object of the present disclosure is to provide an imaging device in which a column signal processing system including a successive approximation register type analog-digital converter capable of operating at a higher speed and with lower power consumption, and an electronic apparatus including the imaging device.

[0009] SOLUTION TO PROBLEM

[0010] An imaging device of the present disclosure for achieving the above object includes:

[0011] a pixel array unit on which a pixel including a photoelectric conversion element is arranged;

[0012] a column amplifier unit that acquires a difference between a reset component and a signal component input from each of the pixels of the pixel array unit through a signal line, and outputs the difference as a pixel signal;

[0013] a capacitance unit that holds the pixel signal input from the column amplifier unit; and

[0014] a successive approximation register type analog-digital conversion unit that converts an analog signal input from the capacitance unit into a digital signal.

[0015] Further, an electronic apparatus of the present disclosure for achieving the above object includes the imaging device having the above configuration. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied.

[0017] Figure 2 is a circuit diagram showing an example of a circuit configuration of a pixel.

[0018] Figure 3 is a plan view schematically showing an outline of a planar semiconductor chip structure of a CMOS image sensor.

[0019] Figure 4 is an exploded perspective view schematically showing an outline of a stacked semiconductor chip structure of a CMOS image sensor.

[0020] Figure 5 is a block diagram showing an outline of a configuration of a CMOS image sensor as an example of an imaging device according to a first embodiment of the present disclosure.

[0021] Figure 6 is a circuit diagram showing an outline of a configuration of a column signal processing system according to the first embodiment.

[0022] Figure 7 is a timing chart for explaining a circuit operation of the column signal processing system according to the first embodiment.

[0023] Figure 8 is a circuit diagram showing an outline of a configuration of a column signal processing system according to a second embodiment.

[0024] Figure 9 is a circuit diagram showing an outline of a configuration of a column signal processing system according to a third embodiment.

[0025] Figure 10 is a timing chart for explaining a circuit operation of the column signal processing system according to the third embodiment.

[0026] Figure 11 is a circuit diagram showing an outline of a configuration of a column signal processing system according to a fourth embodiment.

[0027] Figure 12 is a graph for explaining a level diagram.

[0028] Figure 13 is a circuit diagram showing an example of a configuration of a current-reuse column amplifier.

[0029] Figure 14 is a detailed circuit diagram of a successive approximation register type analog-digital converter.

[0030] Figure 15is a block diagram showing an example of a system configuration of an indirect TOF range image sensor according to a second embodiment of the present disclosure.

[0031] Figure 16 is a circuit diagram showing an example of a circuit configuration of a pixel in an indirect TOF range image sensor according to the second embodiment.

[0032] Figure 17 is a diagram showing an application example according to the technology of the present disclosure.

[0033] Figure 18 is a block diagram showing an outline of a configuration example of an imaging system that is an example of an electronic apparatus of the present disclosure.

[0034] Figure 19 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0035] Figure 20 is a diagram showing an example of a mounting position of an imaging section in a moving body control system. DETAILED DESCRIPTION

[0036] Hereinafter, a form for implementing the technology according to the present disclosure (hereinafter referred to as "embodiment") will be explained in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiment, and each numerical value and the like in the embodiment is an example. In the following explanation, the same reference signs will be used for the same elements or elements having the same function, and redundant explanation will be omitted. Note that the explanation will be made in the following order.

[0037] 1. General Explanation of Imaging Apparatus and Electronic Apparatus of the Present Disclosure

[0038] 2. Imaging Apparatus to Which the Technology According to the Present Disclosure is Applied

[0039] 2-1. Configuration Example of CMOS Image Sensor

[0040] 2-2. Example of Circuit Configuration of Pixel

[0041] 2-3. Semiconductor Chip Structure

[0042] 2-3-1. Planar Semiconductor Chip Structure

[0043] 2-3-2. Laminated Semiconductor Chip Structure

[0044] 2-4. Single Slope Analog-to-Digital Converter

[0045] 3. First Embodiment of the Present Disclosure (Example of CMOS Image Sensor)

[0046] 3-1. First embodiment (example of intermittent operation in which the successive approximation register type analog-digital converter performs the conversion process only during the P phase and stands by during the D phase)

[0047] 3-1-1. Configuration example of column amplifier

[0048] 3-1-2. Configuration example of capacitor multiplexer

[0049] 3-1-3. Configuration example of successive approximation register type analog-digital converter

[0050] 3-1-4. Circuit operation of column signal processing system

[0051] 3-2. Second embodiment (modification of the first embodiment: example of non-intermittent operation in which the successive approximation register type analog-digital converter performs the conversion process not only during the P phase but also during the D phase)

[0052] 3-3. Third embodiment (modification of the second embodiment: example in which three capacitor elements are equally used for the potential VSL of the signal line of the two systems)

[0053] 3-3-1. Configuration example of column signal processing system

[0054] 3-3-2. Circuit operation of column signal processing system

[0055] 3-4. Fourth embodiment (example of configuration in which the capacitor multiplexer and the subsequent unit have a differential circuit)

[0056] 3-4-1. Power supply voltage and transistor used

[0057] 3-4-2. Level diagram

[0058] 3-4-3. Configuration example of column amplifier

[0059] 3-4-4. Configuration example of successive approximation register type analog-digital converter

[0060] 4. Second embodiment of the present disclosure (example of indirect TOF distance image sensor)

[0061] 4-1. Example of system configuration

[0062] 4-2. Example of circuit configuration of pixel

[0063] 5. Modification

[0064] 6. Application example

[0065] 7. Application example of technology according to the present disclosure

[0066] 7-1. Electronic device of the present disclosure (example of imaging device)

[0067] 7-2. Examples applied to mobile bodies

[0068] 8. Configuration that the present disclosure can adopt

[0069] <General description of imaging device and electronic equipment of the present disclosure>

[0070] The imaging device and electronic equipment of the present disclosure can have a configuration in which the column amplifier unit includes an amplifier to which the potential of the signal line is input to a non-inverting input terminal, a first switch having one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier, a second switch having one end connected to the output terminal of the amplifier, a first capacitance element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier, a second capacitance element connected between the other end of the first capacitance element, the inverting input terminal of the amplifier, and a reference potential node, and a third switch having one end connected to the other end of the second switch and one end of the first capacitance element, the other end of the third switch being applied with a reference voltage.

[0071] The imaging device and electronic equipment of the present disclosure including the above-described preferred configuration can have a configuration in which, in the column amplifier unit, when a reset component is input, the first switch is set to a closed state and the reset component is applied to the first capacitance element and the second capacitance element, the third switch is set to a closed state to acquire a local reference voltage, then the first switch and the third switch are set to an open state, the second switch is set to a closed state, and a non-inverting amplifier circuit is constituted by the first capacitance element, the second capacitance element, and the amplifier, and when a signal component is input, feedback is applied so that the voltage at the common connection node between the first capacitance element and the second capacitance element becomes the same as the voltage of the signal component.

[0072] Further, the imaging device and electronic equipment of the present disclosure including the above-described preferred configuration can have a configuration in which, for one successive approximation register type analog-digital converter of the successive approximation register type analog-digital conversion unit, the potentials of a plurality of signal lines are each multiplexed and processed by a plurality of column amplifiers and capacitance units corresponding to the plurality of signal lines. Further, the successive approximation register type analog-digital converter can be configured to perform conversion processing only when a reset component is input and stand by when a signal component is input, or perform conversion processing not only when a reset component is input but also when a signal component is input.

[0073] Further, in the imaging device and electronic equipment of the present disclosure including the above-described preferred configuration, the potentials of a plurality of signal lines can be divided into the potentials of signal lines of two systems, and the capacitance unit can include three capacitance elements. Also, the three capacitance elements of the capacitance unit are each used for the potentials of signal lines of two systems.

[0074] Further, in the imaging device and the electronic apparatus of the present disclosure including the above-described preferred configuration, in a column signal processing system including a column amplifier unit, a capacitance unit, and a successive approximation register type analog-digital conversion unit, the capacitance unit and a subsequent stage portion can have a configuration of a differential circuit. Further, the column amplifiers of the column amplifier unit can each include a current reuse column amplifier that performs voltage amplification by using a bias current of each signal line.

[0075] Further, in the imaging device and the electronic apparatus of the present disclosure including the above-described preferred configuration, the capacitance unit can include a capacitance multiplexer. Further, the capacitance unit can hold a pixel signal by sampling using a switched capacitance.

[0076] [Imaging device to which the technology of the present disclosure is applied]

[0077] First, the basic configuration of an imaging device to which the technology of the present disclosure is applied will be described. Here, as an example of an imaging device, a complementary metal oxide semiconductor (CMOS) image sensor, which is one type of X-Y addressing imaging device, will be described. The CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

[0078] [Configuration example of CMOS image sensor]

[0079] Figure 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor, which is an example of an imaging device to which the technology of the present disclosure is applied.

[0080] The CMOS image sensor 10 of this example includes a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11. The pixel array unit 11 is formed by arranging pixels (pixel circuits) 20 including photoelectric conversion elements in a two-dimensional (i.e., in a matrix form) in a row direction and a column direction. Here, the row direction refers to the arrangement direction of the pixels 20 in a pixel row, and the column direction refers to the arrangement direction of the pixels 20 in a pixel column. The pixels 20 perform photoelectric conversion to generate and accumulate photocharges corresponding to the amount of received light.

[0081] The peripheral circuit unit of the pixel array unit 11 includes, for example, a row selection unit 12, a constant current source unit 13, a column amplifier unit 14, an analog-digital conversion unit 15, a horizontal transfer scanning unit 16, a signal processing unit 17, a timing control unit 18, and the like.

[0082] In the pixel array unit 11, pixel control lines 31 (311 to 31 m ) are wired in the row direction with respect to the pixel array in a matrix form for each pixel row. Further, signal lines 32 (321 to 32 nWiring is performed along the column direction for each pixel column. When a signal is read from pixel 20, pixel control line 31 transmits the drive signal used to execute the drive. Figure 1 In the diagram, pixel control line 31 is shown as a single wiring, but is not limited to a single one. One end of pixel control line 31 is connected to the output terminal corresponding to each row of row selection unit 12.

[0083] The components of the peripheral circuit unit of the pixel array unit 11 will now be described, namely the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-to-digital conversion unit 15, the horizontal transmission scanning unit 16, the signal processing unit 17, and the timing control unit 18.

[0084] The row selection unit 12 includes a shift register, an address decoder, etc., and controls the scanning and addressing of pixel rows when selecting each pixel 20 of the pixel array unit 11. Although the specific structure of the row selection unit 12 is not shown in the figure, the row selection unit 12 typically includes two scanning systems, namely a readout scanning system and a clear scanning system.

[0085] To read the pixel signal from pixel 20, the readout scanning system sequentially selects and scans pixels 20 of the pixel array unit 11 row by row. The pixel signal read from pixel 20 is an analog signal. The clearing scanning system performs a clearing scan on the readout rows to be read out by the readout scanning system before the readout scan, corresponding to the shutter speed.

[0086] By performing a clear scan using the clear scan system, unwanted charges are removed from the photoelectric conversion elements of pixels 20 in the readout line, thus resetting the photoelectric conversion elements. Then, by clearing (resetting) the unwanted charges using the clear scan system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of expelling the photoelectric charge from the photoelectric conversion elements and restarting exposure (starting to accumulate photoelectric charge).

[0087] The constant current source unit 13 includes multiple load current sources I (see...) Figure 2 For example, each load current source I includes a MOS transistor and is connected to each signal line 321 to 32 of each pixel column. n And the constant current source unit 13 is connected to each signal line 321 to 32 n Provide bias current to each pixel of the pixel row selectively scanned by the row selection unit 12.

[0088] The column amplifier unit 14 includes signal lines 321 to 32 corresponding to each pixel column. n A set of column amplifiers is configured. Furthermore, each column amplifier in column amplifier unit 14 amplifies and reads the signal from each pixel 20 of pixel array unit 11 and transmits it through signal lines 321 to 322. nThe pixel signal supplied is amplified, and the amplified pixel signal is supplied to an analog-digital conversion unit 15.

[0089] The analog-digital conversion unit 15 is a column-parallel analog-digital conversion unit including a plurality of analog-digital converters arranged corresponding to the pixel column arrangement of the pixel array unit 11 (for example, for each pixel column arrangement). The analog-digital conversion unit 15 converts the analog pixel signal supplied through the signal line 321 to 32 n The analog pixel signal output and amplified by the column amplifier unit 14 is converted into a digital pixel signal.

[0090] The horizontal transfer scanning unit 16 includes a shift register, an address decoder, and the like, and controls scanning of the pixel column and addressing of the pixel column at the time of reading out the signal of each pixel 20 of the pixel array unit 11. Under the control of the horizontal transfer scanning unit 16, the pixel signal converted into a digital signal by the analog-digital conversion unit 15 is read out to the horizontal transfer line L in units of the pixel column.

[0091] The signal processing unit 17 performs predetermined signal processing on the digital pixel signal supplied through the horizontal transfer line L to generate two-dimensional image data. For example, the signal processing unit 17 performs digital signal processing such as correction of vertical line defects or point defects, parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing unit 17 outputs the generated image data to a later-stage device as an output signal of the CMOS image sensor 10.

[0092] The timing control unit 18 generates various timing signals, clock signals, control signals, and the like, and performs drive control of the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-digital conversion unit 15, the horizontal transfer scanning unit 16, the signal processing unit 17, and the like, based on the generated signals.

[0093] [Example of circuit configuration of pixel]

[0094] Figure 2 is a circuit diagram showing an example of the circuit configuration of the pixel (pixel circuit) 20. The pixel 20 includes, for example, a photodiode 21 as a photoelectric conversion element. In addition to the photodiode 21, the pixel 20 includes a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0095] Examples of the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 include, for example, N-channel MOS field effect transistors (FETs). However, the combination of the conductive types of the four transistors 22 to 25 shown here is merely an example, and the combination is not necessarily essential.

[0096] For pixel 20, multiple pixel control lines are routed together to each pixel 20 in the same pixel row as the aforementioned pixel control line 31. The multiple pixel control lines are connected to the output terminals of each pixel row corresponding to the row selection unit 12, unit by unit. The row selection unit 12 appropriately outputs the transmission signal TRG, the reset signal RST, and the selection signal SEL to the multiple pixel control lines.

[0097] The photodiode 21 has an anode electrode connected to a low-potential power supply (e.g., ground), which converts received light photoelectrically into photocharge (here, photoelectrons) corresponding to the amount of light, and accumulates the photocharge. The cathode electrode of the photodiode 21 is electrically connected to the gate of the amplifying transistor 24 via a transfer transistor 22. Here, the region electrically connected to the gate of the amplifying transistor 24 is the floating diffusion section (floating diffusion region / impurity diffusion region) FD. The floating diffusion section FD is a charge-to-voltage conversion unit that converts charge into voltage.

[0098] Activate high level (e.g., V) DD A transmission signal TRG (level) is provided from the row selection unit 12 to the gate of the transmission transistor 22. The transmission transistor 22 is turned on in response to the transmission signal TRG and transmits the photocharge converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffuser FD.

[0099] Reset transistor 23 is connected to the high-potential side power supply voltage V. DD The node between the floating diffuser FD and the node. A high-level reset signal RST is provided from the row select unit 12 to the gate of the reset transistor 23. The reset transistor 23 turns on in response to the reset signal RST and discharges the charge of the floating diffuser FD to the voltage V. DD The node is used to reset the floating diffuser FD.

[0100] The gate of the amplifying transistor 24 is connected to the floating diffuser FD, and the drain is connected to the high-potential side power supply voltage V. DD The amplifying transistor 24 serves as the input unit for a source follower that reads the signal obtained through photoelectric conversion in the photodiode 21. Specifically, the source of the amplifying transistor 24 is connected to the signal line 32 via the select transistor 25. Then, the amplifying transistor 24 and the load current source I connected to one end of the signal line 32 constitute a source follower that converts the voltage of the floating diffuser FD into the potential of the signal line 32.

[0101] The drain of the selection transistor 25 is connected to the source of the amplification transistor 24, and the source is connected to the signal line 32. The selection signal SEL of the active high level is supplied from the row selection unit 12 to the gate of the selection transistor 25. The selection transistor 25 is turned on in response to the selection signal SEL, and transmits the signal output from the amplification transistor 24 to the signal line 32 in the case where the pixel 20 is in the selected state.

[0102] Note that, in the above-described circuit example, as the circuit configuration of the pixel 20, a 4Tr configuration including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 (i.e., including four transistors (Tr)) has been described as an example, but this circuit configuration is not essential. For example, a 3Tr configuration omitting the selection transistor 25 can be employed as occasion demands, in which the amplification transistor 24 has the function of the selection transistor 25, or a circuit configuration of 5Tr or more in which the number of transistors is increased can be employed.

[0103] [Semiconductor chip structure]

[0104] As the semiconductor chip structure of the CMOS image sensor 10 having the above-described configuration, a planar semiconductor chip structure and a stacked semiconductor chip structure can be exemplified. In any of the CMOS image sensor 10 having the planar semiconductor chip structure and the stacked semiconductor chip structure, when the substrate surface on which the wiring layer side is arranged is a front surface (front surface), the pixel 20 can have a back surface illumination type pixel structure that captures light emitted from the back surface side which is the opposite side of the front surface, or can have a front surface illumination type pixel structure that captures light emitted from the front surface side. The planar semiconductor chip structure and the stacked semiconductor chip structure will be described below.

[0105] (Planar semiconductor chip structure)

[0106] Figure 3 is a plan view schematically showing an outline of the planar semiconductor chip structure of the CMOS image sensor 10. As shown in Figure 3 the planar semiconductor chip structure has a structure in which a circuit portion around the pixel array unit 11 is formed on the same semiconductor chip (semiconductor substrate) 41 as the pixel array unit 11 in which the pixels 20 are arranged in a matrix form. Specifically, the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-digital conversion unit 15, the horizontal transfer scan unit 16, the signal processing unit 17, the timing control unit 18, and the like are formed on the same semiconductor chip 41 as the pixel array unit 11.

[0107] (Stacked semiconductor chip structure)

[0108] Figure 4is an exploded perspective view schematically showing an outline of a stacked semiconductor chip structure of the CMOS image sensor 10. As shown in Figure 4 the stacked semiconductor chip structure is a structure in which at least two semiconductor chips (semiconductor substrates) of the first layer semiconductor chip 42 and the second layer semiconductor chip 43 are stacked. In this stacked structure, the pixel array unit 11 is formed on the first layer semiconductor chip 42. Further, circuit portions such as the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-digital conversion unit 15, the horizontal transfer scanning unit 16, the signal processing unit 17, and the timing control unit 18 are formed on the second layer semiconductor chip 43. Also, the first layer semiconductor chip 42 and the second layer semiconductor chip 43 are electrically connected by connection portions (VIA) 44A and 44B such as Cu-Cu connection.

[0109] In the CMOS image sensor 10 having such a stacked structure, the size (area) of the first layer semiconductor chip 42 only needs to be enough to form the pixel array unit 11, and thus, the size (area) of the first layer semiconductor chip 42 and the size of the entire chip can be reduced. Further, since a process suitable for manufacturing the pixel 20 can be applied to the first layer semiconductor chip 42 and a process suitable for manufacturing the circuit portions can be applied to the second layer semiconductor chip 43, there is also an advantage that the processes can be optimized in manufacturing the CMOS image sensor 10. In particular, an advanced process can be applied in manufacturing the circuit portions.

[0110] Note that, here, a stacked structure of a two-layer structure in which the first layer semiconductor chip 42 and the second layer semiconductor chip 43 are stacked is exemplified, but the stacked structure is not limited to the two-layer structure, and can be a three-layer or more structure. Also, in the three-layer or more stacked structure, the circuit portions such as the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-digital conversion unit 15, the horizontal transfer scanning unit 16, the signal processing circuit unit 17, and the timing control unit 18 can be formed on the semiconductor chips of the second layer and the subsequent layers in a scattered manner.

[0111] [Single slope analog-digital converter]

[0112] In the CMOS image sensor 10 having the above-described configuration, for example, a single slope analog-digital converter is generally used as the analog-digital converter in the analog-digital conversion unit 15. Here, the single slope analog-digital converter will be described.

[0113] In a single slope analog-digital converter, a ramp waveform (ramp) signal that linearly changes at a certain slope is used as a reference signal. The single slope analog-digital converter compares an analog pixel signal read out from the pixel 20 with the reference signal of the ramp, amplifies and clips a difference between the pixel signal and the reference signal to modulate the signal into a phase signal, and then samples to convert the signal into a digital signal. This single slope analog-digital converter has the following problems.

[0114] • Problem 1

[0115] In the process of modulating the phase signal, a shift occurs due to a delay. Therefore, digital correlated double sampling (CDS) for removing fixed pattern noise of the pixel 20 is essential, and an additional time for two times of analog-digital conversion and auto-zeroing is required.

[0116] • Problem 2

[0117] When the pixel signal and the reference signal of the ramp cross, a through current or a kickback occurs. In addition, a cross time depends on a level of the pixel signal, and disturbs analog-digital converters of other pixel columns.

[0118] • Problem 3

[0119] Since the amplification transistor 24 of the pixel 20 is used to hold a voltage during analog-digital conversion, a conversion time limits a readout speed of the pixel signal.

[0120] Regarding Problem 1, in the single slope analog-digital converter, auto-zeroing of an input amplifier (elimination of a shift due to input and output short circuits) is performed to prevent a shift. As a result, a DC shift can be eliminated. However, since the reference signal of the ramp varies with time, an AC shift caused by a delay cannot be eliminated. Although a delay can be reduced by widening a band, output phase noise increases.

[0121] Problem 2 is a mechanism of an interference phenomenon (streak) from a bright portion to a dark portion. In the single slope analog-digital converter, when a plurality of pixel columns have the same brightness, switching occurs at the same time, and thus an influence of interference increases.

[0122] Problem 3 is a problem caused by not sampling a potential of the signal line 32. In the amplification transistor 24 of the pixel 20, a large power is consumed in order to drive the signal line 32 having a large load capacity. Therefore, it is not desirable to use only the amplification transistor 24 to hold a voltage during analog-digital conversion.

[0123] <First Embodiment of the Present Disclosure>

[0124] In the imaging device (CMOS image sensor as an example) according to the first embodiment of the present disclosure, a successive approximation register type (SAR) type analog-digital converter is used as each analog-digital converter of the analog-digital conversion unit 15. The successive approximation register type analog-digital converter can operate at a higher speed and with lower power consumption than the single slope analog-digital converter having the various problems described above. In the present embodiment, the column signal processing system including the successive approximation register type analog-digital converter can operate at a higher speed and with lower power consumption.

[0125] Figure 5 is a block diagram showing a configuration outline of a CMOS image sensor that is an example of the imaging device according to the first embodiment of the present disclosure.

[0126] In the CMOS image sensor 10 according to the present embodiment, the column amplifier unit 14 performs a process (CDS process) of acquiring a difference between a signal component (so-called D-phase) input from each pixel 20 of the pixel array unit 11 through the signal line 32 and a reset component (so-called P-phase), and outputs the difference as a pixel signal. A capacitance unit 19 is provided at a subsequent stage of the column amplifier unit 14.

[0127] The capacitance unit 19 holds the pixel signal input from the column amplifier unit 14, for example, by sampling with a switched capacitor. A successive approximation register type analog-digital conversion unit 15A is provided at a subsequent stage of the capacitance unit 19. The successive approximation register type analog-digital conversion unit 15A includes a plurality of successive approximation register type (SAR) analog-digital converters that can operate at a higher speed and with lower power consumption than the single slope analog-digital converter, and converts an analog pixel signal input from the capacitance unit 19 into a digital pixel signal.

[0128] In the CMOS image sensor 10 according to the present embodiment, each successive approximation register type analog-digital converter of the successive approximation register type analog-digital conversion unit 15A performs a binary search, and thus is more efficient in principle than the single slope analog-digital converter that performs the clearing alone when viewed separately. Further, the CDS process that was conventionally performed twice in the analog-digital converter by the column amplifier unit 14 of the analog circuit system can be halved in the number of times of analog-digital conversion. Further, by introducing a switched capacitor to sample, the potential VSL of the signal line does not have to wait for the analog-digital conversion, and sampling is performed at all times regardless of the potential VSL of the signal line 32. Therefore, the influence of the disturbance caused by the conversion is also small.

[0129] Hereinafter, a specific example of the column signal processing system in the CMOS image sensor 10 according to the first embodiment will be described, specifically, the column signal processing system including the column amplifier unit 14, the capacitance unit 19, and the analog-digital conversion unit 15.

[0130] [First Embodiment]

[0131] The first embodiment is an example of intermittent operation in which the successive approximation register type analog-digital converter performs the conversion process only during the P phase of the input reset component, and stands by during the D phase of the input signal component. Figure 6 is a circuit diagram showing a configuration outline of the column signal processing system according to the first embodiment. The column amplifier unit 14 includes the same number of column amplifiers 140 as the number of pixel columns provided, and the capacitance unit 19 also includes the same number of capacitance multiplexers 190 as the number of pixel columns.

[0132] Here, as an example, it is explained that, for one successive approximation register type analog-digital converter 150 of the successive approximation register type analog-digital converter unit 15A, the potentials VSL0 to VSL7 of the plurality of signal lines 32 (for example, eight signal lines 32) are respectively processed by multiplexing the eight column amplifiers 140 and the eight capacitance multiplexers 190 corresponding to the eight signal lines 32.

[0133] (Configuration Example of Column Amplifier)

[0134] The column amplifier 140 includes an amplifier 141, a first switch 142, a second switch 143, a third switch 144, a first capacitance element 145, and a second capacitance element 146. The first capacitance element 145 (hereinafter simply referred to as "capacitance element 145") has a capacitance value C F , and the second capacitance element 146 (hereinafter simply referred to as "capacitance element 146") has a capacitance value C S .

[0135] The amplifier 141 uses the potentials VSL (VSL0 to VSL7) of the signal lines 32 as the input of the non-inverting (+) input terminal. One end of the first switch 142 (hereinafter simply referred to as "switch 142") is connected to the output terminal of the amplifier 141, and the other end is connected to the inverting (-) input terminal of the amplifier 141, and performs on / off operation according to the polarity (high level / low level) of the switch control signal S p .

[0136] One end of the second switch 143 (hereinafter simply referred to as "switch 143") is connected to the output terminal of the amplifier 141. One end of the capacitance element 145 is connected to the other end of the switch 143, and the other end is connected to the other end of the switch 142 and the inverting input terminal of the amplifier 141. The capacitance element 146 is connected between the node of the other end of the capacitance element 145, the output terminal of the amplifier 141, and a reference potential (for example, ground). The switch 143 performs on / off operation according to the polarity of the switch control signal S D .

[0137] That is, the switch 143, the capacitance element 145, and the capacitance element 146 are connected in series in this order between the output terminal of the amplifier 141 and a node (for example, ground) of a reference potential. Further, the common connection node N1 between the capacitance element 145 and the capacitance element 146 and the other end of the switch 142 are electrically connected to each other.

[0138] One end of a third switch 144 (hereinafter referred to as “switch 144”) is connected to a common connection node N2 between the switch 143 and the capacitance element 145, and performs on / off operation in accordance with the polarity of a switch control signal S VR . A local reference voltage VR defining a zero voltage of the output of the column amplifier 140 is applied to the other end of the switch 144. That is, the switch 144 selectively applies the local reference voltage VR to the common connection node N2 between the switch 143 and the capacitance element 145.

[0139] (Configuration example of capacitance multiplexer)

[0140] The capacitance multiplexer 190 constituting the capacitance unit 19 includes four switches 191 to 194 and one capacitance element 195, and is configured to perform sampling using a switched capacitor. The capacitance element 195 has a capacitance value C IN .

[0141] One end of the switch 191 is connected to the output terminal of the column amplifier 140, that is, the output terminal of the amplifier 141, and performs on / off operation in accordance with the polarity of a switch control signal S IN . One end of the switch 192 is connected to the other end of the switch 191, and performs on / off operation in accordance with the polarity of a switch control signal S VMI0 . A specific reference voltage VX is applied to the other end of the switch 192. The local reference voltage VR can be used as the specific reference voltage VX.

[0142] One end of the capacitance element 195 is connected to the other end of the switch 191. One end of the switch 193 is connected to the other end of the capacitance element 195, and performs on / off operation in accordance with the polarity of a switch control signal S VM . The other end of the switch 193 is applied with an intermediate voltage VM used when resetting the capacitor array unit (C DAC ) 155 of the successive approximation register type analog-digital converter 150.

[0143] One end of the switch 194 is connected to the other end of the capacitance element 195 and the one end of the switch 193, and performs on / off operation in accordance with the polarity of a switch control signal S SUM0The other end of the switch 194 is commonly connected between the eight capacitor multiplexers 190 corresponding to the potentials VSL0 to VSL7 of the signal lines 32, and serves as an output terminal of the capacitor multiplexers 190.

[0144] (An example of the configuration of a successive approximation register type analog-digital converter)

[0145] The successive approximation register type analog-digital converter 150 includes a preamplifier 151, a comparator 152, a SAR logic unit 153, a digital-analog converter (DAC) 154, and a capacitor array unit (C DAC ) 155.

[0146] The preamplifier 151 includes an amplifier 1511 and a switch 1512. The amplifier 1511 uses an analog voltage supplied from the capacitor multiplexers 190 as an input to an inverting (-) input terminal, and uses an output common mode reference voltage V CM as an input to a non-inverting (+) input terminal. The switch 1512 is an auto-zero (offset cancellation due to input and output shorting) switch connected between the inverting (-) input terminal and the output terminal of the preamplifier 151, and performs an on / off operation according to the polarity of a switch control signal S AZ .

[0147] The comparator 152 compares the magnitude of the analog voltage supplied through the preamplifier 151 with the magnitude of a comparison reference voltage in synchronization with a comparator clock CKI, and supplies a comparison result to the SAR logic unit 153.

[0148] The SAR logic unit 153 includes, for example, an N-bit successive approximation register, stores comparison results of respective bits of the comparator 152 in synchronization with a clock CK, and outputs the comparison results as an N-bit digital value D OUT after analog-digital conversion.

[0149] The digital-analog converter 154 and the capacitor array unit 155 constitute an N-bit capacitive digital-analog converter. Also, in this capacitive digital-analog converter, the N-bit digital value D OUT output from the SAR logic unit 153 is converted into an analog voltage and the voltage is applied to the inverting (-) input terminal of the amplifier 1511 as an input.

[0150] (Circuit operation of the column signal processing system)

[0151] Next, the circuit operation of the column signal processing system according to the first embodiment including the column amplifier 140, the capacitor multiplexers 190, and the successive approximation register type analog-digital converter 150 configured as described above is explained with reference to the timing chart in Figure 7 .

[0152] Figure 7 The timing diagram shows the potential VSL of signal line 32 and the switch control signal S. P S VR Switch control signal S D S IN S VM Switch control signal S VMI0 To S VMI7 and S SUM0 To S SUM7 Clock CK, switch control signal S AZ Timing relationship between comparator clock CKI.

[0153] First, the potentials VSL0 to VSL7 of the eight signal lines 32 are input to the corresponding dedicated column amplifiers 140. While the potentials VSL0 to VSL7 of the eight signal lines 32 are in the reset component (P-phase voltage) state, the switch control signal S... P and switch control signal S VR When the voltage is high, switches 142 and 144 are in the on (closed) state. As a result, capacitors 145 and 146 charge the reset component (P-phase voltage). At this time, the reset component (P-phase voltage) varies greatly (low accuracy) depending on pixel 20 in the voltage at the common connection node N2 between switch 143 and capacitor 145, but the local reference voltage VR generated on the side of column amplifier 140 varies very little (high accuracy).

[0154] Next, in the switch control signal S P and switch control signal S VR When the signal is low, switches 142 and 144 are in the off (open) state. Simultaneously, when the switch control signal SD is high, switch 143 is in the on (closed) state. At this time, capacitors 145 and 146 and amplifier 141 constitute a non-inverting amplifier circuit, and the output voltage V of amplifier 140... out The voltage is approximately the same as the local reference voltage VR.

[0155] Subsequently, when each change (more specifically, decrease) in the potentials VSL0 to VSL7 of the eight signal lines 32 corresponds to a signal component (D-phase voltage) as a brightness component, feedback is applied so that the voltage at the common connection node N1 between capacitor elements 145 and 146 becomes the same as the signal component (D-phase voltage). Through this series of operations, CDS processing is performed to obtain the difference between the reset component (P-phase voltage) and the signal component (D-phase voltage), and the output voltage V of the column amplifier 140 is... out The decrease was amplified to (C) F +C S) / C F the voltage of the signal line 32.

[0156] The signal component amplified by the column amplifier 140 is input to a capacitive multiplexer 190 including the same number of capacitive elements 195 as the column amplifier 140. In the capacitive multiplexer 190, the switch control signals S IN and the switch control signals S VM are high during the D phase. In response to this, the switches 191 and 193 enter the on state, and thus the intermediate voltage VM is applied to the capacitive elements 195. Then, the switch control signals S IN and the switch control signals S VM are low, and in response to this, the switches 191 and 193 enter the off state. Thus, the charge is held in the capacitive elements 195 having the capacitance value C IN .

[0157] Next, during the P phase, the switch control signals S VMIx (x = 0 to 7) and the switch control signals S SUMx (x = 0 to 7) become high in order, and the switches 192 and 194 are set to the on state. Thus, the charge held in the capacitive elements 191 is transferred to the successive approximation register type analog-digital converter 150. The charge transfer is performed by dividing the P phase time by 8. Since the D phase is used for sampling, the charge transfer can only be performed in the P phase.

[0158] When the capacitive elements 191 are connected to the input of the successive approximation register type analog-digital converter 150 through the switches 194, the comparator clock CKI is input to the comparator 152 to start the comparison. The comparison result of the comparator 152 is fed back to the digital-analog converter 154 via the SAR logic unit 153, and is bisected so that the input of the preamplifier 151 becomes 0 V. Finally, almost all of the charge accumulated in the capacitive elements 195 of the capacitive multiplexer 190 is transferred to the capacitor array unit (C DAC ) 155, and the input of the digital-analog converter 154 at that time is obtained as the output code.

[0159] Note that it is necessary to set the switch 1512 of the preamplifier 151 to the on (closed) state by setting the switch control signals S AZ to high before the next connection of the capacitive elements 195, and to reset the charge of the capacitor array unit (C DAC ) 155.

[0160] As described above, in the circuit operation of the column signal processing system according to the first embodiment, the successive approximation register type analog-digital converter 150 performs intermittent operation that operates only during the P phase and stands by without doing anything during the D phase. In the standby state, the circuit current is stopped to prevent power consumption, but the portion that cannot respond at high speed cannot be stopped, causing waste. In addition, since the power supply current greatly changes between the P phase and the D phase, it takes time to stabilize the power supply voltage immediately after the resumption.

[0161] In addition, in the configuration of the column signal processing system according to the first embodiment, in the capacitive multiplexer 190, the capacitive element 195 needs to sample the output of the column amplifier 140 in the D phase, and thus cannot continue to hold the charge.

[0162] [Second Embodiment]

[0163] The second embodiment is a modification of the first embodiment, and is an example of non-intermittent operation in which the successive approximation register type analog-digital converter performs conversion processing not only during the P phase in which the reset component is input but also during the D phase in which the signal component is input. Figure 8 is a circuit diagram showing an outline of the configuration of the column signal processing system according to the second embodiment.

[0164] Assuming that the P phase period and the D phase period are approximately the same and that analog-digital conversion is performed on half in each phase, four times of analog-digital conversion are performed in the case where the potentials VSL0 to VSL7 of the eight signal lines 32 are all multiplexed and processed.

[0165] In the column signal processing system according to the second embodiment, as shown in Figure 8 , the potentials VSL0 to VSL7 of the eight signal lines 32 are each divided into the potentials VSL0 to VSL3 of the four signal lines 32 of the first half and the potentials VSL4 to VSL7 of the four signal lines 32 of the second half, and are processed.

[0166] Analog-digital conversion is performed on the potentials VSL0 to VSL3 of the four signal lines 32 of the first half during the P phase, and thus has the same configuration as the intermittent operation in the column signal processing system according to the first embodiment. Since the potentials VSL4 to VSL7 of the four signal lines 32 of the second half are simultaneously sampled and analog-digital converted during the D phase, twice as many capacitive elements are prepared, and the capacitive elements are alternately used each time of sampling.

[0167] Specifically, a circuit of a three-system configuration that performs sampling using a switched capacitor is provided. The first system is a configuration including a switch 191 _A , a switch 192 _A , a switch 193 _A , and a switch 194 _Aand the capacitor element 195 _A The switch 191 _A The switch 192 _A and the switch 193 _A perform on / off operations according to the polarities of the switch control signals S IN0A S VMIA0 S VMA and S SUMA0 .

[0168] The second system is a circuit including the switch 191 _B The switch 192 _B The switch 193 _B The switch 194 _B and the capacitor element 195 _B The switch 191 _B The switch 192 _B and the switch 193 _B perform on / off operations according to the polarities of the switch control signals S IN1B S VMIB0 S VMB and S SUMB0 .

[0169] The third system is a circuit including the switch 191 _C The switch 192 _C The switch 193 _C The switch 194 _C and the capacitor element 195 _C The switch 191 _C 192 _C 193 _C and 194 _C perform on / off operations according to the polarities of the switch control signals S IN1C S VMIC S VMC and S SUMC0 .

[0170] In the capacitance multiplexer 190 according to the column signal processing system of the second embodiment having the above-described configuration, during the P phase, a circuit including the switch 191 _A The switch 192 _A The switch 193 _A The switch 194 _A and the capacitor element 195 _A performs operations with respect to the potentials VSL0 to VSL3 of the four signal lines 32 of the first half. During the D phase, a circuit including the switch 191 _B The switch 192 _B The switch 193 _B The switch 194 _Band the capacitor element 195 _B The circuit including the switch 191 _C , the switch 192 _C , the switch 193 _C , the switch 194 _C , and the capacitor element 195 _C operates on the potentials VSL4 to VSL7 of the four signal lines 32 of the latter half.

[0171] [Third Embodiment]

[0172] The third embodiment is a modification of the second embodiment, and is an example in which the three capacitor elements (195 _A , 195 _B , 195 _C ) of the capacitor unit 19 (capacitor multiplexer 190) are equally used for the potentials VSL0 to VSL3 of the signal lines 32 of two systems and the potentials VSL4 to VSL7 of the signal lines 32. Figure 9 is a circuit diagram showing a configuration outline of the column signal processing system according to the third embodiment.

[0173] (Configuration Example of Column Signal Processing System)

[0174] In the capacitor multiplexer 190 of the column signal processing system according to the third embodiment, the switches 191 _A , 191 _B , and 191 _C of two systems are provided. And, one ends of the switches 191 _0A , 191 _0B , and 191 _0C of one system are commonly connected to the output ends of the column amplifiers 140 of the potentials VSL0 to VSL3 of the four signal lines 32 of the former half, and on / off operations are performed according to the polarities of the switch control signals S IN0A , S IN0B , and S IN0C .

[0175] One ends of the switches 191 _1A , 191 _1B , 191 _1C of the other system are commonly connected to the output ends of the column amplifiers 140 of the potentials VSL4 to VSL7 of the four signal lines 32 of the latter half, and on / off operations are performed according to the polarities of the switch control signals S IN1A , S IN1B , and S IN1C .

[0176] The switches 191 _0A and 191_1A The other end is connected to switch 192 _A The other end is connected to capacitor element 195. _A The input terminal. Switch 191 _0B and switch 191 _1B The other end is connected to switch 192 _B The other end is connected to capacitor element 195. _B The input terminal. Switch 191 _0C and switch 191 _1C The other end is connected to switch 192 _C The other end is connected to capacitor element 195. _C The input terminal.

[0177] (Circuit operation of a signal processing system)

[0178] Figure 10 It is a timing diagram used to illustrate the circuit operation of the column signal processing system according to the third embodiment.

[0179] Figure 10 The timing diagram shows the potential VSL of signal line 32 and the switch control signal S. P and S VR Switch control signal S D S IN and S VM Switch control signal S IN0A and S IN1B Switch control signal S IN0B S IN1C Switch control signal S IN0C and S IN1A and switch control signal S VMA S VMB and S VMC The temporal relationship between them. Figure 10 The timing diagram also shows the switch control signal S VMIA0 To S VMIA3 and S SUMA0 To S SUMA3 Switch control signal S VMIB0 To S VMIB3 and S SUMB0 To S SUMB3 Switch control signal S VMIC0 To S VMIC3 and S SUMC0 To S SUMC3 Clock CK, switch control signal S AZ The timing relationship between the comparator clock CKI and the comparator clock.

[0180] The column amplifier 140 outputs a signal in phase D. Therefore, the three capacitor elements (195)_A 195 _B 195 _C Sampling of the 152 is performed only in phase D, while comparison of the 152 is performed continuously in phases P and D. Figure 10 In the example of the timing diagram, in the first D phase, the potentials VSL0 to VSL3 of signal line 32 pass through capacitor element 195. _A Sampling, and the potentials VSL4 to VSL7 of signal line 32 are passed through capacitor element 195. _B sampling.

[0181] The potentials VSL0 to VSL3 of signal line 32 undergo analog-to-digital conversion in the immediately following P phase, and the potentials VSL4 to VSL7 of signal line 32 undergo analog-to-digital conversion in the second D phase. In the second D phase, due to capacitor element 195... _B Used for analog-to-digital conversion, so at this time the output of column amplifier 140 passes through the available capacitor element 195. _C and capacitor components 195 _A Sampling. At this time, at capacitor element 195 _A The potentials VSL4 to VSL7 of signal line 32, which are different from the previous ones, are sampled. Repeating this operation prevents the same capacitor element from being used every time for the potential VSL of a specific signal line 32.

[0182] In the successive approximation register-type analog-to-digital converter 150, the switch 1512 of the preamplifier 151 is set to the on (closed) state before each analog-to-digital conversion is performed to perform the determination of the capacitor array unit (C DAC The initial value of 155 is automatically zeroed. At this time, switch 194 of capacitor multiplexer 190 is in the off state.

[0183] During automatic zeroing, the capacitor array unit (C DAC )155 is set to an arbitrary reset code, and the reset code at this time is the output code when the input voltage is 0V.

[0184] Automatic zeroing serves to compensate for the offset of the preamplifier 151. However, it should be noted that in this analog-to-digital conversion, since the input capacitors are separated during sampling, the offset cannot be completely compensated.

[0185] After a certain period of time, switch 1512 of preamplifier 151 is set to the off state, and switches 192 and 194 of capacitor multiplexer 190 are set to the on state to transfer charge. Simultaneously, intermediate voltage VM is applied to all capacitor array units 155 (see...). Figure 11 ).

[0186] After setup, the first pulse of the input clock ICK is used to initiate the comparison operation. Multiple inputs of the clock ICK are performed to determine the analog-to-digital conversion result, and the process proceeds to the next analog-to-digital conversion. The auto-zeroing process takes longer than the setup of the capacitor array unit 155, therefore the auto-zeroing has a predetermined length. Furthermore, the time from auto-zeroing to the first clock ICK is set to a predetermined period.

[0187] According to Figure 8 In the configuration of the column signal processing system of the second embodiment shown, capacitor element 195 _A It is always used to sample the potentials VSL0 to VSL3 of signal line 32, but capacitor element 195 _B and capacitor components 195 _C Alternating sampling of the potentials VSL4 through VSL7 of signal line 32 may lead to system errors.

[0188] On the other hand, in the configuration of the column signal processing system according to the third embodiment, it can be clearly seen from the above circuit operation that the three capacitor elements (195) _A 195 _B 195 _C The potentials VSL0 to VSL3 and VSL4 to VSL7 of signal lines 32 are equally applied to both systems, thus avoiding system errors.

[0189] [Fourth Implementation Plan]

[0190] The fourth implementation is an example of an implementation of a signal processing system, and is an example of a configuration of capacitor unit 19 (capacitor multiplexer 190) and a subsequent stage having differential circuitry. Figure 11 This is a circuit diagram showing the structural outline of the column signal processing system according to the fourth embodiment.

[0191] Figure 11 A reference voltage generation unit 160 is shown, which generates a reference voltage used in a column amplifier 140, a capacitor multiplexer 190, and a successive approximation register-type analog-to-digital converter 150. The reference voltage generation unit 160 includes a first amplifier unit 161, a second amplifier unit 162, and a third amplifier unit 163.

[0192] The first amplifier unit 161 generates a local reference voltage VR that defines a zero voltage at the output of the column amplifier 140. The local reference voltage VR is provided to the column amplifier 140 via voltage line L1. The second amplifier unit 162 transmits the common-mode reference voltage V from the output of the preamplifier 151 via voltage line L2. CM Provided to capacitor multiplexer 190. Output common-mode reference voltage V. CMis also supplied to the successive approximation register type analog-digital converter 150 through the voltage line L3. The third amplifier unit 163 generates a high voltage VH, a medium voltage VM, and a low voltage VL used in the capacitor array unit (C DAC ) 155. The high voltage VH, the medium voltage VM, and the low voltage VL are supplied to the capacitor array unit (C DAC ) 155 through the voltage lines L4, L5, and L6.

[0193] During the P phase, the capacitance element 145 of the column amplifier 140 is charged with the local reference voltage VR, and during the D phase, the local reference voltage VR is set as a signal input of the negative side of the capacitance multiplexer (CMUX) 190. The capacitance multiplexer 190 is constituted in a differential manner. The switches 192 _A , 192 _B , and 192 _C are short-circuited between the differences when the comparison is made by the comparator 152, and are not connected to the common node. In this way, since the input side of the capacitance multiplexer 190 is completely isolated when the comparison is made by the comparator 152, the stabilization of the capacitor array unit (C DAC ) 155 in the successive approximation register type analog-digital converter 150 can be accelerated.

[0194] The switches 193 _AP , 193 _AM , 193 _BP , 193 _BM , and 193 _CP , 193 _CM of the output side of the capacitance multiplexer 190 are connected to the voltage line L2 which transmits the output common mode reference voltage V CM , and are in the on state at the time of sampling. The output common mode reference voltage V CM is the same voltage as the input operating potential of the preamplifier 151.

[0195] The high voltage VH, the medium voltage VM, and the low voltage VL generated by the third amplifier unit 163 are the reference voltages of the capacitor array unit (C DAC ) 155. Since the capacitor array unit (C DAC ) 155 operates at high speed when the comparison is made by the comparator 152, the high voltage VH and the low voltage VL are required to be able to respond quickly and have low impedance.

[0196] (Power supply voltage and transistor used)

[0197] Here, for example, the specifications of the power supply voltage are assumed to be 2.8 V (V DD_ H) and 0.8 V (V DD_L).2.8V is the same voltage as used in the pixel 20, and is used for the circuit of the high-breakdown voltage transistor. It is assumed that 0.8V is the voltage used in the logic circuit. The potential VSL of the signal line 32 is at most 2V or more, and cannot be handled by the low-breakdown voltage transistor. Therefore, the column amplifier 140 needs to be constituted by the high-breakdown voltage transistor. The successive approximation register type analog-digital converter 150 needs a high-speed comparison operation, and is expected to be constituted by the low-breakdown voltage transistor. However, it is necessary to note that the drain current of the low-breakdown voltage transistor is large.

[0198] Furthermore, when a plurality of power sources are involved between the loops of the successive approximation register type analog-digital converter 150, an operation margin that absorbs variations between the different power sources is required, and therefore it is important to use a single power source. The high voltage VH and the low voltage VL are set to 0.8V (V DD_ L) and the same voltage as the ground, so as to sufficiently apply a gate voltage to the switches that constitute the capacitor array unit (C DAC ) 155. Since the output of the column amplifier 140 has a high voltage, the switches that constitute the capacitor multiplexer 190 are all constituted by the high-breakdown voltage transistor.

[0199] (level diagram)

[0200] Figure 12 A level diagram is shown. The voltage range of the potential VSL of the signal line 32 varies according to the sensor specifications, but here, it is assumed that the voltage drops with the luminance, with 2V as a reference, and the maximum drop is 450mV. The potential VSL of the signal line 32 is amplified by the column amplifier 140. The higher the gain, the more the noise of the successive approximation register type analog-digital converter 150 in the subsequent stage is suppressed, and the noise of the column amplifier 140 is also reduced. Therefore, it is desirable to obtain as large a gain as possible. However, since the power source voltage is 2.8V, it is necessary to suppress the output of the column amplifier 140 within the range obtained by adding the operation range and margin of the circuit to the power source voltage.

[0201] Here, the gain is set to 4 times, and the range with respect to 2.8V is 1.8V. The input of the successive approximation register type analog-digital converter 150 is a differential voltage, and the input on the negative side is fixed to a reference voltage. When the luminance of the pixel 20 is 0, a difference of 0V is input to the successive approximation register type analog-digital converter 150, and as the pixel becomes brighter (i.e., the potential VSL of the signal line 32 decreases), a negative differential voltage is applied. The relationship with the output code of the successive approximation register type analog-digital converter 150 is such that a difference of 1.8V corresponds to 3 / 4 full scale, and when 0V is input, 7 / 8 full scale is output.

[0202] For a small input signal, the input conversion noise can be reduced by increasing the gain. As Figure 12As shown, when the gain is eight times (x8), the input range is halved. Further, although it is possible to increase the gain, since the contribution of the column amplifier 140 is dominant in the input conversion noise, it is not beneficial to set the gain to be more than eight times.

[0203] A specific configuration example of the column amplifier 140 and the successive approximation register type analog-digital converter 150 will be described below.

[0204] (Configuration Example of Column Amplifier)

[0205] Here, as an example of a specific configuration of the column amplifier 140, a current reuse column amplifier (CRCA) will be exemplified. Since the current reuse column amplifier performs voltage amplification using the bias current of the signal line 32, a non-inverting column amplifier with lower power consumption can be realized. Figure 13 is a circuit diagram showing a configuration example of the current reuse column amplifier.

[0206] The current reuse column amplifier 1400 includes a current amplification transistor 1401, current source transistors 1402 and 1403, series transistors 1404 and 1405, switches 1406, 1407, and 1408, a reference side capacitive element 1409, and a feedback capacitive element 1410.

[0207] Here, for example, a P-channel MOS field effect transistor is used as the current amplification transistor 1401, the current source transistor 1403, and the series transistor 1404. Further, for example, an N-channel MOS field effect transistor is used as the current source transistor 1402 and the series transistor 1405.

[0208] The current amplification transistor 1401 and the current source transistor 1402 are connected in series between a node of the signal line 32 and a reference potential (for example, ground). That is, the source electrode of the current amplification transistor 1401 is connected to the signal line 32. A predetermined bias voltage nbias is applied to the gate electrode of the current source transistor 1402. As a result, the current source transistor 1402 causes a constant bias current corresponding to the predetermined bias voltage nbias to flow through the signal line 32.

[0209] The current source transistor 1403, the series transistor 1404, and the series transistor 1405 are connected in series between a node of the power supply voltage V DD and the drain electrode of the current source transistor 1402. A predetermined bias voltage pbias is applied to the gate electrode of the current source transistor 1403, a predetermined bias voltage pcas is applied to the gate electrode of the series transistor 1404, and a predetermined bias voltage ncas is applied to the gate electrode of the series transistor 1405.

[0210] The switch 1406 is connected between the gate electrode of the current amplification transistor 1401 and the drain electrode of the series transistor 1404 (the drain electrode of the series transistor 1405), and performs on / off operation in accordance with the polarity of a switch control signal S p .

[0211] The reference-side capacitive element 1409 is connected between the gate electrode of the current amplification transistor 1401 and a node of a reference potential (for example, ground). One end of the feedback capacitive element 1410 is connected to the gate electrode of the current amplification transistor 1401.

[0212] The switch 1047 is connected between the other end of the feedback capacitive element 1410 and the drain electrode of the series transistor 1404 (the drain electrode of the series transistor 1405), and performs on / off operation in accordance with the polarity of a switch control signal S D .

[0213] One end of the switch 1408 is connected to a common connection node N 11 between the feedback capacitive element 1410 and the switch 1047, and performs on / off operation in accordance with the polarity of a switch control signal S VR . A local reference voltage VR is applied to the other end of the switch 1408. Thus, the switch 1408 selectively applies the local reference voltage VR to the common connection node N 11 under the control of the switch control signal S VR .

[0214] In the above-described configuration, the current-reuse column amplifier 1400 is configured such that the source electrode of the current amplification transistor 1401 serves as a (+) input terminal, the gate electrode serves as a (-) input terminal, and the common connection node N 12 between the series transistor 1404 and the series transistor 1405 serves as an output terminal. The current amplification transistor 1401 using the bias current of the signal line 32 can efficiently perform voltage amplification.

[0215] In the current-reuse column amplifier 1400 having the above-described configuration, in correspondence with the column amplifier 140 illustrated in Figure 6 , the switch 1406 corresponds to the switch 142 in Figure 6 , the switch 1407 corresponds to the switch 143 in Figure 6 , and the switch 1408 corresponds to the switch 144 in Figure 6 . In addition, the reference-side capacitive element 1409 corresponds to the capacitive element 146 having a capacitance value C S , and the feedback capacitive element 1410 corresponds to the capacitive element 145 having a capacitance value C F .

[0216] (An example of the configuration of a successive approximation register type analog-digital converter)

[0217] The successive approximation register type analog-digital converter 150 has excellent power efficiency. Figure 14 is a detailed circuit diagram of the successive approximation register type analog-digital converter 150.

[0218] The circuit of the successive approximation register type analog-digital converter 150 is configured entirely differentially. In a normal successive approximation register type analog-digital converter, an input capacitor that samples an input voltage and a DAC capacitor (C DAC ) are usually integrated, but here, the input capacitor and the DAC capacitor (C DAC ) are separated for multiplexing.

[0219] Figure 14 An input capacitor unit (hereinafter, for convenience, referred to as "capacitor multiplexer 190") that also functions as the capacitor multiplexer 190 is also shown. Here, for simplicity, only one of the plurality of input capacitor units (190) is shown.

[0220] In the capacitor multiplexer 190, at the time of sampling, switches 191 _P and 191 _M and switches 193 _P and 193 _M are in the on (closed) state to charge the capacitor elements 195 _P and 195 _M with charges. At the time of analog-digital conversion, switches 192 and switches 194 _P and 194 _M are in the on (closed) state, so the capacitor multiplexer 190 is connected to the successive approximation register type analog-digital converter 150.

[0221] Switch 192 is not connected to a specific reference potential, but only shorts between the differences. This is to prevent the in-phase potential on the side of the preamplifier 151 from changing due to the input of the in-phase potential. If the output in-phase potential of the preamplifier 151 matches the output common-mode reference voltage V CM , the input in-phase potential of the preamplifier 151 will always be the same as the output common-mode reference voltage V CM .

[0222] Since the output of the column amplifier 140 is single-ended, the input of the in-phase potential changes according to the signal, but because the input in-phase potential of the preamplifier 151 does not change, the linearity improves. The input side has the output (2.4 V to 0.6 V) of the column amplifier 140 and the local reference voltage VR (2.4 V), but since the output common-mode reference voltage V CMIt is fixed at around 0.5V, so it can be used with low voltage (V) DD_ L) preamplifier 151.

[0223] Although the input differential voltage is as high as 1.8V, due to the interaction with the DAC capacitor (C) during charge transfer... DAC The input voltage of the preamplifier 151 is sufficiently attenuated due to the series connection. In this way, by managing the in-phase and differential voltages, the device, except for the capacitor multiplexer 190, can be constructed from thin-film low-voltage transistors with relatively thin film thickness. Incidentally, all the switches of the capacitor multiplexer 190 are constructed from high-voltage transistors with relatively large film thickness.

[0224] The comparison circuit of the successive approximation register-type analog-to-digital converter 150 includes a preamplifier 151, a comparator 152, a SAR logic unit 153, and a DAC capacitor (C). DAC All switches use transistors with the same power supply voltage and the same film thickness, thus enabling high-speed operation.

[0225] Equally important, the SAR logic unit 153 is completely isolated from the column amplifier 140 and the reference nodes except for the high-voltage VH and low-voltage VL during operation. Because these nodes are not fast and have low impedance, it is necessary to avoid affecting the DAC capacitors (C...). DAC The stability of ).

[0226] like Figure 14 As shown, the DAC capacitor (C) DAC The capacitor array consists of 14 capacitors grouped in a 6-4-4 configuration. The first 6 bits are defined as the MSB, the middle 4 bits as LSB1, and the last 4 bits as LSB0. Each group is separated by a bridge capacitor element, and the weight of each capacitor element varies. When the MSB weight is 1, LSB1 is 1 / 8 and LSB0 is 1 / 32.

[0227] In LSB1, the weight of the most significant bit and the weight of the least significant bit in MSB have the same value and are redundant. Similarly, in LSB0, the most significant bits overlap. Since the redundancy totals 2 bits, the bit precision of the successive approximation register-type analog-to-digital converter 150 ultimately reaches 12 bits. Redundancy is used to compensate for insufficient instability in the higher bits and to correct for nonlinearity caused by variations in the bridge capacitor elements.

[0228] To extend the redundancy range, redundant bits should be inserted as high as possible, but adding capacitors is a trade-off and will also increase noise. Furthermore, to correct for variations in bridge capacitors, redundant bits need to be inserted in each group.

[0229] The capacitance value C of the bridge capacitor element BThe following formula represents the weight ratio of the lower group to the lower group as α (<1), and the total capacitance value of the lower group (including the actual capacitance value) is C. TL .

[0230] C B =C TL / {(1 / α)-1}

[0231] Since the bridge capacitor elements determine the weight of the entire lower bit, deviations in the ratio of the bridge capacitor elements to the unit capacitor elements can cause nonlinearity. Therefore, it is necessary to perform this as unbiasedly as possible; however, due to the non-integer multiples of the ratios and the discontinuous layout, matching the ratios of the bridge capacitor elements to the unit capacitor elements is difficult. Therefore, it is deemed necessary to perform digital correction by multiplying each group by a non-integer correction factor.

[0232] <Second Implementation Plan of this Disclosure>

[0233] A second embodiment of this disclosure is an example of applying the technology according to this disclosure to an indirect time-of-flight (TOF) distance image sensor. An indirect TOF distance image sensor is a sensor that measures the distance to the object being measured by measuring the time of flight of the light, based on detecting the arrival phase difference of reflected light emitted from a light source and reflected by the object being measured (the subject).

[0234] [Example of system configuration]

[0235] Figure 15 This is a block diagram illustrating an example of the system configuration of an indirect TOF distance image sensor according to a second embodiment of the present disclosure.

[0236] In the indirect TOF distance image sensor 50, light emitted from the light source 60 is reflected by the object being measured (the subject), and the reflected light is incident. The indirect TOF distance image sensor 50 has a stacked structure including a sensor chip 51 and a circuit chip 52 stacked on the sensor chip 51. In this stacked structure, the sensor chip 51 and the circuit chip 52 are electrically connected via connection points (not shown), such as through-holes (VIA) or Cu-Cu connections. Note that... Figure 15 The wiring of sensor chip 51 and circuit chip 52 are shown to be electrically connected via the aforementioned connection portion.

[0237] A pixel array unit 53 is formed on the sensor chip 51. The pixel array unit 53 includes a plurality of pixels 54 arranged in a matrix (array) in a two-dimensional grid pattern on the sensor chip 51. In the pixel array unit 53, the plurality of pixels 54 each receive incident light (for example, near-infrared light), perform photoelectric conversion, and output an analog pixel signal. In the pixel array unit 53, two signal lines VSL1 and VSL2 are wired for each pixel column. When the number of pixel columns of the pixel array unit 53 is M (M is an integer), a total of (2 x M) signal lines VSL are wired in the pixel array unit 53.

[0238] The plurality of pixels 54 each have a first tapping portion A and a second tapping portion B (details of which will be described later). An analog pixel signal AIN P1 based on the charge of the first tapping portion A of the pixel 54 in the corresponding pixel column is output to the signal line VSL1 of the two signal lines VSL1 and VSL2. Further, an analog pixel signal AIN P2 based on the charge of the second tapping portion B of the pixel 54 in the corresponding pixel column is output to the signal line VSL2. Details of the analog pixel signals AIN P1 and AIN P2 will be described later.

[0239] A row selection unit 55, a column signal processing unit 56, an output circuit unit 57, and a timing control unit 58 are arranged on the circuit chip 52. The row selection unit 55 drives each pixel 54 of the pixel array unit 53 in units of rows of pixels and outputs the pixel signals AIN P1 and AIN P2 Under the drive of the row selection unit 55, the analog pixel signals AIN P1 and AIN P2 output from the pixels 54 in the selected row are supplied to the column signal processing unit 56 through the two signal lines VSL1 and VSL2.

[0240] The column signal processing unit 56 includes a plurality of analog-digital converters (ADCs) 59 provided corresponding to the pixel columns of the pixel array unit 53 (for example, for each pixel column). The analog-digital converters 59 perform analog-digital conversion processing on the analog pixel signals AIN P1 and AIN P2 supplied through the signal lines VSL1 and VSL2, and output the pixel signals AIN P1 and AIN P2 to the output circuit unit 57. The output circuit unit 57 performs predetermined signal processing on the digital pixel signals AIN P1 and AIN P2 output from the column signal processing unit 56, and outputs the pixel signals AIN P1 and AIN P2Output to the outside of the circuit chip 52.

[0241] The timing control unit 58 generates various timing signals, clock signals, control signals, and the like, and performs drive control of the row selection unit 55, the column signal processing unit 56, the output circuit unit 57, and the like, on the basis of these signals.

[0242] [Example of circuit configuration of pixel]

[0243] Figure 16 is a circuit diagram showing an example of a circuit configuration of the pixel 54 in the indirect TOF range image sensor 50 according to the second embodiment.

[0244] The pixel 54 of this example includes, for example, a photodiode 541 as a photoelectric conversion element. In addition to the photodiode 541, the pixel 54 includes an overflow transistor 542, two transfer transistors 543 and 544, two reset transistors 545 and 546, two floating diffusion layers 547 and 548, two amplification transistors 549 and 550, and two selection transistors 551 and 552. The two floating diffusion layers 547 and 548 correspond to Figure 15 The first tapping portion A and the second tapping portion B (hereinafter, can be simply described as “tapping portions A and B”) shown.

[0245] The photodiode 541 photoelectrically converts received light to generate electric charges. The photodiode 541 can have, for example, a backside-illumination type pixel structure. However, the structure is not limited to the backside-illumination type structure, and can also be a frontside-illumination type structure that acquires light emitted from the front surface side of the substrate.

[0246] The overflow transistor 542 is connected between the cathode electrode of the photodiode 541 and a power supply line of the power supply voltage V DD , and has a function of resetting the photodiode 541. Specifically, the overflow transistor 542 becomes conductive in response to an overflow gate signal TRG supplied from the row selection unit 55, and thus sequentially transfers the electric charges generated in the photodiode 541 to the floating diffusion layers 547 and 548.

[0247] The floating diffusion layers 547 and 548 corresponding to the first tapping portion A and the second tapping portion B accumulate the electric charges transferred from the photodiode 541, convert them into voltage signals having voltage values corresponding to the amounts of the electric charges, and generate pixel signals AIN P1 and AIN P2 .

[0248] The two reset transistors 545 and 546 are respectively connected between the two floating diffusion layers 547 and 548 and a power supply line of the power supply voltage V DDBetween the power lines. Furthermore, reset transistors 545 and 546 become on in response to the reset signal RST provided from the row selection unit 55, thus extracting charge from the floating diffusion layers 347 and 348 respectively, and initializing the amount of charge.

[0249] The two amplifying transistors 549 and 550 are respectively connected to the power supply voltage V. DD The power supply line is between the two selection transistors 551 and 552, and the voltage signal converted from charge to voltage is amplified in the floating diffusion layers 547 and 548, respectively.

[0250] Two selection transistors 551 and 552 are connected between two amplification transistors 549 and 550 and signal lines VSL1 and VSL2, respectively. Furthermore, selection transistors 551 and 552 turn on in response to the selection signal SEL provided from the row selection unit 55, thus outputting the voltage signals amplified by amplification transistors 549 and 550 to the two signal lines VSL1 and VSL2 as analog pixel signals AIN. P1 and AIN P2 .

[0251] Two signal lines, VSL1 and VSL2, are connected to the input of an analog-to-digital converter 59 in the column signal processing unit 56 for each pixel column, and to the analog pixel signal AIN output from pixel 54 for each pixel column. P1 and AIN P2 Transmitted to analog-to-digital converter 59.

[0252] It should be noted that the circuit configuration of pixel 54 is not limited to... Figure 16 The illustrated circuit configuration is valid as long as it can generate analog pixel signals AIN through photoelectric conversion. P1 and AIN P2 That's all.

[0253] In the indirect TOF distance image sensor 50 having the above-described configuration, the technology according to this disclosure can be applied to a column signal processing unit 56 including an analog-to-digital converter 59. Specifically, as the column signal processing unit 56 including the analog-to-digital converter 59, similar to the case of the first embodiment, a column signal processing system according to the first, second, third, or fourth embodiment, including a column amplifier unit 14, a capacitor unit 19, and a successive approximation register type analog-to-digital converter unit 15A, can be used.

[0254] <Variation Example>

[0255] Although the technology according to the present disclosure has been described above based on the preferred embodiments, the technology according to the present disclosure is not limited to these embodiments. The constitution and structure of the CMOS image sensor and the indirect TOF range image sensor described in the above embodiments are examples, and can be changed as appropriate.

[0256] <Application Examples>

[0257] For example, as shown in FIG. 1, the imaging device (CMOS image sensor) according to the first embodiment can be used for various devices that sense light such as visible light, infrared light, ultraviolet light, and X-rays. Specific examples of the various devices are listed below. Figure 17

[0258] • A device for viewing a captured image, such as a digital camera, a portable device with a camera function, and the like.

[0259] • A device for transportation, such as a vehicle-mounted sensor that captures an image of the front, rear, surrounding environment, interior, or the like of a car for safe driving such as automatic stop, recognition of the driver's state, and the like; a monitoring camera that monitors a traveling vehicle and a road; and a range sensor that measures the distance between vehicles, and the like.

[0260] • A device for a home appliance such as a television, a refrigerator, an air conditioner, and the like, for capturing an image of a user's gesture and performing a device operation according to the gesture.

[0261] • A device for medical and health care, such as an endoscope, a device that performs angiography by receiving infrared light, and the like.

[0262] • A device for security, such as a monitoring camera for preventing crime, a camera for human authentication, and the like.

[0263] • A device for beauty care, such as a skin meter for capturing an image of skin, a microscope for capturing an image of a scalp, and the like.

[0264] • A device for sports, such as a motion camera or a wearable camera for sports, and the like.

[0265] • A device for agriculture, such as a camera for monitoring a field and a crop condition, and the like.

[0266] <Application Examples of the Technology According to the Present Disclosure>

[0267] The technology according to the present disclosure can be applied to various products. More specific application examples will be described below.

[0268] [Electronic Device of the Present Disclosure]

[0269] ​Here, a case where the technology according to the present disclosure is applied to an imaging system such as a digital camera or a video camera, a mobile terminal device having an imaging function such as a mobile phone, or an electronic device such as a copier using an imaging device as an image reader will be described.

[0270] (Example of Imaging System)

[0271] Figure 18 is a block diagram showing a configuration example of an imaging system that is an example of the electronic device of the present disclosure.

[0272] As shown in Figure 18 , the imaging system 100 of this example includes an imaging optical system 101 having a lens group or the like, an imaging section 102, a digital signal processor (DSP) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operating system 107, a power supply system 108, and the like. Also, the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operating system 107, and the power supply system 108 are connected to each other via a bus 109.

[0273] The imaging optical system 101 takes in incident light (image light) from a subject and forms an image on an imaging surface of the imaging section 102. The imaging section 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electric signal per pixel and outputs the electric signal as a pixel signal. The DSP circuit 103 performs general camera signal processing such as white balance processing, demosaicing processing, and gamma correction processing, and the like.

[0274] The frame memory 104 is appropriately used to store data in the processing of the signal processing of the DSP circuit 103. The display device 105 includes a panel-type display device such as a liquid crystal display device or an organic electroluminescence (EL) display device, and displays a moving image or a still image taken by the imaging section 102. The recording device 106 records a moving image or a still image taken by the imaging section 102 in a recording medium such as a portable semiconductor memory, an optical disk, a hard disk drive (HDD), or the like.

[0275] The operating system 107 issues operation commands for various functions of the imaging device 100 in response to the operation of a user. The power supply system 108 appropriately supplies various power supplies that are operation power sources of the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operating system 107 to these supply objects.

[0276] In the imaging system 100 having the configuration described above, the imaging apparatus according to the first embodiment described above can be used as the imaging unit 102. In particular, the successive approximation register type analog-to-digital converter in the imaging apparatus according to the first embodiment has excellent power efficiency, so using the imaging apparatus as the imaging unit 102 can help reduce the power consumption of the imaging system 100.

[0277] Application examples of moving bodies

[0278] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as an imaging device mounted on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, unmanned aerial vehicles, ships, robots, construction machinery, agricultural machinery (tractors), etc.

[0279] Figure 19 This is a block diagram illustrating a schematic example of the configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0280] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 19 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0281] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: drive force generating devices such as internal combustion engines or drive motors for generating drive force for the vehicle, drive force transmission mechanisms for transmitting drive force to the wheels, steering mechanisms for adjusting the vehicle's steering angle, and braking devices for generating braking force for the vehicle.

[0282] The body system control unit 12020 controls the operation of various devices mounted to the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a head lamp, a back lamp, a brake lamp, a turn signal lamp, or a fog lamp. In this case, a radio wave transmitted from a portable device or a signal of various switches instead of a key can be input to the body system control unit 12020. The body system control unit 12020 receives the input radio wave or signal and controls a door lock device, a power window device, or a lamp of the vehicle, and the like.

[0283] The outside -vehicle information detecting unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging section 12031 is connected to the outside-vehicle information detecting unit 12030. The outside-vehicle information detecting unit 12030 causes the imaging section 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside-vehicle information detecting unit 12030 can perform a detection process of an object such as a person, a car, an obstacle, a sign, a character on a road surface, or a distance detection process thereto.

[0284] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging section 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the imaging section 12031 can be visible light or invisible light such as infrared rays.

[0285] The in-vehicle information detecting unit 12040 detects information inside the vehicle. The in-vehicle information detecting unit 12040 is connected to, for example, a driver state detecting section 12041 that detects the state of the driver. For example, the driver state detecting section 12041 can include a camera that images the driver. Based on the detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 can calculate the degree of fatigue or concentration of the driver, or can determine whether the driver is dozing off.

[0286] The microcomputer 12051 can calculate a control target value of a driving force generating device, a steering mechanism, or a braking device based on information inside and outside the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the function of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of the vehicle, follow-up running based on a follow-up distance, vehicle speed maintenance running, vehicle collision warning, and lane departure warning of the vehicle, and the like.

[0287] Moreover, the microcomputer 12051 can perform cooperative control to achieve automatic driving that makes the vehicle autonomously travel without depending on the operation of the driver, or the like, by controlling the driving force generation device, the steering mechanism, or the brake device, or the like, on the basis of information about the surroundings of the vehicle obtained by the outside information detection unit 12030 or the in-vehicle information detection unit 12040.

[0288] Moreover, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of information outside the vehicle obtained by the outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control to achieve glare prevention such as switching a high beam to a low beam by controlling the headlamp in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030.

[0289] The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or aurally notifying information to the occupant of the vehicle or outside the vehicle. In Figure 19 In the example, as the output devices, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are shown. The display section 12062 can include at least one of a vehicle-mounted display and a head-up display, for example.

[0290] Figure 20 FIG. 13 is a diagram showing an example of a mounting position of the imaging section 12031.

[0291] In Figure 20 In the example, the vehicle 12100 includes imaging sections 12101, 12102, 12103, 12104, and 12105 as the imaging section 12031.

[0292] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front of the vehicle 12100, the side mirrors, the rear bumper, the rear door, and the upper portion of the windshield in the vehicle, for example. The imaging section 12101 provided at the front and the imaging section 12105 provided at the upper portion of the windshield in the vehicle mainly obtain images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the side mirrors mainly obtain images of the side of the vehicle 12100. The imaging section 12104 provided at the rear bumper or the rear door mainly obtains images of the rear of the vehicle 12100. The front images obtained by the imaging section 12101 and the imaging section 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, and the like.

[0293] Note that Figure 20Examples of imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 indicates an imaging range of the imaging section 12101 provided at the vehicle front. The imaging ranges 12112 and 12113 respectively indicate imaging ranges of the imaging sections 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates an imaging range of the imaging section 12104 provided at the rear bumper or the rear door. For example, by superimposing image data captured by the imaging sections 12101 to 12104, a bird's-eye image of the vehicle 12100 viewed from above can be obtained.

[0294] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera including a plurality of imaging devices, or can be an imaging device having pixels for phase difference detection.

[0295] For example, based on the distance information obtained from the imaging sections 12101 to 12104, the microcomputer 12051 obtains the distance to each of the three-dimensional objects within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100), and thus can extract, as a preceding vehicle, a three-dimensional object that is on a travel route of the vehicle 12100, in particular, closest to the vehicle 12100, and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). Further, the microcomputer 12051 can set a vehicle-to-vehicle distance that is secured in advance with respect to the preceding vehicle, and can perform automatic brake control (including follow-up travel stop control), automatic acceleration control (including follow-up travel start control), and the like. As described above, it is possible to perform cooperative control for autonomous travel of the vehicle without relying on the operation of the driver, such as automatic driving.

[0296] For example, based on the distance information obtained from the imaging sections 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and other three-dimensional objects such as a utility pole, extract the three-dimensional object data, and automatically avoid obstacles using the three-dimensional object data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by a driver of the vehicle 12100 and obstacles that are difficult to be visually recognized. Then, the microcomputer 12051 judges a collision risk indicating a degree of danger of collision with each of the obstacles. When the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer 12051 can perform assist driving to avoid the collision by outputting a warning to the driver via the audio speaker 12061 or the display section 12062, or performing forced deceleration or evasive steering via the drive system control unit 12010.

[0297] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by judging whether a pedestrian is present in an image captured by the imaging sections 12101 to 12104. For example, the recognition of a pedestrian is performed by a step of extracting a feature point in an image captured by the imaging sections 12101 to 12104 as an infrared camera, and a step of performing pattern matching processing on a series of feature points indicating the outline of an object to judge whether the object is a pedestrian. When the microcomputer 12051 judges that a pedestrian is present in an image captured by the imaging sections 12101 to 12104 and recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 to superimpose and display a quadrangular outline for emphasis on the recognized pedestrian. Further, the sound / image output section 12052 can also control the display section 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0298] The above has explained an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging sections 12101, 12102, 12103, 12104, and 12105 and the outside-vehicle information detection unit 12030 in the above-described configuration. Then, in particular, since the successive approximation register type analog-digital converter is excellent in terms of power efficiency, the application of the technology according to the present disclosure can contribute to reduction in power consumption of the vehicle control system.

[0299] <Configuration that the present disclosure can adopt>

[0300] Note that the present disclosure can also adopt the following configuration.

[0301] <Imaging device>

[0302] [A-01] An imaging device comprising:

[0303] a pixel array unit on which a pixel including a photoelectric conversion element is arranged;

[0304] a column amplifier unit that acquires a difference between a reset component and a signal component input from each of the pixels of the pixel array unit through a signal line, and outputs the difference as a pixel signal;

[0305] a capacitance unit that holds the pixel signal input from the column amplifier unit; and

[0306] a successive approximation register type analog-digital conversion unit that converts an analog signal input from the capacitance unit into a digital signal.

[0307] [A-02] The imaging device according to the above-mentioned [A-01], in which

[0308] The column amplifier unit includes:

[0309] an amplifier to which the potential of the signal line is input to a non-inverting input terminal of the amplifier;

[0310] a first switch having one end connected to an output terminal of the amplifier and the other end connected to an inverting input terminal of the amplifier;

[0311] a second switch having one end connected to the output terminal of the amplifier;

[0312] a first capacitive element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier;

[0313] a second capacitive element connected between both of the other end of the first capacitive element and the inverting input terminal of the amplifier and a reference potential node; and

[0314] a third switch having one end connected to the other end of the second switch and the one end of the first capacitive element, and the other end of the third switch to which a local reference voltage is applied.

[0315] [A-03] The imaging device according to the above [A-02], wherein

[0316] in the column amplifier unit,

[0317] when the reset component is input, the first switch is set to a closed state to charge the reset component to the first capacitive element and the second capacitive element, and the third switch is set to a closed state to acquire the local reference voltage,

[0318] then, the first switch and the third switch are set to an open state, the second switch is set to a closed state, and the first capacitive element, the second capacitive element, and the amplifier constitute a non-inverting amplifier circuit,

[0319] when the signal component is input, a feedback is applied so that the voltage at a common connection node between the first capacitive element and the second capacitive element is the same as the voltage of the signal component.

[0320] [A-04] The imaging device according to any one of the above [A-01] to [A-03], wherein

[0321] for one successive approximation register type analog-digital converter of the successive approximation register type analog-digital conversion unit, the potentials of a plurality of the signal lines are multiplexed and processed by a plurality of column amplifiers corresponding to the plurality of signal lines and the capacitive unit.

[0322] [A-05]The imaging device according to [A-04] above, wherein

[0323] The successive approximation register type analog-to-digital converter only performs conversion processing when the reset component is input, and stands by when the signal component is input.

[0324] [A-06]The imaging device according to [A-04] above, wherein

[0325] The successive approximation register type analog-to-digital converter not only performs conversion processing when the reset component is input, but also performs conversion processing when the signal component is input.

[0326] [A-07]The imaging device according to [A-06] above, wherein

[0327] The potentials of the plurality of signal lines are divided into the potentials of signal lines of two systems,

[0328] The capacitor unit includes three capacitor elements, and

[0329] The three capacitor elements of the capacitor unit are equally used for the potentials of the signal lines of the two systems.

[0330] [A-08]The imaging device according to [A-06] above, wherein

[0331] In the column signal processing system including the column amplifier unit, the capacitor unit, and the successive approximation register type analog-to-digital conversion unit, the capacitor unit and the subsequent stage part have a differential circuit configuration.

[0332] [A-09]The imaging device according to [A-08] above, wherein

[0333] Each of the column amplifiers of the column amplifier unit includes a current reuse column amplifier that performs voltage amplification by using the bias current of each of the signal lines.

[0334] [A-10]The imaging device according to any one of [A-01] to [A-09] above, wherein

[0335] The capacitor unit includes a capacitor multiplexer.

[0336] [A-11]The imaging device according to [A-10] above, wherein

[0337] The capacitor unit samples and holds the pixel signal by switched capacitors.

[0338] <<B. Electronic Device>> [[ID=!50]]

[0339] [B-01] An electronic device including an imaging device including:

[0340] a pixel array unit on which a pixel including a photoelectric conversion element is arranged;

[0341] a column amplifier unit that acquires a difference between a reset component and a signal component input from each of the pixels of the pixel array unit through a signal line, and outputs the difference as a pixel signal;

[0342] a capacitance unit that holds the pixel signal input from the column amplifier unit; and

[0343] a successive approximation register type analog-digital conversion unit that converts an analog signal input from the capacitance unit into a digital signal.

[0344] [B-02] The electronic device according to the above [B-01], wherein

[0345] the column amplifier unit includes:

[0346] an amplifier to which a potential of the signal line is input to a non-inverting input terminal of the amplifier;

[0347] a first switch one end of which is connected to an output terminal of the amplifier and the other end of which is connected to an inverting input terminal of the amplifier;

[0348] a second switch one end of which is connected to the output terminal of the amplifier;

[0349] a first capacitance element one end of which is connected to the other end of the second switch and the other end of which is connected to the other end of the first switch and the inverting input terminal of the amplifier;

[0350] a second capacitance element connected between both of the other end of the first capacitance element and the inverting input terminal of the amplifier and a reference potential node; and

[0351] a third switch one end of which is connected to the other end of the second switch and the one end of the first capacitance element, the other end of the third switch to which a local reference voltage is applied.

[0352] [B-03] The electronic device according to the above [B-02], wherein

[0353] in the column amplifier unit,

[0354] when the reset component is input, the first switch is set to a closed state to charge the reset component to the first capacitance element and the second capacitance element, and the third switch is set to a closed state to acquire the local reference voltage,

[0355] Next, the first switch and the third switch are set to an open state, the second switch is set to a closed state, and the first capacitor element, the second capacitor element, and the amplifier constitute a non-inverting amplifier circuit,

[0356] When the signal component is input, feedback is applied so that the voltage at the common connection node between the first capacitor element and the second capacitor element is the same as the voltage of the signal component.

[0357] [B-04] The electronic device according to any one of [B-01] to [B-03] described above, wherein

[0358] For one successive approximation register type analog-digital conversion unit of the successive approximation register type analog-digital conversion unit, the potentials of the plurality of signal lines are multiplexed and processed by a plurality of column amplifiers corresponding to the plurality of signal lines and the capacitor unit.

[0359] [B-05] The electronic device according to [B-04] described above, wherein

[0360] The successive approximation register type analog-digital converter performs conversion processing only when the reset component is input, and stands by when the signal component is input.

[0361] [B-06] The electronic device according to [B-04] described above, wherein

[0362] The successive approximation register type analog-digital converter performs conversion processing not only when the reset component is input, but also when the signal component is input.

[0363] [B-07] The electronic device according to [B-06] described above, wherein

[0364] The potentials of the plurality of signal lines are divided into potentials of signal lines of two systems,

[0365] The capacitor unit includes three capacitor elements, and

[0366] The three capacitor elements of the capacitor unit are equally used for the potentials of the signal lines of the two systems.

[0367] [B-08] The electronic device according to [B-06] described above, wherein

[0368] In a column signal processing system including the column amplifier unit, the capacitor unit, and the successive approximation register type analog-digital conversion unit, the capacitor unit and a subsequent stage portion have a configuration of a differential circuit.

[0369] [B-09] The electronic device according to the above [B-08], wherein

[0370] Each of the column amplifiers of the column amplifier unit includes a current reuse column amplifier that performs voltage amplification by using a bias current of each of the signal lines.

[0371] [B-10] The electronic device according to any one of the above [B-01] to [B-09], wherein

[0372] The capacitance unit includes a capacitance multiplexer.

[0373] [B-11] The electronic device according to the above [B-10], wherein

[0374] The capacitance unit holds the pixel signal by sampling with a switched capacitance.

[0375] List of Reference Signs

[0376] 10 CMOS image sensor

[0377] 11 Pixel array unit

[0378] 12 Row selection unit

[0379] 13 Constant current source unit

[0380] 14 Column amplifier unit

[0381] 15 Analog-digital conversion unit

[0382] 15A Successive approximation register type analog-digital conversion unit

[0383] 16 Horizontal transfer scanning unit

[0384] 17 Signal processing unit

[0385] 18 Timing control unit

[0386] 19 Capacitance unit

[0387] 20 Pixel (pixel circuit)

[0388] 21 Photodiode (photoelectric conversion element)

[0389] 22 Transfer transistor

[0390] 23 Reset transistor

[0391] 24 Amplification transistor

[0392] 25 Selection transistor

[0393] 31 (311 to 31m ) pixel control line

[0394] 32 (321 to 32 n ) signal line

[0395] 50 indirect TOF range image sensor

[0396] 60 light source

[0397] 100 imaging system

[0398] 140 column amplifier

[0399] 150 successive approximation register type analog-to-digital converter

[0400] 160 reference voltage generation unit

[0401] 190 capacitance multiplexer

[0402] 1400 current reuse column amplifier (CRCA)

[0403] VR local reference voltage

[0404] V CM output common mode reference voltage

Claims

1. An imaging device comprising: A pixel array unit, on which pixels including photoelectric conversion elements are arranged; A column amplifier unit acquires the difference between the reset component and the signal component input from each pixel of the pixel array unit via a signal line, and outputs the difference as a pixel signal. A capacitor unit that holds the pixel signal input from the column amplifier unit; as well as A successive approximation register-type analog-to-digital converter (ADC) converts the analog signal input from the capacitor unit into a digital signal. The column amplifier unit includes: An amplifier, wherein the potential input of the signal line is connected to the non-inverting input terminal of the amplifier; The first switch has one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier; The second switch has one end connected to the output terminal of the amplifier; A first capacitor element, one end of which is connected to the other end of the second switch, and the other end of which is connected to the other end of the first switch and the inverting input terminal of the amplifier; A second capacitor element is connected between the other end of the first capacitor element, the inverting input of the amplifier, and the reference potential node; and A third switch, one end of which is connected to the other end of the second switch and one end of the first capacitor element, the other end of which is supplied with a local reference voltage.

2. The imaging device according to claim 1, wherein, In the column amplifier unit, When the reset component is input, the first switch is set to the closed state to charge the reset component to the first capacitor element and the second capacitor element, and the third switch is set to the closed state to obtain the local reference voltage. Next, the first switch and the third switch are set to the open state, the second switch is set to the closed state, and the first capacitor element, the second capacitor element, and the amplifier constitute a non-inverting amplifier circuit. When the signal component is input, feedback is applied such that the voltage at the common connection node between the first capacitor element and the second capacitor element is the same as the voltage of the signal component.

3. The imaging apparatus according to claim 1 or 2, wherein, For a successive approximation register-type analog-to-digital converter (ADC) of the successive approximation register-type ADC unit, the potentials of the multiple signal lines are multiplexed and processed by multiple column amplifiers corresponding to the multiple signal lines and the capacitor units.

4. The imaging device according to claim 3, wherein, The successive approximation register-type analog-to-digital converter performs conversion processing only when the reset component is input, and stands by when the signal component is input.

5. The imaging device according to claim 3, wherein, The successive approximation register-type analog-to-digital converter performs conversion processing not only when the reset component is input, but also when the signal component is input.

6. The imaging apparatus according to claim 5, wherein, The potentials of the multiple signal lines are divided into the potentials of the signal lines in two systems. The capacitor unit includes three capacitor elements, and The three capacitor elements of the capacitor unit are all connected to the signal lines of the two systems in the same way.

7. The imaging apparatus according to claim 5, wherein, In a column signal processing system including the column amplifier unit, the capacitor unit, and the successive approximation register type analog-to-digital converter unit, the capacitor unit and the subsequent stage are configured with differential circuits.

8. The imaging apparatus according to claim 7, wherein, Each of the column amplifiers in the column amplifier unit includes a current-reuse column amplifier that performs voltage amplification using the bias current of each of the signal lines.

9. The imaging apparatus according to claim 1 or 2, wherein, The capacitor unit includes a capacitor multiplexer.

10. The imaging apparatus according to claim 9, wherein, The capacitor unit samples and maintains the pixel signal by switching the capacitor.

11. An electronic device comprising an imaging device, said imaging device being the imaging device according to any one of claims 1 to 10.

Images