Photomask and Method of Manufacturing a Semiconductor Device

Abstract

A photomask and a method of manufacturing a semiconductor device. The photomask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterned region of a device area. The first assist feature is in the patterned region and adjacent to the device features. The first assist feature is used to correct optical proximity effects in an optical lithography process. The second assist feature is in an unpatterned region of the device area. The second assist feature is a sub-resolution assist feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between two adjacent ones of the device features.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to the design of photomasks and methods of forming semiconductor devices, and more particularly, to improvements to photomasks and methods of forming semiconductor devices using improved photomasks. Background Art

[0002] Optical lithography is a process used in the fabrication of semiconductor integrated circuit (IC) devices to create device structures on a semiconductor or other substrate. Given the reduction in the size of device structures compared to the wavelength of the radiation used during optical lithography, distortion of the device structures becomes apparent. Challenges faced by sub-wavelength optical lithography techniques include image distortion in the form of line-end shortening, corner rounding, isolated / dense proximity effects, and adverse effects on depth of focus (DOF). One source of distortion is due to light scattering or the influence of adjacent structures. The distortion of the projected image in terms of size and shape exhibited by this phenomenon is referred to as the proximity effect. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a photomask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterned region of a device area. The first assist feature is in the patterned region and adjacent to the device features. The first assist feature is used to correct optical proximity effects in an optical lithography process. The second assist feature is in an unpatterned region of the device area. The second assist feature is a sub-resolution assist feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent ones of the device features.

[0004] According to some embodiments of the present disclosure, a method includes forming a floating gate material over a memory region of a substrate. A dielectric film, a control gate film, and a hard mask layer are deposited over the floating gate material and a logic region of the substrate. After depositing the hard mask layer, a photoresist layer is deposited over the memory region and the logic region of the substrate. The photoresist layer is patterned using a photomask to form a patterned photoresist layer over the memory region of the substrate. The photomask includes a main feature and two first assist features. The main feature defines the patterned photoresist layer, and a portion of the radiation used to expose the photoresist layer is incident on a portion of the photoresist layer over the logic region of the substrate through a space between the two first assist features. The hard mask layer is patterned using the patterned photoresist layer as a first etch mask to form a hard mask over the memory region of the substrate. The control gate film, the dielectric film, and the floating gate material are patterned using the hard mask as a second etch mask to form a gate stack.

[0005] According to some embodiments of the present disclosure, a method includes forming a gate stack including a floating gate and a control gate over a memory region of a substrate. A protective layer covering the gate stack is deposited and a logic region of the substrate is exposed. After depositing the protective layer, gate material and a hard mask layer are deposited over the logic region of the substrate. After depositing the hard mask layer, a photoresist layer is deposited over the memory region and the logic region of the substrate. Radiation is projected through a photomask onto the photoresist layer to expose the photoresist layer. The photomask includes a patterned region and an unpatterned region. A portion of the radiation passing through the patterned region is incident on a portion of the protective layer over the memory region of the substrate, and another portion of the radiation passing through the unpatterned region is incident on another portion of the protective layer over the logic region of the substrate. The photomask includes a plurality of device features in the patterned region and a plurality of first assist features in the unpatterned region. After projecting the radiation onto the photoresist layer, the photoresist layer is developed to form a patterned photoresist layer defined by the device features. The hard mask layer and the gate material are patterned by using the patterned photoresist layer as an etch mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figure 1 drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Illustrates a simplified optical lithography system according to some embodiments of the present disclosure;

[0008] Figure 2 Illustrates a top view of a photomask according to Figure 1 the present disclosure;

[0009] Figure 3A is an enlarged view of region P in Figure 2 according to some embodiments;

[0010] Figures 3B to 3D is an enlarged view of region P in Figure 2 according to some other embodiments;

[0011] Figures 4A to 4C is a cross-sectional view of the photomask taken along Figure 2 line A-A;

[0012] Figures 5 to 20 Illustrates a method of manufacturing a (flash) memory device at different stages according to some embodiments;

[0013] Figures 21 to 32 Illustrates a method of manufacturing a (flash) memory device at different stages according to some embodiments;

[0014] Figure 33 is Figure 2 an enlarged view of one of the device regions in

[0015] Figure 34A illustrates according to the present disclosure Figure 1 a top view of the photomask in

[0016] Figure 34B is Figure 34A an enlarged view of one of the device regions in

[0017] Figure 35 is a flowchart of a method for modifying an IC design layout before mask manufacturing according to various aspects of the present disclosure;

[0018] Figure 36 is a block diagram of an IC device design system according to some embodiments of the present disclosure;

[0019] Figure 37 is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to some embodiments of the present disclosure.

[0020]

Symbol Description

[0021] 10: Wafer

[0022] 12: Memory cell

[0023] 14: Memory cell

[0024] 16: Logic transistor

[0025] 100: Optical lithography system

[0026] 110: Light source

[0027] 112: Radiation

[0028] 120: Wafer stage

[0029] 130: Mask holder

[0030] 140: Lens system

[0031] 150: Lens system

[0032] 200: Photomask

[0033] 200′: Photomask

[0034] 202: Exposure field

[0035] 210: Main feature

[0036] 212: Device region

[0037] 212a: Patterned area

[0038] 212a': Patterned area

[0039] 212b: Unpatterned area

[0040] 212b': Unpatterned area

[0041] 215: Main feature

[0042] 220: Auxiliary feature

[0043] 225: Auxiliary feature

[0044] 225': Auxiliary feature

[0045] 225'': Auxiliary feature

[0046] 230: Substrate

[0047] 232: Front side of 230

[0048] 234: Back side of 230

[0049] 240: Absorption band

[0050] 310: Substrate

[0051] 312: Memory area

[0052] 312t: Top surface

[0053] 313: Groove

[0054] 314: Logic area

[0055] 314t: Top surface

[0056] 320: Buffer layer

[0057] 325: Tunnel layer

[0058] 330: Mask layer

[0059] 340: Isolation structure

[0060] 350: Floating gate layer

[0061] 350': Floating gate material

[0062] 355: Floating gate

[0063] 360: Dielectric film

[0064] 365: Dielectric layer

[0065] 370: Control gate film

[0066] 375: Control gate

[0067] 380: Hard mask layer

[0068] 385: Hard mask

[0069] 390: Protection layer

[0070] 400: Gate stack

[0071] 405: Gate spacer

[0072] 410: Gate dielectric layer

[0073] 410′: Dielectric layer

[0074] 420: Gate structure

[0075] 420′: Gate material

[0076] 430: Hard mask layer

[0077] 430′: Hard mask layer

[0078] 440: LDD region

[0079] 450: Gate spacer

[0080] 452: First spacer layer

[0081] 454: Second spacer layer

[0082] 460: Source / drain feature

[0083] 465: Source / drain feature

[0084] 470: Metal alloy layer

[0085] 480: ILD layer

[0086] 490: Contact

[0087] 500: Gate stack

[0088] 510: Spacer structure

[0089] 520: Source region

[0090] 525: CS dielectric layer

[0091] 530′: Conductive layer

[0092] 532: Erase gate

[0093] 534: Select gate

[0094] 540′: Hard mask layer

[0095] 600: Method

[0096] 612, 614, 616, 618: Operations

[0097] 3600: IC Device Design System

[0098] 3602: Hardware Processor

[0099] 3604: Non - Transitory Computer - Readable Storage Medium

[0100] 3606: Instructions

[0101] 3608: Bus

[0102] 3610: I / O Interface

[0103] 3612: Network Interface

[0104] 3614: Network

[0105] 3620: IC Layout Design Diagram

[0106] 3622: Design Specification

[0107] 3624: Manufacturing Tool

[0108] 3700: IC Manufacturing System

[0109] 3720: Design Studio

[0110] 3722: IC Design Layout Diagram

[0111] 3730: Mask Studio

[0112] 3732: Mask Data Preparation

[0113] 3744: Mask Manufacturing

[0114] 3745: Mask

[0115] 3750: IC Wafer Fab

[0116] 3752: Wafer Manufacturing

[0117] 3753: Semiconductor Wafer

[0118] 3760: IC Device

[0119] D1: First Direction

[0120] D2: Second Direction

[0121] A - A: Line

[0122] A1, A2, A3: Areas

[0123] CDBAR: Critical Dimension Bar Pattern

[0124] d1, d2, d3, d4, d5: Distance

[0125] d2′, d2″: Distance

[0126] L1, L2, L3: Length

[0127] M1, M2, M3, M4, M5: Patterned Photoresist Layer

[0128] M2a: Patterned Photoresist Layer

[0129] M2′, M3, M4, M5′: Photoresist Layer

[0130] W1, W2, W3, W4, W5: Width

[0131] O1: Opening

[0132] OVL: Overlying Pattern

[0133] P: Region

[0134] PCM: Process Control Monitor Pattern

[0135] IDNT: Identification Pattern Detailed Implementation Modes

[0136] The following disclosure provides many different implementation modes, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an implementation mode in which the first feature and the second feature are formed in direct contact, and may also include an implementation mode in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various implementation modes and / or configurations discussed.

[0137] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. The spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0138] As used herein, "about", "circa", "substantially", or "approximately" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. Quantities given herein are approximate, such that the terms "about", "circa", "substantially", or "approximately" may be inferred where not expressly stated.

[0139] In view of the challenges posed by sub-wavelength optical lithography, resolution enhancement technology (RET) has been designed to extend the available resolution of an imaging system without reducing the wavelength of light or increasing the numerical aperture of the imaging tool. RET includes phase-shifting masks, off-axis illumination (OAI), and optical proximity correction (OPC). Embodiments of the present disclosure provide new and unique assist features (or scattering bars) to improve image distortion problems. The term scattering bar refers to both scattering bars and anti-scattering bars. The disclosure herein describes assist features placed in the non-patterned regions of a photomask, which are regions without primary features.

[0140] For example, when a photomask is used for patterning features of a flash memory device (e.g., control gates, floating gates, select gates, or other elements), the patterned regions of the photomask correspond to the memory regions of the flash memory device, and the non-patterned regions of the photomask correspond to the logic regions of the flash memory device. In such a case, primary features are only provided in the patterned regions of the photomask and not in the non-patterned regions of the photomask. Additionally, some assist features are provided in the non-patterned regions of the photomask to address heating issues of the photomask, thereby improving the image performance of optical lithography.

[0141] Figure 1FIG. 0 illustrates a simplified optical lithography system 100 according to some embodiments of the present disclosure. The optical lithography system 100 includes a light source 110 for projecting radiation 112 onto a wafer 10 disposed on a wafer stage 120 via an optical lithography mask (or mask or reticle) 200, and the optical lithography mask 200 is supported by a mask holder 130. Various lenses (e.g., lens systems 140 and 150) and other light manipulation and / or emission devices may also be provided. For example, the lens system 140 is disposed between the light source 110 and the main mask holder 130, and the lens system 150 is disposed between the main mask holder 130 and the wafer stage 120. In some embodiments, the lens system 140 includes a single lens or multiple lenses and / or other lens components. For example, the lens system 140 includes a microlens array, a shadow mask, or other structures designed to help guide the radiation 112 from the light source 110 to the mask 200. In some embodiments, the lens system 150 is a projection optics box (POB) that includes refractive optics and / or reflective optics.

[0142] The radiation 112 may include ultraviolet (UV) light (e.g., KrF (248 nm) light or ArF (193 nm) light), extreme ultraviolet (EUV) (13.5 nm) light, an electron beam, an X-ray, or an ion beam. In a further implementation of this embodiment, the wafer 10 is a semiconductor wafer for receiving an integrated circuit pattern from the mask 200. The pattern from the mask 200 will appear on a layer of the wafer 10, thereby producing an integrated circuit device or chip when combined with other layers.

[0143] The radiation 112 projected from the light source 110 passes through the lens system 140 to the mask 200, and the pattern of the mask 200 is imparted to the radiation 112, and then the radiation 112 passes through the lens system 150 to the wafer 10. Thus, the pattern from the mask 200 will appear on the layer of the wafer 10. In some embodiments, the mask 200 includes a small amount of pattern, resulting in most of the radiation 112 passing through the mask 200 to the lens system 150. In this case, the lens system 150 absorbs a large amount of heat from the radiation 112 and begins to heat up. The large amount of heat in the lens system 150 causes lens distortion in the lens system 150, resulting in image distortion of the pattern projected onto the wafer 10.

[0144] Therefore, the mask 200 can be designed to solve the problems of the lens system 150. Figure 2 FIG. illustrates the top view of the mask 200 according to the present disclosure Figure 1 and Figure 3A is according to some embodiments Figure 2Enlarged view of the middle region P. Refer to Figure 2 and Figure 3A . The photomask 200 has an exposure field 202, and the exposure field 202 includes a region of the wafer 10 (see Figure 1 ) covered (e.g., exposed) by a single exposure or “shot”. In some embodiments, the photomask 200 includes an absorption band 240, and the exposure field 202 is enclosed (and defined) by the absorption band 240. The photomask 200 also includes main features 210, 215 and auxiliary features 220, 225, which are placed in the exposure field 202 and in configurations according to various aspects of the present disclosure. For clarity, Figure 3A illustrates the main feature 215 and the auxiliary features 220, 225, and in Figure 2 these features are omitted. The configurations of the auxiliary features 220 and 225 are described in more detail below. Although described herein as provided on the photomask 200, the main features 210, 215 also illustrate features and configurations (e.g., layouts) developed in device design (e.g., integrated circuit design). For example, the configuration can be represented by data used during the design or manufacturing process, including the layout represented by the output of a design file (e.g., GDS output).

[0145] The photomask 200 can be a binary mask, a phase shift mask including an attenuated phase shift mask (attPSM), an alternating phase shift mask (altPSM), chromeless phase lithography (CPL), and / or other mask types. The photomask 200 also includes a substrate 230 (see Figures 4A to 4C ). The substrate 230 can be a transparent substrate such as fused silica (SiO 2 ), or quartz, relatively defect-free, calcium fluoride, or other suitable materials. In some embodiments, the main features 210, 215, the auxiliary features 220 and 225, and the absorption band 240 are disposed above or in the substrate 230.

[0146] The main features 210 and 215 can be designed to form part of an integrated circuit pattern on a semiconductor wafer, as Figure 1wafer 10. The main feature 210 may be a scribing feature surrounding the main feature 215. Specifically, the main feature 210 at least defines a device region 212, and each device region 212 corresponds to a die of the wafer 10. The scribing feature 210 can be transferred onto the wafer 10 to create scribing on the wafer 10. A cutting operation uses a cutter to cut the wafer 10 into individual dies along the scribing. In some embodiments, the scribing feature (i.e., the main feature 210) includes an overlay pattern OVL, a critical dimension bar pattern CDBAR, a process control monitor pattern PCM, an identification pattern IDNT, a frame cell (not shown), and / or a wafer acceptance test pattern (not shown). The overlay pattern OVL is used to align multiple layers formed on the wafer 10. The critical dimension bar CDBAR is designed to measure critical process dimensions in a semiconductor device manufacturing process. The process control monitor pattern PCM includes those for measuring electrical parameters of active devices (threshold voltage, gate diode breakdown, channel length / width reduction, drain / source series resistance, etc.), properties of passive devices (area capacitance, sheet resistance, contact / via resistance, etc.), and in-line related parameters such as line width control and alignment. The identification pattern IDNT is converted into an identification of the wafer 10. Figure 2 The positions of the overlay pattern OVL, the critical dimension bar pattern CDBAR, the process control monitor pattern PCM, and the identification pattern IDNT in [the figure] are exemplary and do not limit the claims.

[0147] The main feature (or device feature) 215 is placed in the device region 212 and can be designed to form integrated circuit features such as contacts (e.g., vias), insulating regions, conductive lines, source / drain features, gates, doped regions, and / or other possible features. Although shown as rectangular, the main feature 215 can include any variations in shape, size, and / or dimension. Additionally, the shape, size, dimension, and position of the main feature 215 can be modified during the design and mask manufacturing process.

[0148] In some embodiments, an optical proximity correction (OPC) process is applied to the mask 200 for resolution enhancement. Optical proximity correction is an optical lithography enhancement technique used to compensate for image errors caused by diffraction or process effects. Optical proximity correction is used in wafer lithography to produce printed images that match the design intent while optimizing critical dimension control. Optical proximity correction improves image fidelity by adding and subtracting small enhancement shapes from the original pattern data. In some embodiments, auxiliary features 220 are added to the mask 200 and are close to the main feature 215 to enhance resolution. The auxiliary features 220 can be secondary resolution assist features. In other words, their size is such that the features do not image onto the wafer 10 when the mask 200 is irradiated. Although illustrated as rectangular, the auxiliary features 220 can include any variation in shape, size, and / or dimensions. Additionally, the shape, size, dimensions, and location of the auxiliary features 220 can be modified during the design and mask fabrication processes.

[0149] In some embodiments, the mask 200 is used to expose only some regions of the wafer 10 (see Figure 1 ). For example, the mask 200 is used to expose the memory region of a memory device rather than the logic region, and vice versa. Alternatively, the mask 200 is used to expose the core region of an integrated circuit rather than the input / output region, and vice versa. In these cases, the main features 215 of the mask 200 may not be uniformly distributed in the device region 212. Additionally, large areas of the device region 212 not occupied by the main features 215 (and the auxiliary features 220) are blank, and the radiation 112 can pass through them. The radiation 112 passing through the blank regions can cause significant heat in the lens system 150 (see Figure 1 ), which in turn causes image distortion on the wafer 10.

[0150] Some embodiments of the present disclosure provide auxiliary features 225 to address the heating problem. Taking the mask for exposing a memory device as an example, the device region 212 has a patterned region 212a and an unpatterned region 212b. In some embodiments, the patterned region 212a and the unpatterned region 212b are arranged along a first direction D1. In some embodiments, the area A1 of the patterned region 212a can be greater than, equal to, or less than the area A2 of the unpatterned region 212b.

[0151] In some embodiments, the patterned region 212a corresponds to the memory region of the memory device, and the unpatterned region 212b corresponds to the logic region of the memory device. That is, the radiation 112 passing through the patterned region 212a (see Figure 1) A portion of the radiation is incident on the memory region of the memory device, and another portion of the radiation 112 passing through the non-patterned region 212b is incident on the logic region of the memory device. The main feature 215 and the auxiliary feature 220 are placed in the patterned region 212a and not in the non-patterned region 212b. In this case, the main feature 215 can be used to pattern control gates, floating gates, select gates, or other components in the memory region of the memory device, and the auxiliary feature 220 is placed close to the main feature 215 for enhancing resolution.

[0152] The auxiliary feature 225 is placed in the non-patterned region 212b to block the radiation 112. Thus, the radiation 112 can only pass through the regions not occupied by the auxiliary feature 225 (e.g., the spaces between the auxiliary features 225), so that the intensity of the radiation 112 passing through the mask 200 can be reduced, and the heat generation problem of the lens system 150 can be improved. The auxiliary feature 225 can be a secondary resolution assist feature. In other words, its size is such that the feature does not image onto the wafer 10 when the mask 200 is irradiated. Although illustrated as rectangular, the auxiliary feature 225 can include any variations in shape, size, and / or dimensions. In addition, the shape, size, dimensions, and position of the auxiliary feature 225 can be modified during the design and mask fabrication process.

[0153] In some embodiments, the sizes (e.g., length, width, and / or diameter) of the main features 210 and 215 are all larger than the printable size, which is defined as the minimum size that can be printed onto a photoresist layer during a lithography patterning process. For example, Figure 3A at least one of the main features (i.e., device features) 215 has a length L1 and a width W1, and both the length L1 and the width W1 are larger than the printable size. Note that the main feature 215 can have different sizes (e.g., different lengths and / or different widths). In addition, in Figure 2 the minimum size (width W2 in this example) of the main feature (i.e., scribe feature) 210 is larger than the printable size. In some embodiments, when the radiation 112 is 193 nm light, the printable size can be in the range of about 25 nm to about 30 nm (or in the range of about 27 nm to about 29 nm).

[0154] In some embodiments, the auxiliary features 220 and 225 have several sizes (e.g., length, width, and / or diameter), and the minimum sizes of the auxiliary features 220 and 225 are smaller than the printable size. For example, Figure 3AAt least one of the auxiliary features 220 has a length L2 and a width W3, and at least the width W3 is less than the printable size. In some other embodiments, both the length L2 and the width W3 are less than the printable size. Note that the auxiliary features 220 may have different sizes (e.g., different lengths and / or different widths). In addition, at least one of the auxiliary features 225 has a length L3 and a width W4, and at least the width W4 is less than the printable size. In some other embodiments, both the length L3 and the width W4 are less than the printable size. Note that the auxiliary features 225 may have different sizes (e.g., different lengths and / or different widths).

[0155] Therefore, the width W1 of the main feature 215 is greater than the width W3 of the auxiliary feature 220. In addition, the width W1 of the main feature 215 is greater than the width W4 of the auxiliary feature 225. Additionally, the width W2 of the main feature 210 is greater than the width W3 of the auxiliary feature 220. In addition, the width W2 of the main feature 210 is greater than the width W4 of the auxiliary feature 225. In some embodiments, the width W3 of the auxiliary feature 220 is greater than the width W4 of the auxiliary feature 225. In some embodiments, the width W4 of the auxiliary feature 225 is greater than the width W3 of the auxiliary feature 220, but less than the width W1 of the main feature 215 and / or the width W2 of the main feature 210.

[0156] In some embodiments, the minimum distance d1 between each of the auxiliary features 225 and the main feature 215 is greater than about 1 um. For example, the minimum distance d1 is greater than about 1 um and less than the maximum size (length) of the exposure field 202 of the reticle 200. For example, the minimum distance d1 is greater than about 1 um and less than about 200 mm. In other words, each of the auxiliary features 225 is spaced apart from any main feature 215 by at least 1 um. In some embodiments, the minimum distance d1 is greater than the distance d5 between adjacent ones of the main features 215 (for clarity, see Figure 3C ). Therefore, the auxiliary features 225 are used to reduce the transparent area in the non-patterned region 212b and are not used for the resolution enhancement of the main feature 215. On the other hand, the distance (e.g., distance d4) between any one of the auxiliary features 220 and the nearest main feature 215 is less than the minimum distance d1 between each of the auxiliary features 225 and the main feature 215.

[0157] Since the auxiliary features 220 are used to enhance the resolution of the main feature 215, the positions of the auxiliary features 220 are determined based on the shape of the main feature 215. For example, the auxiliary features 220 are disposed close to the main feature 215 and may be disposed at the corners and / or on the sides of the main feature 215. On the other hand, as Figure 3AAs shown, the auxiliary features 225 can be randomly placed in the non-patterned region 212b. As long as the auxiliary features 225 are disposed in the non-patterned region 212b, the embodiment falls within the scope of this disclosure.

[0158] In some embodiments, the minimum distances d2 (in the first direction D1) and d2' (in the second direction D2 perpendicular to the first direction D1) are defined between adjacent ones of the auxiliary features 225. In some embodiments, when the photomask 200 is used in an immersion 193-nm lithography process, the minimum distance d2 (or d2') is greater than about 0.06 um and less than the width W5 of the non-patterned region 212b. In some embodiments, when the photomask 200 is used in a dry 193-nm lithography process, the minimum distance d2 (or d2') is greater than about 0.16 um and less than the width W5 of the non-patterned region 212b. If the minimum distance d2 (or d2') is less than about 0.06 um (or 0.16 um), two adjacent auxiliary features 225 may be misidentified as main features and appear on the wafer 10.

[0159] In some embodiments, the exposure field 202 has an area A3, and the area occupied by all the main features 210, 215 and the auxiliary features 220, 225 is greater than about 5% of the area A3. Depending on different device designs, the main features 210 and 215 occupy different percentages of the area A3 in the exposure field 202. In some embodiments, the area occupied by all the main features 210, 215 is about 80% - 90% of the area A3. In still some other embodiments, the area occupied by all the main features 210, 215 is about 40% - 50% of the area A3. In yet some other embodiments, the area occupied by all the main features 210, 215 is about 20% - 30% of the area A3 (e.g., when the photomask 200 is only used to expose elements in the memory region or the logic region of a flash memory device). As long as the area occupied by all the main features 210, 215 is greater than about 1% of the area A3, the embodiment falls within the scope of this disclosure.

[0160] In some embodiments, the total area occupied by the auxiliary features 225 is greater than the total area occupied by the main features 210, 215 (e.g., Figure 34B ). In some embodiments, the total area occupied by the auxiliary features 225 is several times the total area occupied by the main features 210, 215. For example, the total area occupied by the auxiliary features 225 is about 4% of the area A3, and the total area occupied by the main features 210, 215 is about 1% of the area A3.

[0161] Figures 3B to 3D is according to some other embodiments Figure 2 An enlarged view of the region P in Figure 3BIn [reference], the photomask 200 further includes an auxiliary feature 225' between the main feature 215 and the auxiliary feature 225. The shape, profile, and dimensions of the auxiliary feature 225' are similar to or substantially the same as those of the auxiliary feature 225. Therefore, the description in this regard will not be repeated hereinafter. The minimum distance d3 between each auxiliary feature 225' and the main feature 215 is less than about 1 um. The auxiliary feature 225' is used to reduce the transparent area of the non-patterned region 212b and is not used for resolution enhancement, such that the auxiliary feature 225' is not as close to the main feature 215 as the auxiliary feature 220 (see Figure 3A ). That is, the distance (e.g., distance d4) between any one of the auxiliary features 220 and the nearest main feature 215 is less than the distance (e.g., distance d3) between any one of the auxiliary features 225' and the nearest main feature 215.

[0162] In Figure 3C and Figure 3D , the shape of the auxiliary feature 225 is different from that of the auxiliary feature 225 in Figure 3A and Figure 3B . However, Figure 3C and Figure 3D , the minimum size of the auxiliary feature 225 is less than the printable size. In some embodiments, the minimum distance d2″ between two adjacent ones of the auxiliary features 225 is greater than the minimum distance d5 between two adjacent ones of the main features 215, but the scope of the patent application of the present disclosure is not limited thereto. In Figure 3D , the photomask 200 further includes at least one auxiliary feature 225″ that interconnects at least one of the main features 215 and at least one of the auxiliary features 225. For example, the auxiliary feature 225″ extends in a first direction D1, and the main feature 215 and the auxiliary feature 225 extend in a second direction D2. Note that Figures 3A to 3D , the extending directions of all the main features 215 and the auxiliary features 220, 225, 225', and 225″ in [[reference]] are illustrative and should not limit the scope of the patent application of the present disclosure.

[0163] Figures 4A to 4C is a cross-sectional view of the photomask 200 taken along the line A-A in Figure 2 . In Figure 4A , the main feature 215 (and Figure 2 the main feature 210 in [[reference]]) and the auxiliary feature 225 (and Figures 3A to 3D the auxiliary features 220, 225', 225″ in [[reference]]) can be formed of an attenuation material disposed on the substrate 230. The attenuation material may include chromium or other materials, such as, for example, gold (Au), molybdenum silicide (MoSi), chromium nitride (CrN), molybdenum (Mo), niobium pentoxide (Nb 2 O 5 ), titanium (Ti), tantalum (Ta), molybdenum trioxide (MoO3 ) molybdenum nitride (MoN), chromium(III) oxide (Cr 2 O 3 ), titanium nitride (TiN), zirconium nitride (ZrN), titanium dioxide (TiO 2 ), tantalum nitride (TaN), tantalum pentoxide (Ta 2 O 5 ), niobium nitride (NbN), silicon nitride (Si 3 N 4 ), zirconium nitride (ZrN), aluminum oxide (Al 2 O 3 ), or a combination thereof. The primary features 210, 215 and the secondary features 220, 225, 225′, and 225″ can be formed using a process that includes photoresist deposition, soft baking, mask alignment, exposure (e.g., patterning), baking, developing the photoresist, hard baking, resist stripping, and / or other processes. In alternative embodiments, the lithography pattern can include electron beam writing, ion beam writing, maskless lithography, and / or nanoimprinting. Although illustrated as symmetric and square features, the primary features 210, 215 and the secondary features 220, 225, 225′, and 225″ can be of any shape, size, or dimension.

[0164] In some other embodiments, as Figure 4B shown, at least the secondary features 225 (225′, 225″) are embedded in the substrate 230, while the primary features 215 (and 210 and the secondary feature 220) are disposed on the substrate 230. In some other embodiments, as Figure 4C shown, at least the secondary features 225 (225′, 225″) are disposed on the back surface 234 of the substrate 230, while the primary features 215 (and 210 and the secondary feature 220) are disposed on the front surface 232 of the substrate 230.

[0165] Figures 5 to 20 FIG. illustrates a method of manufacturing a (flash) memory device at different stages according to some embodiments. It should be understood that for additional embodiments of the method, additional operations can be provided before, during, and after the processes shown in Figures 5 to 20 , and some of the operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged. Refer to Figure 5。Provide a substrate 310. In some embodiments, the substrate 310 can be a semiconductor substrate, such as a bulk silicon substrate, a germanium substrate, a compound semiconductor substrate, or other suitable substrates. The substrate 310 can include an epitaxial layer overlying a body semiconductor, a silicon-germanium layer overlying a body silicon, a silicon layer overlying a body silicon-germanium, or a semiconductor-on-insulator (SOI) structure. The substrate 310 includes a memory region 312 and a logic region 314. The logic region 314 is located at at least one edge of the memory region 312. The area of the logic region 314 can be greater than, equal to, or less than the area of the memory region 312.

[0166] Then, the memory region 312 of the substrate 310 is recessed (such as by etching). Thus, a groove 313 is formed in the memory region 312 of the substrate 310. The top surface 312t of the memory region 312 is lower than the top surface 314t of the logic region 314.

[0167] Next, a liner layer 320 is formed over the substrate 310. The liner layer 320 can be formed of a dielectric material, such as an oxide layer. A mask layer 330 is formed over the liner layer 320. In some embodiments, the mask layer 330 is formed of a dielectric material, such as silicon nitride (SiN) or other suitable materials. Subsequently, a plurality of isolation structures 340 are formed in the substrate 310. More specifically, a plurality of trenches are formed in the substrate 310, and a dielectric material covers the substrate 310, the liner layer 320, and the mask layer 330. In some embodiments, the dielectric material includes an oxide and / or other dielectric materials. Optionally, a liner oxide (not shown) can be formed in advance. In some embodiments, the liner oxide can be a thermal oxide. In some other embodiments, in-situ steam generation (ISSG) can be used to form the liner oxide. In still some other embodiments, selective area chemical vapor deposition (SACVD) or other common CVD methods can be used to form the liner oxide. The formation of the liner oxide reduces the electric field, thus improving the performance of the resulting semiconductor device. Then, chemical mechanical polish (CMP) is performed to make the top surface of the dielectric material flush with the top surface of the mask layer 330, thereby forming a plurality of isolation structures 340.

[0168] Reference Figure 6 。A patterned photoresist layer M1 is formed over the logic region 314 of the substrate 310 to cover the structure disposed over the logic region 314 of the substrate 310, and expose the structure disposed over the memory region 312 of the substrate 310. Then, the mask layer 330 is removed (seeFigure 5 ) above the memory region 312. In this way, a portion of the liner layer 320 above the memory region 312 is exposed, and this portion of the liner layer 320 can be referred to as the tunneling film.

[0169] Reference Figure 7 . Then, the patterned photoresist layer M1 (see Figure 6 ) is removed, and the removal method can be performed by, for example, solvent stripping or plasma ashing. The floating gate material 350' is conformally formed above the substrate 310. The floating gate material 350' can include polysilicon formed by, for example, a low pressure CVD (LPCVD) method, a CVD method, and a PVD sputtering method using a suitable silicon source material. If needed, the floating gate material 350' can be ion implanted to the desired conduction type. It should be understood that other gate electrode materials, such as metals, metal alloys, single crystal silicon, or combinations thereof.

[0170] Reference Figure 8 . Figure 7 The floating gate material 350' in Figure 8 is patterned into the floating gate layer 350 above the memory region 312. In some embodiments, a planarization process including a chemical mechanical planarization (CMP) process is performed to remove a portion of the floating gate material 350' until the top surface of the isolation structure 340 is exposed, and then an etch-back process is performed to remove another portion of the floating gate material 350' until the remaining floating gate layer 350 has the desired thickness. In some embodiments, as shown in

[0171] Reference Figure 9 . In Figure 8 above the structure, a dielectric film 360 is conformally formed. In some embodiments, the dielectric film 360 and the tunneling film 320 can have the same or different materials. The dielectric film 360 can include, for example, a dielectric material such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4) silicon oxynitride (SiON), high-k materials, other non-conductive materials, or combinations thereof. In some embodiments, the dielectric film 360 has an oxide-nitride-oxide (ONO) structure, including an oxide layer, a nitride layer above the oxide layer, and an additional oxide layer above the nitride layer. Chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), ozone oxidation, other suitable processes, or combinations thereof can be used to form the dielectric film 360.

[0172] Next, a control gate film 370 is conformally formed over the dielectric film 360. The control gate film 370 can include polysilicon formed by, for example, a low pressure CVD (LPCVD) method, a CVD method, and a PVD sputtering method using a suitable silicon source material. If desired, the control gate film 370 can be ion implanted to the desired conduction type. It should be understood that other gate electrode materials, such as metals, metal alloys, single crystal silicon, or combinations thereof.

[0173] A hard mask layer 380 is conformally formed over the control gate film 370. The hard mask layer 380 can include a single layer or multiple layers. In some embodiments, the hard mask layer 380 includes a SiN / SiO 2 / SiN stacked layer or other suitable materials. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (ALD), ozone oxidation, other suitable processes, or combinations thereof can be used to form the hard mask layer 380.

[0174] Reference Figure 10 and Figure 11 . A patterned photoresist layer M2 is formed over the memory region 312 of the substrate 310, and the logic region 314 of the substrate 310 is exposed. For example, the patterned photoresist layer M2 is formed by a combination of spin coating, exposure, and development processes. Specifically, a photoresist layer M2' is formed over the Figure 9 structure, and a patterning process is performed using a mask to remove at least a portion of the photoresist layer M2' to form the patterned photoresist layer M2, as shown in Figure 11 . That is, the patterned photoresist layer M2 is formed over the memory region 312 of the substrate 310 and not over the logic region 314 of the substrate 310.

[0175] For example, Figure 10 The structure of can be disposed on Figure 1 the wafer stage 120 of, and the reticle is disposed on the main reticle support 130. The light source 110 then provides radiation 112 to the reticle to expose the photoresist layer M2'. The exposed photoresist layer M2' is then baked, developed, and hard baked to form Figure 11 the patterned photoresist layer M2.

[0176] In some embodiments, the reticle for patterning the photoresist layer M2' is as shown in Figure 2 and Figure 33 is Figure 2 an enlarged view of one of the device regions 212 in. Refer to Figure 11 and Figure 33 . The device region 212 of the reticle 200 includes a patterned region 212a and an unpatterned region 212b. The patterned region 212a corresponds to the memory region 312 of the substrate 310, and the unpatterned region 212b corresponds to the logic region 314 of the substrate 310. That is, a part of the radiation 112 (see Figure 1 ) passing through the patterned region 212a is incident on the memory region 312 of the substrate 310, and another part of the radiation 112 passing through the unpatterned region 212b is incident on the logic region 314 of the substrate 310. The main feature 215 and the auxiliary features 220 are in the patterned region 212a, while the auxiliary feature 225 is in the unpatterned region 212b. Although shown as rectangular, the main feature 215 and the auxiliary features 220 and 225 may include any variations in shape, size, and / or dimensions. In addition, the shape, size, dimensions, and positions of the main feature 215 and the auxiliary features 220 and 225 may be modified during the design and mask manufacturing processes.

[0177] Figure 33 The main feature 215 in is used to pattern Figure 10 the photoresist layer M2' in, and the profile of the patterned photoresist layer M2 corresponds to the main feature 215. The auxiliary feature 220 is disposed close to the main feature 215 for resolution enhancement. The auxiliary feature 225 is disposed in the unpatterned region 212b to reduce the radiation intensity incident on the logic region 314. Figure 33 The shapes, sizes, dimensions, and positions of the main features 210 and 215 and the auxiliary features 220 and 225 in are substantially the same as or similar to those shown in Figures 2 to 4C , and thus, the description in this regard will not be repeated hereinafter.

[0178] Refer to Figure 12 . Figure 11The hard mask layer 380, control gate film 370, dielectric film 360, floating gate layer 350, and tunneling film 320 therein are patterned to form at least one gate stack 400 over the memory region 312 of the substrate 310. The gate stack 400 includes a tunneling layer 325, a floating gate 355, a dielectric layer 365, a control gate 375, and a hard mask 385. The tunneling layer 325 is formed from Figure 11 the tunneling film 320. For example, the tunneling film 320 can be patterned to form the tunneling layer 325. The floating gate 355 is formed over the tunneling layer 325 and is formed from Figure 11 the floating gate layer 350. For example, the floating gate layer 350 can be patterned to form the floating gate 355. The dielectric layer 365 is formed over the floating gate 355. For example, the dielectric film 360 can be patterned to form the dielectric layer 365. The control gate 375 is formed over the dielectric layer 365. For example, the control gate film 370 can be patterned to form the control gate 375. The hard mask 385 is formed over the control gate 375. For example, the hard mask layer 380 can be patterned to form the hard mask 385. After patterning the hard mask layer 380, control gate film 370, dielectric film 360, floating gate layer 350, and tunneling film 320, the patterned photoresist layer M2 (see Figure 11 ) is then removed, and the removal method can be performed, for example, by solvent stripping or plasma ashing.

[0179] Reference Figure 13。A gate spacer 405 is formed on the sidewalls of the gate stack 400. In some embodiments of the gate spacer formation operation, a spacer material layer is deposited on the substrate 310. The spacer material layer can be a conformal layer that is subsequently etched back to form the gate spacer 405. In some embodiments, the spacer material layer includes multiple layers, such as a first spacer layer and a second spacer layer formed above the first spacer layer. Each of the first spacer layer and the second spacer layer is made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination thereof. By way of example and not limitation, the first spacer layer and the second spacer layer can be formed by sequentially depositing two different dielectric materials above the gate stack 400 using a process such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes. Then, an anisotropic etching process is performed on the deposited spacer layer to expose portions of the substrate 310 that are not covered by the gate stack 400. The portions of the spacer layer directly above the gate stack 400 can be removed by this anisotropic etching process. For simplicity, the portions of the spacer layer on the sidewalls of the gate stack 400 can be retained to form gate sidewall spacers, which are denoted as the gate spacer 405. In some embodiments, the first spacer layer is formed of silicon oxide having a lower dielectric constant than silicon nitride, and the second spacer layer is formed of silicon nitride having a higher resistance to subsequent etching processes than silicon oxide.

[0180] Reference Figure 14 。A protective layer 390 is formed above the memory region 312 of the substrate 310 such that the protective layer 390 covers the structures formed above the substrate 310 (i.e., the gate stack 400 and the gate spacer 405). The protective layer 390 can be made of polysilicon or other suitable materials. The protective layer 390 has a tapered profile, and the protective layer 390 tapers towards the logic region 314 of the substrate 310. The protective layer 390 exposes the logic region 314 such that the protective layer 390 exposes portions of the patterned mask layer 330 formed above the logic region 314.

[0181] Reference Figure 15 。Then, the patterned liner layer 320 and the patterned mask layer 320 are removed (see Figure 14) to expose the logic region 314 of the exposure substrate 310. Additionally, the isolation feature 340 is etched back. A dielectric layer 410' is conformally formed over the protective layer 390 and the logic region 314 of the substrate 310. In some embodiments, the dielectric layer 410' may include silicon dioxide, silicon nitride, a high-k dielectric material, or other suitable materials. In various examples, the dielectric layer 410' may be deposited by an ALD process, a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, a PVD process, or other suitable processes. For example, the dielectric layer 410' may be used to prevent damage to the substrate 310 by subsequent processing (e.g., subsequent formation of the gate structure).

[0182] A gate material 420' is conformally formed over the dielectric layer 410'. The gate material 420' may include polysilicon formed by, for example, a low pressure CVD (LPCVD) method, a CVD method, and a PVD sputtering method using a suitable silicon source material. It should be understood that other gate materials, such as metals, metal alloys, single crystal silicon, or combinations thereof.

[0183] A hard mask layer 430' is formed over the gate material 420'. In some embodiments, the hard mask layer 430' may be made of silicon nitride or other suitable materials. Subsequently, another photoresist layer M3' is formed over the gate material 420'.

[0184] Reference Figure 16 . A patterned photoresist layer M3 is formed over the logic region 314 of the substrate 310, and the memory region 312 of the substrate 310 is exposed. For example, the patterned photoresist layer M3 is formed by a combination of spin coating, exposure, and development processes. Specifically, a patterning process is performed using a photomask to remove at least a portion of the photoresist layer M3', thereby forming the patterned photoresist layer M3, as Figure 16 shown. That is, the patterned photoresist layer M3 is formed over the logic region 314 of the substrate 310 and not over the memory region 312 of the substrate 310.

[0185] For example, Figure 15 the structure may be disposed on Figure 1 the wafer stage 120, and the photomask is disposed on the main photomask holder 130. The light source 110 then provides radiation 112 to the photomask to expose the photoresist layer M3'. Subsequently, the exposed photoresist layer M3' is baked, developed, and hard baked to form Figure 16 the patterned photoresist layer M3.

[0186] In some embodiments, the photomask used to pattern the photoresist layer M3' may be shown in Figure 34A ​Figure 34A A top view of a reticle 200' similar to the reticle 200 in accordance with the present disclosure, and Figure 1 is an enlarged view of one of the device regions 212 in Figure 34B is Figure 34A one of the device regions 212 in Figure 34A The difference between the reticle 200' in Figure 2 and the reticle 200 in Figure 34A relates to the positions of the patterned regions and the non-patterned regions. In Figure 1 , the device region 212' of the reticle 200' includes a patterned region 212a' and a non-patterned region 212b'. The patterned region 212a' corresponds to the logic region 314 of the substrate 310, and the non-patterned region 212b' corresponds to the memory region 312 of the substrate 310. That is, a part of the radiation 112 (see Figure 1 ) passing through the patterned region 212a' is incident on the logic region 314 of the substrate 310, and another part of the radiation 112 passing through the non-patterned region 212b' is incident on the memory region 312 of the substrate 310. The main feature 215 and the auxiliary feature 220 are in the patterned region 212a', and the auxiliary feature 225 is in the non-patterned region 212b'. In this case, the main feature 215 can be used to pattern a gate electrode or other components in the logic region of the memory device, and the auxiliary feature 220 is disposed close to the main feature 215 for resolution enhancement. Although shown as rectangular, the main feature 215 and the auxiliary features 220 and 225 can include any variations in shape, size, and / or dimensions. In addition, the shape, size, dimensions, and positions of the main feature 215 and the auxiliary features 220 and 225 can be modified during the design and mask manufacturing process. For example, the number of the auxiliary features 225 is greater than the number of the main feature 215. In addition, the total area occupied by all of the auxiliary features 225 is greater than the total area occupied by the main features 210 and 215.

[0187] Refer to Figure 16 and Figure 34B . Figure 34B The main feature 215 in Figure 15 is used to pattern the photoresist layer M3' of Figure 15 , and the profile of the patterned photoresist layer M3 corresponds to the main feature 215. The auxiliary feature 220 is disposed close to the main feature 215 for resolution enhancement. The auxiliary feature 225 is disposed in the non-patterned region 212b' to reduce the intensity of the radiation incident on the logic region 314. Figure 34A and Figure 34B The shapes, sizes, dimensions, and positions of the main features 210 and 215 and the auxiliary features 220 and 225 in Figures 2 to 4C are substantially the same as or similar to those shown in Figures 2 to 4C , and thus, the description in this regard will not be repeated hereinafter.

[0188] Refer toFigure 17 。 Figure 16 The hard mask layer 430' is patterned into the hard mask layer 430, Figure 16 the gate material 420' is patterned into the gate structure 420, and Figure 16 the dielectric layer 410' is patterned into the gate dielectric layer 410. After patterning of the hard mask layer 430', for example, the patterned photoresist layer M3 (see Figure 16 ) is removed by solvent stripping or plasma ashing. Subsequently, implantation is performed to introduce impurities (e.g., n-type dopants such as arsenic and / or phosphorus or p-type dopants such as boron and / or boron difluoride) into the logic region 314 of the substrate 310. Thus, lightly doped source and drain (LDD) regions 440 are formed in the logic region 314 of the substrate 310 and on opposite sides of the gate structure 420.

[0189] Subsequently, gate spacers 450 are formed on the sidewalls of the gate structure 420. In some embodiments of the gate spacer forming operation, a spacer material layer is deposited on the substrate 310. The spacer material layer can be a conformal layer that is subsequently etched back to form the gate spacers 450. In some embodiments, the spacer material layer includes multiple layers, such as a first spacer layer 452 and a second spacer layer 454 formed above the first spacer layer 452. Each of the first spacer layer 452 and the second spacer layer 454 is made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination thereof. By way of example and not limitation, the first spacer layer 452 and the second spacer layer 454 can be formed by sequentially depositing two different dielectric materials above the gate structure 420 using a process such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes. Then, an anisotropic etching process is performed on the deposited spacer layer to expose portions of the substrate 310 not covered by the gate structure 420 and the protective layer 390. The portion of the spacer layer directly above the gate structure 420 can be removed by this anisotropic etching process. For simplicity, the portion of the spacer layer on the sidewalls of the gate structure 420 can be retained to form a gate sidewall spacer layer, which is denoted as the gate spacer layer 450. In some embodiments, the first spacer layer 452 is formed of silicon oxide having a lower dielectric constant than silicon nitride, and the second spacer layer 454 is formed of silicon nitride having a higher etch resistance to subsequent etching processes than silicon oxide.

[0190] Reference Figure 18 . The protective layer 390 (see Figure 17) It is removed by performing, for example, an etching process. Subsequently, source / drain features 460 are formed on opposite sides of the gate stack 400, and source / drain features 465 are formed on opposite sides of the gate structure 420. In some embodiments, the source / drain features 460 and 465 are formed by ion implantation, diffusion techniques, or other suitable techniques. For example, ion implantation using dopants can be performed to form the source / drain features 460 and 465 in the substrate 310. In some embodiments, the source / drain features 460 and / or 465 are N-type doped regions, and the dopants implanted in the source / drain features 460 and / or 465 can be arsenic, phosphorus, or other suitable materials. In some other embodiments, the source / drain features 460 and / or 465 are P-type doped regions, and the dopants implanted into the source / drain features 460 and / or 465 can be boron, boron difluoride, or other suitable materials.

[0191] Subsequently, a plurality of metal alloy layers 470 are respectively formed over the source / drain features 460 and 465. For example, a metal layer is formed over the source / drain features 460 and 465. Then an annealing process is performed on the metal layer to form the metal alloy layer 470. If the source / drain features 460 and 465 are made of silicon, the annealing process is also referred to as a silicidation process. The silicidation process converts the surface portions of the source / drain features 460 and 465 into silicide contacts (i.e., the metal alloy layer 470 in this case). The silicidation process involves the deposition of a metal material that undergoes a silicidation reaction with silicon (Si). To form silicide contacts on the source / drain features 460 and 465, a metal layer is blanket-deposited on the exposed surfaces of the source / drain features 460 and 465. After heating the wafer to a temperature at which the metal reacts with the silicon of the source / drain features 460 and 465 to form contacts, the unreacted metal is removed. The silicide contacts remain over the source / drain features 460 and 465, while the unreacted metal is removed from other regions. In some embodiments, the metal alloy layer 470 can be made of NiSi or other suitable materials.

[0192] Reference Figure 19 . In Figure 18 An interlayer dielectric (ILD) layer 480 is formed on the structure of . In some embodiments, the ILD layer 480 is formed by chemical vapor deposition (CVD), high-density plasma CVD, spin-on, sputtering, or other suitable methods. In some embodiments, the ILD layer 480 comprises silicon oxide. In some other embodiments, the ILD layer 480 can comprise silicon oxynitride, silicon nitride, or a low-k material.

[0193] In some embodiments, before forming the ILD layer 480, a contact etch stop layer (CESL) is conformally formed over the structure of Figure 18 In some embodiments, the CESL can be one or more stress layers. In some embodiments, the CESL has tensile stress and is formed of Si 3 N 4 formed. In some other embodiments, the CESL comprises a material such as oxynitride. In some other embodiments, the CESL can have a composite structure including multiple layers, such as a silicon nitride layer overlying a silicon oxide layer. Plasma enhanced CVD (PECVD) can be used to form the CESL. However, other suitable methods, such as low pressure CVD (LPCVD), atomic layer deposition (ALD), and the like, can also be used.

[0194] Subsequently, a chemical mechanical polish (CMP) process is performed to planarize the top surface of the ILD layer 480 (and the CESL) with the top surface of the control gate 375 and the top surface of the gate structure 420. In this way, at least one memory cell 12 and at least one logic transistor 16 are formed. The memory cell 12 includes a floating gate 355, a control gate 375 over the floating gate 355, a dielectric layer 365 between the floating gate 355 and the control gate 375, and source / drain regions 460 on opposite sides of the floating gate 355. The logic transistor 16 includes a gate structure 420 and source / drain regions 465 on opposite sides of the gate structure 420.

[0195] Optionally, a replacement gate (RPG) process scheme is adopted. In the RPG process scheme, a dummy polysilicon gate (e.g., the gate structure 420 in this case) is formed in advance and is subsequently replaced by a metal gate. In some embodiments, the dummy gate structure 420 is removed to form an opening having the gate spacer 450 as its sidewall. Subsequently, a metal gate structure is formed in the opening.

[0196] Refer to Figure 20 . A plurality of contacts 490 are formed over the memory cell 12 and the logic transistor 16. For example, a plurality of openings are formed in the ILD 480, and the openings are filled with a conductive material. The excess conductive material is removed to form the contacts 490. The contacts 490 can be made of tungsten, aluminum, copper, or other suitable materials. The contacts 490 are in contact with the metal alloy layer 470, respectively.

[0197] Figures 21 to 32 FIG. illustrates a method of fabricating a (flash) memory device at different stages according to some embodiments. It should be understood that for additional embodiments of this method, additional operations may be provided before, during, and after the Figures 21 to 32 process shown, and some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged. In the following embodiments, the same or similar configurations, materials, processes, and / or operations as those Figures 5 to 20 described may be employed, and the detailed descriptions may be omitted.

[0198] After forming the structure as shown in Figure 10 , a patterning process is performed using a mask to remove at least a portion of the photoresist layer M2′, thereby forming a patterned photoresist layer M2a, as shown in Figure 21 . In some embodiments, the mask used for patterning the photoresist layer M2′ may be shown in Figure 2 and Figure 33 . Since the details of the masks described above in Figure 2 and Figure 33 are provided, the description in this regard will not be repeated hereinafter.

[0199] For example, Figure 10 the structure of Figure 1 may be disposed on the wafer stage 120 of Figure 21 , and the mask is disposed on the main mask holder 130. The light source 110 then provides radiation 112 to the mask to expose the photoresist layer M2′. Subsequently, the exposed photoresist layer M2′ is baked, developed, and hard baked to form the Figure 21 patterned photoresist layer M2a.

[0200] Refer to Figure 22 . Figure 21 The hard mask layer 380, control gate film 370, and dielectric film 360 in Figure 21 are patterned to form a hard mask 385, control gate 375, and dielectric layer 365, respectively. After patterning the hard mask layer 380, control gate film 370, and dielectric film 360, the patterned photoresist layer M2a (see Figure 21 ) is subsequently removed, and the removal method may be performed, for example, by solvent stripping or plasma ashing.

[0201] Refer to Figure 23 . Gate spacers 405 are formed on the sidewalls of the hard mask 385, control gate 375, and dielectric layer 365. The details of the material and manufacturing process of the gate spacers 405 are similar to those of the gate spacers 405 in Figure 13 , and for the sake of brevity, these details will not be repeated here.

[0202] Subsequently, Figure 22The floating gate layer 350 and the tunneling film 320 therein are patterned to form a floating gate 355 and a tunneling layer 325, respectively. Accordingly, the tunneling layer 325, the floating gate 355, the dielectric layer 365, the control gate 375, and the hard mask 385 are referred to as a gate stack 500. Subsequently, a spacer structure 510 is formed on the sidewalls of the gate stack 500. Details regarding the material and manufacturing process of the spacer structure 510 are similar to those of the gate spacer 405 in Figure 13 and thus, for the sake of brevity, these details are not repeated herein.

[0203] Refer to Figure 24 and Figure 25 . Another patterned photoresist layer M4 having at least one opening O1 is formed over the substrate 310, and the opening O1 exposes the region between the two in the gate stack 400. For example, the patterned photoresist layer M4 is formed by a combination of spin coating, exposure, and development processes. Specifically, a photoresist layer M4' is formed over the structure of Figure 23 , and a patterning process is performed using a mask to remove at least a portion of the photoresist layer M4' to form the patterned photoresist layer M4' as shown in Figure 25 .

[0204] In some embodiments, masks for patterning the photoresist layer M4' may be shown in Figure 2 and Figure 33 . For example, Figure 33 the main feature 215 therein corresponds to the opening O1 of the patterned photoresist layer M4. Since the details of the masks in Figure 2 and Figure 33 are described above, the description in this regard will not be repeated hereinafter.

[0205] For example, Figure 24 the structure of Figure 1 may be disposed on the wafer stage 120 of Figure 25 , and the mask is disposed on the main mask holder 130. The light source 110 then provides radiation 112 to the mask to expose the photoresist layer M4'. Subsequently, the exposed photoresist layer M4' is baked, developed, and hard baked to form the patterned photoresist layer M4 of

[0206] Refer to Figure 26 . At least one source region 520 is formed between two adjacent gate stacks 400. For example, ions are implanted into the region exposed by the opening O1 to form the source region 520. Subsequently, a common source (CS) dielectric layer 525 is formed over the source region 520. The CS dielectric layer 525 may be a dielectric isolation structure and may be formed by oxidizing the substrate 310, other suitable processes, or a combination thereof.

[0207] Refer toFigure 27 。Then, the patterned photoresist layer M4 (see Figure 26 ) is removed, and the removal method can be performed by, for example, solvent stripping or plasma ashing. A conductive material is deposited over the substrate 310, and the conductive material is patterned or etched back to form a conductive layer 530'. Subsequently, a hard mask layer 540' is formed over the conductive layer 530'. In some embodiments, the conductive layer 530' can be made of polysilicon or other suitable materials. In some embodiments, the hard mask layer 540' includes a SiN layer or other suitable materials.

[0208] Refer to Figure 28 and Figure 29 . Another patterned photoresist layer M5 is formed over the gate stack 500. For example, the patterned photoresist layer M5 is formed by a combination of spin coating, exposure, and development processes. Specifically, a photoresist layer M5' is formed over the structure of Figure 27 , and a patterning process is performed using a photomask to remove at least a portion of the photoresist layer M5' to form the patterned photoresist layer M5, as shown in Figure 29 . In some embodiments, the photomask for patterning the photoresist layer M5' can be shown in Figure 2 and Figure 33 . Since the details of the photomasks in Figure 2 and Figure 33 are described above, the description in this regard will not be repeated hereinafter. For example, Figure 28 the structure can be disposed on the wafer stage 120 of Figure 1 , and the photomask is disposed on the main photomask holder 130. The light source 110 then provides radiation 112 to the photomask to expose the photoresist layer M5'. Then, the exposed photoresist layer M5' is baked, developed, and hard baked to form Figure 29 the patterned photoresist layer M5. That is, the patterned photoresist layer M5 is formed over the memory region 312 of the substrate 310 and not over the logic region 314 of the substrate 310.

[0209] Refer to Figure 30 . An etching process is formed to pattern Figure 29 the hard mask layer 540' and the conductive layer 530' in Figure 29 . The hard mask layer 540' in Figure 29 is patterned by using the patterned photoresist layer M5 as an etching mask to form the hard mask 540, and then the conductive layer 530' is patterned by using the hard mask 540 as an etching mask to form the erase gate 532 and the select gate 534. In some embodiments, the erase gate 532 and the select gate 524 can be made of polysilicon or other suitable materials.

[0210] Refer to Figure 31。A protective layer 390 is formed over the memory region 312 of the substrate 310 such that the protective layer 390 covers the structures formed over the substrate 310 (i.e., the gate stack 500 and the gate spacers 405). Details regarding the material and manufacturing process of the protective layer 390 are similar to those of the protective layer 390 in Figure 14 and thus are not repeated here for the sake of brevity.

[0211] Next, the patterned liner layer 320 and the patterned mask layer 320 (see Figure 30 ) are removed to expose the logic region 314 of the substrate 310. Subsequently, a gate structure 420, a hard mask layer 430, a lightly doped drain (LDD) region 440, and gate spacers 450 are formed over the logic region 314 of the substrate 310. Details regarding the material and manufacturing process of the gate structure 420, the hard mask layer 430, the lightly doped region 440, and the gate spacers 450 are respectively similar to those of the gate structure 420, the hard mask layer 430, the lightly doped region 440, and the gate spacers 450 in Figure 17 and thus these details are not repeated here for the sake of brevity.

[0212] Refer to Figure 32 . Similar to the process shown in Figures 18 to 20 , the protective layer 390 is removed (see Figure 31 ). Source / drain features 460 and 465 are formed in the substrate 310. A metal alloy layer 470 is formed over the source / drain features 460 and 465. An interlayer dielectric (ILD) layer 480 (and CESL) is formed over the substrate 310, and a planarization process is performed to level the top surface of the ILD layer 480 with the top surface of the control gate 375 and the top surface of the gate structure 420. Optionally, a replacement gate (RPG) process scheme is employed for the gate structure 420. Additionally, a plurality of contacts 490 are formed over the memory cells 14 and the logic transistors 16.

[0213] Thus, at least one memory cell 14 and at least one logic transistor 16 are formed. The memory cell 14 includes two floating gates 355, two control gates 375, two dielectric layers 365, an erase gate 532, two select gates 534, a source region 520, and two drain regions 460. The logic transistor 16 includes a gate structure 420 and source / drain regions 465 on opposite sides of the gate structure 420.

[0214] Figure 35 is a flowchart of a method 600 for modifying an IC design layout before mask manufacturing according to various aspects of the present disclosure. In some embodiments, the method 600 can be performed inFigure 37 implemented in mask data preparation 3732 of the mask chamber 3730 shown in. In addition, Figure 35 The method 600 in is an overview, and the details associated with each operation in the method 600 will be described in connection with the subsequent figures in this disclosure.

[0215] The method 600 includes an operation 612 of receiving an IC design layout. The IC design layout is presented in one or more data files having geometric pattern information. In some embodiments, the IC design layout is expressed in the GDS file format. In alternative embodiments, the IC design layout can be transferred between components in an IC manufacturing system in an alternative file format such as DFII, CIF, OASIS, and / or any other suitable file type. The IC design layout includes various geometric patterns representing integrated circuit features. For example, the IC design layout may include a plurality of primary features (e.g., Figures 3A to 3D , Figure 33 , and Figure 34B the primary feature 215 in).

[0216] The method 600 further includes an operation 614 of inserting a plurality of first auxiliary features to form a first modified IC design layout. The first auxiliary features (e.g., Figures 3A to 3D , Figure 33 , and Figure 34B the auxiliary feature 220 of) are used to modify the shape of the primary features to compensate for diffraction and / or other process effects in the lithography process, so that the shape of the primary features formed in the final integrated circuit more closely matches the shape of the primary features in the IC design layout.

[0217] The method 600 further includes an operation 616 of determining non-patterned regions adjacent to the primary features and the first auxiliary features. In some embodiments, the non-patterned regions correspond to Figure 2 the non-patterned region 212b of or Figure 34A the non-patterned region 212b' of. In some embodiments, after inserting the first auxiliary features, the total area of the primary features (i.e., device features and scribe features) and the first auxiliary features is calculated, and the percentage of the total area occupied by the mask exposure field area is determined. In some embodiments, the percentage is less than 50%, for example, about 20% to about 30%. In these cases, most of the radiation will pass through the reticle and heat the lens system (e.g., Figure 1 the lens system 150 in).

[0218] The method 600 further includes an operation 618 of inserting a plurality of second auxiliary features in the non-patterned regions to form a second modified IC design layout. The second auxiliary features (e.g., Figures 3A to 3D , Figure 33 , and Figure 34BThe auxiliary feature 225) is used to block the non-patterned area, thereby improving the heating problem.

[0219] Figure 36 is a block diagram of an IC device design system 3600 according to some embodiments of the present disclosure. According to some embodiments, one or more operations of the method 600 discussed above with respect to Figure 35 can be implemented using the IC device design system 3600.

[0220] In some embodiments, the IC device design system 3600 is a computing device including a processor 3602 and a non-transitory computer-readable storage medium 3604. The non-transitory computer-readable storage medium 3604 encodes, among other things, computer program code, that is, a set of executable instructions 3606. Execution of the instructions 3606 by the hardware processor 3602 represents (at least in part) the IC device design system, and the implementation of the IC device design system is part or all of the method 600 discussed above with respect to Figure 35 (hereinafter referred to as the mentioned processes and / or methods).

[0221] The processor 3602 is electrically coupled to the non-transitory computer-readable storage medium 3604 via a bus 3608. The processor 3602 is also electrically coupled to an I / O interface 3610 via the bus 3608. A network interface 3612 is also electrically connected to the processor 3602 via the bus 3608. The network interface 3612 is connected to a network 3614, such that the processor 3602 and the non-transitory computer-readable storage medium 3604 can be connected to external components via the network 3614. The processor 3602 is configured to execute the instructions 3606 encoded in the non-transitory computer-readable storage medium 3604, so that the IC device design system 3600 can be used to execute part or all of the mentioned processes and / or methods. In one or more embodiments, the processor 3602 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0222] In one or more embodiments, the non-transitory computer-readable storage medium 3604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the non-transitory computer-readable storage medium 3604 includes semiconductor or solid state memories, magnetic tapes, removable computer disks, random access memory (RAM), read-only memory (ROM), hard disks, and / or optical disks. In one or more embodiments using optical disks, the non-transitory computer-readable storage medium 3604 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0223] In one or more embodiments, the non-transitory computer-readable storage instructions 3606 are such that the IC device design system 3600 can be used to execute part or all of the processes and / or methods mentioned. In one or more embodiments, the non-transitory computer-readable storage medium 3604 also stores information that facilitates part or all of the processes and / or methods mentioned. In various embodiments, the non-transitory computer-readable storage medium 3604 stores at least one of the IC layout design diagrams 3620 or at least one of the design specifications 3622 or a combination thereof, each design specification 3622 as discussed above with respect to Figure 35 discussed.

[0224] The IC device design system 3600 includes an I / O interface 3610. The I / O interface 3610 is coupled to an external circuit system. In various embodiments, the I / O interface 3610 includes one or a combination of the following: a keyboard, a keypad, a mouse, a trackball, a track pad, a display, a touch screen, and / or cursor direction keys for communicating information and commands to and / or from the processor 3602.

[0225] The IC device design system 3600 also includes a network interface 3612 coupled to the processor 3602. The network interface 3612 allows the IC device design system 3600 to communicate with a network 3614 to which one or more other computer systems are connected. The network interface 3612 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a part or all of the processes and / or methods mentioned are implemented in two or more systems 3600.

[0226] The IC device design system 3600 is configured to receive information via the I / O interface 3610. The information received via the I / O interface 3610 includes at least one design rule instruction, at least one set of criteria, at least one design rule, at least one DRM, and / or one or a combination of other parameters for processing by the processor 3602. This information is transmitted to the processor 3602 via the bus 3608. The IC device design system 3600 is configured to send and / or receive information related to the user interface via the I / O interface 3610.

[0227] The IC device design system 3600 also includes one or more manufacturing tools 3624 coupled to the network 3614. The manufacturing tools 3624 are used to manufacture the IC layout designed by the IC device design system 3600. The manufacturing tools 3624 include deposition tools (e.g., chemical vapor deposition (CVD) equipment, physical vapor deposition (PVD) equipment), etching tools (e.g., dry etching devices, wet etching equipment), planarization tools (e.g., CMP equipment), or other tools for manufacturing IC devices, including the IC layout designed by the IC device design system 3600.

[0228] In some embodiments, a part or all of the processes and / or methods mentioned are implemented as a stand-alone software application for execution by the processor. In some embodiments, a part or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, a part or all of the processes and / or methods mentioned are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, the IC layout is generated using tools such as those available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0229] In some embodiments, the process is implemented as the functionality of a program stored in a non - transitory computer - readable recording medium. Examples of non - transitory computer - readable recording media include, but are not limited to, external / removable and / or internal / embedded memories or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic discs, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, and the like.

[0230] By one or more operations of method 600 that can be used to implement Figure 35 IC device design system 3600 and non - transitory computer - readable storage media (e.g., non - transitory computer - readable storage media 3604) enable the benefits discussed above with respect to Figure 35 method 600.

[0231] Figure 37 FIG. 3700 is a block diagram of an IC manufacturing system 3700 and its associated IC manufacturing process according to some embodiments of the present disclosure. In some embodiments, based on a layout design, at least one of the following is manufactured using IC manufacturing system 3700: (A) one or more masks or (B) at least one component in a semiconductor IC layer.

[0232] In Figure 37 , IC manufacturing system 3700 includes entities such as design house 3720, mask house 3730, and IC manufacturer / fab 3750, which interact with each other in the design, development, and manufacturing cycles and / or in services related to manufacturing IC device 3760 (e.g., Figure 20 and / or Figure 31 devices). The entities in system 3700 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of design house 3720, mask house 3730, and IC fab 3750 are owned by a single larger company. In some embodiments, two or more of design house 3720, mask house 3730, and IC fab 3750 co - exist in a common facility and use common resources.

[0233] Design house (or design team) 3720 generates an IC design layout (or design) 3722 based on Figure 35 method 600 of Figures 2 to 4C and Figures 33 to 34BA discussion is carried out. The IC design layout 3722 includes various geometric patterns that correspond to metal, oxide, or semiconductor layer patterns of various components that make up the IC device 3760 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 3722 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnection, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and disposed in various material layers on the semiconductor substrate. The design house 3720 implements an appropriate design process, including Figure 35 method 600, and discussed above in connection with Figures 2 to 4C and Figures 33 to 34B to form the IC design layout 3722. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 3722 is displayed in one or more data files having information of geometric patterns. For example, the IC design layout 3722 can be expressed in GDSII file format or DFII file format.

[0234] The mask room 3730 includes data preparation 3732 and mask manufacturing 3744. The mask room 3730 uses the IC design layout 3722 to manufacture one or more masks 3745 (corresponding to Figure 2 and the photomasks 200 and / or 200' in FIG. 34) for manufacturing the various layers of the IC device 3760 according to the IC design layout 3722. The mask room 3730 performs mask data preparation 3732, in which the IC design layout 3722 is translated into a representative data file ("representative data file, RDF"). The mask data preparation 3732 provides the RDF to the mask manufacturing 3744. The mask manufacturing 3744 includes a mask writer. The mask writer converts the RDF into an image on a substrate such as a mask (master mask) 3745 or a semiconductor wafer 3753. The design layout 3722 is manipulated by the mask data preparation 3732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 3750. In Figure 37 , the mask data preparation 3732 and the mask manufacturing 3744 are illustrated as separate elements. In some embodiments, the mask data preparation 3732 and the mask manufacturing 3744 are collectively referred to as mask data preparation.

[0235] In some embodiments, mask data preparation 3732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may result from diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 3722. In some embodiments, mask data preparation 3732 includes further resolution enhancement technology (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0236] In some embodiments, mask data preparation 3732 includes a mask rule checker (MRC) that examines the IC design layout 3722, the mask rule checker having undergone a process in OPC that applies a set of mask generation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in the semiconductor manufacturing process, and the like. In some embodiments, the MRC modifies the IC design layout 3722 to compensate for limitations during mask manufacturing 3744, which may undo portions of the modifications performed by OPC in order to meet the mask generation rules.

[0237] In some embodiments, mask data preparation 3732 includes lithography process checking (LPC), which simulates the process to be implemented by the IC foundry 3750 to fabricate the IC device 3760. LPC simulates the process based on the IC design layout 3722 to produce a simulated fabricated device, such as the IC device 3760. The process parameters in the LPC simulation may include parameters associated with the various processes of the IC manufacturing cycle, parameters associated with the tools used to fabricate the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated fabricated device has been generated by LPC, if the shape of the simulated device is not sufficiently close to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 3722.

[0238] It should be understood that the above description of mask data preparation 3732 has been simplified for clarity purposes. In some embodiments, data preparation 3732 includes additional features, such as a logic operation (LOP) to modify the IC design layout 3722 according to manufacturing rules. Additionally, the processes applied to the IC design layout 3722 during data preparation 3732 can be performed in a variety of different orders.

[0239] After mask data preparation 3732 and during mask manufacturing 3744, the mask 3745 or group of masks 3745 is fabricated based on the modified IC design layout 3722. In some embodiments, mask manufacturing 3744 includes performing one or more lithography exposures based on the IC design layout 3722. In some embodiments, an electron-beam (e-beam) or multiple electron-beams mechanism is used to pattern the mask (reticle or master reticle) 3745 based on the modified IC design layout 3722. The mask 3745 can be formed using various techniques. In some embodiments, the mask 3745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 3745 includes a transparent substrate (e.g., fused silica) of the binary mask and an opaque material (e.g., chromium) coated in the opaque regions. In another example, the mask 3745 is formed using a phase-shift technique. In the phase-shift mask (PSM) version of the mask 3745, various features in the pattern formed on the phase-shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask(s) produced by mask manufacturing 3744 are used in a variety of processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in the semiconductor wafer 3753, in an etching process to form various etched regions in the semiconductor wafer 3753, and / or in other suitable processes.

[0240] IC wafer fab 3750 includes wafer fabrication 3752. IC wafer fab 3750 is an IC manufacturing operation that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 3750 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) fabrication of a variety of IC products, while a second manufacturing facility may provide back-end-of-line (BEOL) fabrication for interconnecting and packaging the IC products, and a third manufacturing facility may provide other services for the foundry business.

[0241] IC wafer fab 3750 uses mask 3745 fabricated by mask chamber 3730 to fabricate IC device 3760. Thus, IC wafer fab 3750 uses IC design layout 3722 at least indirectly to fabricate IC device 3760. In some embodiments, wafer 3753 is fabricated by IC wafer fab 3750 using mask 3745 to form IC device 3760. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 3722. Wafer 3753 includes a silicon substrate or other suitable substrate having material layers formed thereon. Wafer 3753 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

[0242] Based on the above discussion, it can be seen that the present disclosure has advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages need to be disclosed herein, and no specific advantage is required for all embodiments. One advantage is that the risk of image distortion caused by the heating problem of the lens can be reduced due to the addition of auxiliary features in the non-patterned area of the photomask. Another advantage is that the addition of auxiliary features in the non-patterned area of the photomask can be fabricated together with the main features without increasing the manufacturing cost of the photomask. And another advantage is that since the auxiliary features in the non-patterned area are far from the main features, the presence of the auxiliary features in the non-patterned area does not interfere with the imaging of the main features on the wafer.

[0243] According to some embodiments, a photomask includes a plurality of device features, a first auxiliary feature, and a second auxiliary feature. The device features are in the patterned area of the device region. The first auxiliary feature is in the patterned area and adjacent to the device features. The first auxiliary feature is used to correct the optical proximity effect in the optical lithography process. The second auxiliary feature is in the non-patterned area of the device region. The second auxiliary feature is a sub-resolution correction feature, and a first distance between the second auxiliary feature and one of the device features closest to the second auxiliary feature is greater than a second distance between adjacent ones of the device features.

[0244] According to some embodiments, the photomask further includes scribe features surrounding the device features, the first auxiliary features, and the second auxiliary features. The scribe features define the device regions. According to some embodiments, a third distance between the first auxiliary feature and one of the device features closest to the first auxiliary feature is less than a first distance between the second auxiliary feature and one of the device features closest to the second auxiliary feature. According to some embodiments, the photomask further includes a third auxiliary feature between the second auxiliary feature and the one of the device features closest to the second auxiliary feature. According to some embodiments, the third distance between the first auxiliary feature and one of the device features closest to the first auxiliary feature is less than a fourth distance between the third auxiliary feature and one of the device features closest to the third auxiliary feature. According to some embodiments, the photomask further includes a third auxiliary feature connecting the second auxiliary feature and the one of the device features closest to the second auxiliary feature. According to some embodiments, the patterned region is used to expose a portion of the photoresist layer over the memory region of the substrate, and the non-patterned region is used to expose another portion of the photoresist layer over the logic region of the substrate. According to some embodiments, the patterned region is used to expose a portion of the photoresist layer over the logic region of the substrate, and the non-patterned region is used to expose another portion of the photoresist layer over the memory region of the substrate.

[0245] According to some embodiments, a method includes forming a floating gate material over a memory region of a substrate. A dielectric film, a control gate film, and a hard mask layer are deposited over the floating gate material and the logic region of the substrate. After depositing the hard mask layer, a photoresist layer is deposited over the memory region and the logic region of the substrate. The photoresist layer is patterned using a photomask to form a patterned photoresist layer over the memory region of the substrate. The photomask includes a main feature and two first auxiliary features. The main feature defines the patterned photoresist layer, and a portion of the radiation used to expose the photoresist layer is incident on a portion of the photoresist layer over the logic region of the substrate through the space between the two first auxiliary features. The hard mask layer is patterned using the patterned photoresist layer as a first etch mask to form a hard mask over the memory region of the substrate. The control gate film, the dielectric film, and the floating gate material are patterned using the hard mask as a second etch mask to form a gate stack.

[0246] According to some embodiments, the distance between the main feature and any one of the first auxiliary features is greater than about 1 micron and less than the length of the exposure field of the photomask. According to some embodiments, the first auxiliary feature is a sub-resolution assist feature. According to some embodiments, the patterned photoresist layer includes removing a portion of the photoresist layer above the logic region of the substrate. According to some embodiments, the patterned photoresist layer results in no remaining photoresist layer above the logic region of the substrate. According to some embodiments, the photomask further includes a second auxiliary feature for correcting optical proximity effects in an optical lithography process for patterning the photoresist layer.

[0247] According to some embodiments, a method includes forming a gate stack including a floating gate and a control gate above a memory region of a substrate. Depositing a protective layer covering the gate stack and exposing the logic region of the substrate. After depositing the protective layer, depositing a gate material and a hard mask layer above the logic region of the substrate. After depositing the hard mask layer, depositing a photoresist layer above the memory region and the logic region of the substrate. Projecting radiation through a photomask onto the photoresist layer to expose the photoresist layer. The photomask includes a patterned region and an unpatterned region. A portion of the radiation passing through the patterned region impinges on a portion of the protective layer above the memory region of the substrate, and another portion of the radiation passing through the unpatterned region impinges on another portion of the protective layer above the logic region of the substrate. The photomask includes a plurality of device features in the patterned region and a plurality of first auxiliary features in the unpatterned region. After projecting the radiation onto the photoresist layer, developing the photoresist layer to form a patterned photoresist layer defined by the device features. Pattern the hard mask layer and the gate material by using the patterned photoresist layer as an etch mask.

[0248] According to some embodiments, the number of the first auxiliary features is greater than the number of the device features. According to some embodiments, a first area of the photomask occupied by the first auxiliary features is greater than a second area of the photomask occupied by the device features. According to some embodiments, the photomask further includes a second auxiliary feature in the patterned region. According to some embodiments, the first auxiliary feature is a sub-resolution assist feature. According to some embodiments, none of the device features are disposed in the unpatterned region of the photomask.

[0249] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be made herein without departing from the spirit and scope of the present disclosure by various changes, substitutions, and alterations.

Claims

1. A photomask, characterized in that, it comprises: a plurality of main features in a patterned area of a device area; a first auxiliary feature in the patterned area and adjacent to the plurality of main features, wherein the first auxiliary feature is used to correct an optical proximity effect in an optical lithography process; and a second auxiliary feature in an unpatterned area of the device area, wherein the second auxiliary feature is a sub-resolution correction feature, and a first distance between the second auxiliary feature and one of the plurality of main features closest to the second auxiliary feature is greater than a second distance between adjacent ones of the plurality of main features, wherein a width of one of the plurality of main features is greater than a width of the first auxiliary feature and greater than a width of the second auxiliary feature, and a distance between one of the plurality of main features and the second auxiliary feature is greater than 1 micron and less than a length of an exposure field of the photomask.

2. The photomask according to claim 1, characterized in that, it further comprises: a scribe feature surrounding the plurality of main features, the first auxiliary feature and the second auxiliary feature, wherein the scribe feature defines the device area.

3. The photomask according to claim 1, characterized in that, a third distance between the first auxiliary feature and one of the plurality of main features closest to the first auxiliary feature is less than the first distance between the second auxiliary feature and one of the plurality of main features closest to the second auxiliary feature.

4. The photomask according to claim 1, characterized in that, it further comprises a third auxiliary feature between the second auxiliary feature and one of the plurality of main features closest to the second auxiliary feature.

5. The photomask according to claim 4, characterized in that, a third distance between the first auxiliary feature and one of the plurality of main features closest to the first auxiliary feature is less than a fourth distance between the third auxiliary feature and one of the plurality of main features closest to the third auxiliary feature.

6. The photomask according to claim 1, characterized in that, it further comprises a third auxiliary feature connecting the second auxiliary feature and one of the plurality of main features closest to the second auxiliary feature.

7. The photomask according to claim 1, characterized in that, the patterned area is used to expose a part of a photoresist layer above a memory area of a substrate, and the unpatterned area is used to expose another part of the photoresist layer above a logic area of the substrate.

8. The photomask according to claim 1, characterized in that, the patterned area is used to expose a part of a photoresist layer above a logic area of a substrate, and the unpatterned area is used to expose another part of the photoresist layer above a memory area of the substrate.

9. A method of manufacturing a semiconductor device, characterized in that, it comprises: forming a floating gate material above a memory area of a substrate; depositing a dielectric film, a control gate film and a hard mask layer above the floating gate material and a logic area of the substrate; After depositing the hard mask layer, a photoresist layer is deposited over the memory region and the logic region of the substrate; The photoresist layer is patterned using a mask to form a patterned photoresist layer over the memory region of the substrate, wherein the mask includes a patterned region corresponding to the memory region of the substrate and an unpatterned region corresponding to the logic region of the substrate, wherein the mask includes a plurality of main features and a first auxiliary feature in the patterned region and two second auxiliary features in the unpatterned region, the plurality of main features defining the patterned photoresist layer, and a portion of the radiation used to expose the photoresist layer is incident on a portion of the photoresist layer over the logic region of the substrate through a space between the two second auxiliary features, wherein a width of one of the plurality of main features is greater than a width of the first auxiliary feature and greater than a width of one of the two second auxiliary features, and a distance between one of the plurality of main features and any one of the two second auxiliary features is greater than 1 micron and less than a length of an exposure field of the mask; The hard mask layer is patterned using the patterned photoresist layer as a first etch mask to form a hard mask over the memory region of the substrate; and The control gate film, the dielectric film, and the floating gate material are patterned using the hard mask as a second etch mask to form a gate stack.

10. The method according to claim 9, wherein, the distance between one of the plurality of main features and any one of the two second auxiliary features is less than 200 millimeters.

11. The method according to claim 9, wherein, the two second auxiliary features are sub-resolution assist features.

12. The method according to claim 9, wherein, patterning the photoresist layer includes removing the portion of the photoresist layer over the logic region of the substrate.

13. The method according to claim 9, wherein, the photoresist layer is patterned such that no remaining photoresist layer is left over the logic region of the substrate.

14. The method according to claim 9, wherein, the first auxiliary feature is used to correct an optical proximity effect in an optical lithography process for patterning the photoresist layer.

15. A method of manufacturing a semiconductor device, wherein, comprises: forming a gate stack including a floating gate and a control gate over a memory region of a substrate; depositing a protective layer covering the gate stack and exposing a logic region of the substrate; after depositing the protective layer, depositing a gate material and a hard mask layer over the logic region of the substrate; after depositing the hard mask layer, depositing a photoresist layer over the memory region and the logic region of the substrate; Radiate a photoresist layer through a photomask to expose the photoresist layer, where the photomask includes a patterned area and an unpatterned area. A part of the radiation passing through the patterned area is incident on a part of the protective layer above the memory area of the substrate, and another part of the radiation passing through the unpatterned area is incident on another part of the protective layer above the logic area of the substrate. The photomask includes a plurality of main features and a first auxiliary feature in the patterned area and a plurality of second auxiliary features in the unpatterned area. A width of one of the plurality of main features is greater than a width of the first auxiliary feature and greater than a width of one of the plurality of second auxiliary features. A distance between one of the plurality of main features and any one of the plurality of second auxiliary features is greater than 1 micron and less than a length of an exposure field of the photomask; After radiating the photoresist layer, develop the photoresist layer to form a patterned photoresist layer defined by the plurality of main features; and Pattern the hard mask layer and the gate material by using the patterned photoresist layer as an etching mask.

16. The method according to claim 15, wherein, a number of the plurality of second auxiliary features is greater than a number of the plurality of main features.

17. The method according to claim 15, wherein, a first area of the photomask occupied by the plurality of second auxiliary features is greater than a second area of the photomask occupied by the plurality of main features.

18. The method according to claim 15, wherein, the distance between one of the plurality of main features and any one of the plurality of second auxiliary features is less than 200 millimeters.

19. The method according to claim 15, wherein, the plurality of second auxiliary features are sub-resolution assist features.

20. The method according to claim 15, wherein, none of the plurality of main features is disposed in the unpatterned area of the photomask.

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