Power module, display device and method of supplying power

Abstract

A power module, a display device, and a method for powering are disclosed. The power module includes: a first power module that generates a first output current based on a first input voltage; a second power module that generates a second output voltage based on a second input voltage, generates a second output current based on the second output voltage, and generates the second output current when the level of the first input voltage is less than the level of a reference voltage; and a voltage controller that generates a feedback signal for adjusting at least one of the levels of the first input voltage and the second input voltage based on current information related to the current flowing through the power module.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0083110, filed with the Korean Intellectual Property Office on June 25, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure described herein relate to a power module and an electronic device including the power module, and more specifically, to a power module and an electronic device including the power module for the purpose of regulating the voltage level for maximizing the efficiency of the delivered power consumed by the system load. Background Technology

[0003] Today, electronic devices perform a wide variety of operations, resulting in a diverse range of load currents flowing through them. For example, as display resolutions and scan rates increase, displays operate at various resolutions and scan rates, thus expanding the range of load currents they cover. Consequently, power supply devices have recently been developed that apply sufficiently high voltages to electronic devices to enable them to operate at maximum load current. However, since the maximum current flowing through an electronic device is temporary and occurs only under limiting conditions, consistently applying high voltages to such situations is wasteful and inefficient. Summary of the Invention

[0004] Embodiments of this disclosure provide a power module and an electronic device including the power module, wherein the power module regulates the level of the input voltage by monitoring the amount of current flowing to the power module, such that the electronic device consumes power with maximum efficiency according to the power required by the system load.

[0005] According to an embodiment, a power module includes: a first power module that generates a first output current based on a first input voltage; a second power module that generates a second output voltage based on a second input voltage, generates a second output current based on the second output voltage, and generates the second output current when the level of the first input voltage is less than the level of a reference voltage; and a voltage controller that generates a feedback signal for adjusting at least one of the levels of the first input voltage and the second input voltage based on current information related to the current flowing through the power module.

[0006] According to an embodiment, a power supply method includes: generating a first output current based on a first input voltage; comparing the level of the first input voltage with the level of a reference voltage; generating a comparison signal based on the comparison result of comparing the level of the first input voltage with the level of the reference voltage; generating a result code corresponding to accumulated information of the comparison signal; generating a second output current based on the result code and a second input voltage; supplying power to an external device based on the first output current and the second output current; sensing at least one of the first output current and the second output current to generate current information; generating a feedback signal based on the current information for adjusting the level of at least one of the first input voltage and the second input voltage; and adjusting and outputting the level of said at least one of the first input voltage and the second input voltage based on the feedback signal.

[0007] According to an embodiment, a display device includes: a display panel for displaying an image; a power management integrated circuit for generating a first input voltage and a second input voltage; and a display driving circuit for generating gate signals on a plurality of gate lines and generating data voltages on a plurality of data lines. The display driving circuit includes: a power module for providing power required by the display panel based on at least one of the first input voltage and the second input voltage. The power module generates a first current based on the first input voltage, generates a second current based on the first input voltage and the second input voltage when a drop in the first input voltage occurs, and monitors the first current and the second current to generate a feedback signal for adjusting the level of at least one of the first current and the second input voltage based on at least one of the first current and the second current. Attached Figure Description

[0008] The above-mentioned objects and features, as well as other objects and features of this disclosure, will become clear from the detailed description of the embodiments of this disclosure with reference to the accompanying drawings.

[0009] Figure 1 This is a configuration diagram illustrating a power module and an electronic device including the power module according to exemplary embodiments of the present disclosure.

[0010] Figure 2A and Figure 2B This is a detailed diagram illustrating the configuration of a power module according to exemplary embodiments of the present disclosure.

[0011] Figure 3A and Figure 3B It is shown in detail Figure 2A and Figure 2B The diagram shows the configuration of the analog LDO regulator 1120.

[0012] Figure 4 It is shown in detail Figure 2A and Figure 2B The diagram shows the configuration of the digital LDO regulator 1220.

[0013] Figure 5 This is a timing diagram used to describe the operation of a digital LDO regulator according to an exemplary embodiment of the present disclosure.

[0014] Figure 6A and Figure 6B This is a configuration diagram illustrating a power module operating in an internally powered manner according to an exemplary embodiment of the present disclosure.

[0015] Figure 7A and Figure 7B This is a configuration diagram illustrating a power supply module operating in an external power supply manner according to an exemplary embodiment of the present disclosure.

[0016] Figure 8 This is a configuration diagram illustrating a power module operating in an internal power supply mode and an external power supply mode according to exemplary embodiments of the present disclosure.

[0017] Figure 9 This is a configuration diagram illustrating an electronic device according to another exemplary embodiment of the present disclosure.

[0018] Figure 10 It is a graph showing the load current for each scenario according to an exemplary embodiment of the present disclosure.

[0019] Figure 11 This is a graph illustrating a current sampling method according to an exemplary embodiment of the present disclosure.

[0020] Figure 12A and Figure 12B It is a graph showing how much power is reduced according to an exemplary embodiment of the present disclosure.

[0021] Figure 13 This is a configuration diagram illustrating the communication structure of an electronic device according to exemplary embodiments of the present disclosure.

[0022] Figure 14 This is a configuration diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0023] Figure 15 This is a flowchart illustrating a method of operating an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] The embodiments of this disclosure will now be described in detail and clearly to the extent that those skilled in the art will readily understand them.

[0025] Figure 1This is a configuration diagram illustrating an electronic device according to an embodiment of the present disclosure. The electronic device according to an exemplary embodiment of the present disclosure may include a power management integrated circuit (PMIC) 10, a power module 1000, and a system load 20. The electronic device according to an embodiment of the present disclosure may include various electronic devices capable of being powered (such as smartphones, tablets, wearable devices, digital cameras, televisions, displays, laptops, black boxes, and robots).

[0026] The power management integrated circuit 10 can provide various voltage levels based on a battery placed inside or outside the electronic device. According to embodiments of this disclosure, the power management integrated circuit 10 can provide a first input voltage VIN1 and a second input voltage VIN2. For example, the first input voltage VIN1 and the second input voltage VIN2 can be provided as separate voltage sources. The power management integrated circuit 10 can adjust the level of the first input voltage VIN1 based on a feedback signal FS. Therefore, the level of the first input voltage VIN1 can be increased or decreased by the feedback signal FS. However, the power management integrated circuit 10 is not limited to this, and the power management integrated circuit 10 can also adjust the level of the second input voltage VIN2.

[0027] Power module 1000 may include a first power module 1100, a second power module 1200, and a voltage controller 1300. Power module 1000 can generate an output voltage VOUT based on a first input voltage VIN1 and a second input voltage VIN2. When sufficient power is provided to system load 20 using only the first input voltage VIN1, power module 1000 can generate the output voltage VOUT using only the first input voltage VIN1. Conversely, when sufficient power cannot be provided to system load 20 using only the first input voltage VIN1 as the level of load current consumed by system load 20 increases, power module 1000 can generate the output voltage VOUT by using both the second input voltage VIN2 and the first input voltage VIN1.

[0028] Additionally, the power module 1000 can monitor the load current flowing to the system load 20. Here, the load current can be variable. For example, the power module 1000 can measure the current level based on a first input voltage VIN1 and the current level based on a second input voltage VIN2. According to embodiments of this disclosure, the power module 1000 can generate a feedback signal FS based on the measured current level. Here, the feedback signal FS can include information indicating whether to increase, decrease, or maintain the level of the first input voltage VIN1.

[0029] The first power module 1100 can generate a first output voltage VOUT1 based on a first input voltage VIN1. For example, to stably supply power, the first power module 1100 can increase, decrease, and / or invert the first input voltage VIN1. For example, the first power module 1100 can remove noise from the first input voltage VIN1. Additionally, the first power module 1100 can provide the first input voltage VIN1 to the second power module 1200. Although not explicitly stated... Figure 1 As shown, however, the first power module 1100 can provide the first output voltage VOUT1 to the second power module 1200.

[0030] According to embodiments of the present disclosure, a first power supply module 1100 can generate first current information ID1. Here, the first current information ID1 may include information relating to the current (hereinafter referred to as "first current") based on a first input voltage VIN1 and / or a first output voltage VOUT1. For example, the first current information ID1 may include the level of the first current and / or a set of values ​​obtained by sampling the first current at regular intervals (or periods). Reference will be made to... Figure 2A and Figure 2B The configuration and operation of the first power module 1100 are described in detail.

[0031] The second power module 1200 can generate a second output voltage VOUT2 based on a first input voltage VIN1 and a second input voltage VIN2. For example, when the system load 20 requires a given level or higher of power, a voltage drop may occur at the first output voltage VOUT1. In this case, to compensate for the voltage drop of the first output voltage VOUT1, the second power module 1200 can generate a second output voltage VOUT2. For example, the second power module 1200 can determine the level of the additional current based on the first input voltage VIN1, and can generate a second output voltage VOUT2 corresponding to the level of the additional current based on the second input voltage VIN2. Although not explicitly stated in... Figure 1 As shown, however, the second power module 1200 can generate a second output voltage VOUT2 based on the first output voltage VOUT1 and the second input voltage VIN2. In this case, the second power module 1200 can determine the level of the additional current based on the first output voltage VOUT1.

[0032] According to embodiments of the present disclosure, a second power supply module 1200 can generate second current information ID2. Here, the second current information ID2 may include information relating to the current (hereinafter referred to as "second current") based on a second input voltage VIN2 and / or a second output voltage VOUT2. For example, the second current information ID2 may include the level of the second current and / or a set of values ​​obtained by sampling the second current at regular intervals (or periods). (Refer to...) Figure 2A and Figure 2B The configuration and operation of the second power module 1200 are described in detail.

[0033] Voltage controller 1300 can be configured to monitor a first current and / or a second current. According to embodiments of this disclosure, voltage controller 1300 can receive first current information ID1 and / or second current information ID2 from a first power module 1100 and / or a second power module 1200. According to embodiments of this disclosure, the time period for receiving the first current information ID1 and the second current information ID2, as well as the period for receiving the first current information ID1 and the second current information ID2, can be determined based on a user request or manufacturer settings. Furthermore, the time period for receiving the first current information ID1 and the second current information ID2, as well as the period for receiving the first current information ID1 and the second current information ID2, may not be fixed and can be determined for real-time adjustment. For example, when the first current information ID1 and the second current information ID2 consist only of analog current signals, voltage controller 1300 can sample the first current and the second current at regular intervals (or periodically).

[0034] Additionally, the voltage controller 1300 can generate a feedback signal FS based on at least one of the first current information ID1 and the second current information ID2. For example, the voltage controller 1300 can calculate the level of the first input voltage VIN1 based on at least one of the first current information ID1 and the second current information ID2 to correspond to the power required by the system load 20. Here, the level of the first input voltage VIN1 according to an embodiment of the present disclosure will be described with reference to Equations 1 to 4 below.

[0035] [Equation 1]

[0036] IL = I1 + I2

[0037] [Equation 2]

[0038] P = I1 × VIN1 + I2 × VIN2

[0039] [Equation 3]

[0040] VIN1≤VIN2

[0041] [Equation 4]

[0042] Pmin=IL×VIN1

[0043] Referring to Equations 1 through 4, “IL” is defined as the level of the total current flowing to system load 20. “I1” is defined as the level of the current supplied by the first power module 1100 to system load 20, and “I2” is defined as the level of the current supplied by the second power module 1200 to system load 20. “P” is defined as the total power consumed by system load 20. “Pmin” is defined as the minimum value of the total power consumed by system load 20.

[0044] Referring to Equations 1 and 2, the total current flowing to system load 20 is determined by the sum of I1 and I2, and the total power consumed by system load 20 is determined by the product of I1 and the first input voltage VIN1 and the product of I2 and the second input voltage VIN2. According to an embodiment of this disclosure, in Equation 3, it is assumed that the level of the first input voltage VIN1 is less than or equal to the level of the second input voltage VIN2. However, this disclosure is not limited thereto. For example, the level of the first input voltage VIN1 may be greater than the level of the second input voltage VIN2. For convenience, a description will be given assuming that Equation 3 is valid. When the level of the first input voltage VIN1 is always less than or equal to the level of the second input voltage VIN2, the minimum value Pmin of the total power consumed by system load 20 can be determined based on Equation 4.

[0045] Therefore, according to embodiments of this disclosure that satisfy the assumption that Equation 3 is valid, Pmin can be minimized by adjusting (or regulating) the level of the first input voltage VIN1. In one embodiment, the voltage controller 1300 may calculate the level of the first input voltage VIN1 based on the second current information ID2. In this case, the voltage controller 1300 may periodically calculate the increment or decrement of the level of the second current. In one embodiment, the voltage controller 1300 may calculate the increment or decrement of the level of the current flowing through the second power module 1200 based on the second current information ID2 by comparing the level of the current in the current period with the level of the current in the next period. For example, when the increment of the level of the second current exceeds a first threshold, the voltage controller 1300 may generate a feedback signal FS for increasing the level of the first input voltage VIN1 output by the power management integrated circuit 10. For example, when the decrement of the level of the second current exceeds a second threshold, the voltage controller 1300 may generate a feedback signal FS for decreasing the level of the first input voltage VIN1 output by the power management integrated circuit 10. For example, when the increment of the second current level is less than or equal to a first threshold and the decrease of the second current level is less than or equal to a second threshold, the voltage controller 1300 may generate a feedback signal FS to maintain the level of the first input voltage VIN1 output by the power management integrated circuit 10 at the same level as the current. According to embodiments of this disclosure, the period during which the level of the first input voltage VIN1 is regulated can be changed by user request or manufacturer setting.

[0046] The voltage controller 1300 can generate a feedback signal FS that includes information related to the level of the first input voltage VIN1. The power management integrated circuit 10 can provide the feedback signal FS. The power management integrated circuit 10 can increase, decrease, or maintain the level of the first input voltage VIN1 to correspond to the level of the first input voltage VIN1 indicated by the feedback signal FS, and can output the first input voltage VIN1 to the first power module 1100. Figure 1 Unlike the examples shown, the voltage controller 1300 according to an embodiment of this disclosure may be located in the system load 20. In one embodiment, the voltage controller 1300 may determine at least one of the following: the period during which sampling is performed, the period during which the feedback signal FS is generated, the period during which the level of the first input voltage VIN1 increases or decreases, and the period during which at least one of the first current information ID1 and the second current information ID2 is received.

[0047] System load 20 may operate based on output voltage VOUT (i.e., consume power). System load 20 may be implemented differently using chips or modules included in electronic devices (e.g., communication circuitry, memory, application processors, storage devices, display driver integrated circuits (DDI), and input / output (I / O) interfaces). However, this disclosure is not limited thereto. For example, system load 20 may include any system or sub-device that requires power. Figure 1 The illustration shows an example where system load 20 is supplied with only the output voltage VOUT, but this disclosure is not limited thereto. For example, system load 20 may be supplied with any other voltage from any other voltage source in addition to the output voltage VOUT.

[0048] Figure 2A and Figure 2B This is a detailed diagram illustrating the configuration of a power module according to an embodiment of the present disclosure. For convenience, refer to... Figure 1 The given description will be omitted to avoid redundancy.

[0049] Reference Figure 2A The first power module 1100 may include at least one current sensor 1110 and an analog low-dropout (LDO) regulator 1120. Although not explicitly stated in... Figure 2A As shown in the diagram, however, the first power module 1100 according to embodiments of this disclosure may further include an amplifier for signal amplification or an attenuator for signal attenuation. Although not shown in the diagram... Figure 2A As shown, each of the first power module 1100 and the second power module 1200 may also include a switching regulator (or “switching power supply”) for regulating the input voltage.

[0050] Meanwhile, the first power module 1100 can generate voltage in at least two modes, including an internal power supply mode and an external power supply mode, according to user requests or manufacturer settings. The power supply mode can be selected based on the range of power consumed by the system load 20. For example, in the internal power supply mode, the first input voltage (hereinafter referred to as the "first internal input voltage") VIN1_INT of the internal power supply mode can be received from the power management integrated circuit 10, and the first output voltage (hereinafter referred to as the "first internal output voltage") VOUT1_INT of the internal power supply mode with a specific level can be generated by the analog LDO regulator 1120. For example, in the external power supply mode, the first input voltage (hereinafter referred to as the "first external input voltage") VIN1_EXT of the external power supply mode can be received from the power management integrated circuit 10, and the first output voltage (hereinafter referred to as the "first external output voltage") VOUT1_INT of the external power supply mode can be output via a line. Meanwhile, the level of the first external input voltage VIN1_EXT may be reduced due to parasitic resistance. Therefore, the level of the first external output voltage VOUT1_EXT can be lower than the level of the first external input voltage VIN1_EXT.

[0051] Current sensor 1110 can generate first current information ID1 based on a first internal input voltage VIN1_INT or a first external input voltage VIN1_EXT. Simultaneously or optionally, although not in... Figure 2A As shown, however, the current sensor 1110 can generate first current information ID1 based on a first internal output voltage VOUT1_INT or a first external output voltage VOUT1_EXT. For example, the current sensor 1110 can sense (or detect) current generated by a voltage output from the power management integrated circuit 10. The current sensor 1110 can periodically sample the level of the sensed current. (Refer to...) Figure 11 Describe how the current sensor 1110 samples the current. The current sensor 1110 can generate first current information ID1, which includes periodically sampled current values.

[0052] The analog LDO regulator 1120 can generate a first internal output voltage VOUT1_INT based on a first internal input voltage VIN1_INT. For example, the analog LDO regulator 1120 can adjust the first internal input voltage VIN1_INT to have a given level. The analog LDO regulator 1120 can generate a first internal output voltage VOUT1_INT as a result of adjusting the level of the first internal input voltage VIN1_INT. (Refer to...) Figure 3A and Figure 3B Provide a detailed description of the configuration and operation of the analog LDO regulator 1120.

[0053] The second power supply module 1200 may include at least one current sensor 1210 and a digital low-dropout (LDO) regulator 1220. The current sensor 1210 may generate second current information ID2 based on a second output voltage VOUT2. Simultaneously or optionally, although not in... Figure 2A As shown, however, current sensor 1210 can generate second current information ID2 based on the second input voltage VIN2. The operation of current sensor 1210 generating second current information ID2 is similar to the operation of current sensor 1110 generating first current information ID1; therefore, additional descriptions will be omitted to avoid redundancy.

[0054] The digital LDO regulator 1220 may include a comparator 1221, a shift register 1222, and a transistor array 1223.

[0055] Comparator 1221 can generate a comparison signal CS based on a first input voltage VIN1. Here, depending on the power supply mode of the first power module 1100, the first input voltage VIN1 can be a first internal input voltage VIN1_INT or a first external input voltage VIN1_EXT. For example, when the first power module 1100 operates in internal power supply mode, the first input voltage VIN1 can be the first internal input voltage VIN1_INT. For example, when the first power module 1100 operates in external power supply mode, the first input voltage VIN1 can be the first external input voltage VIN1_EXT. Additionally, comparator 1221 can compare the first input voltage VIN1 with a reference voltage. For example, comparator 1221 can generate a comparison signal CS based on the result of comparing the reference voltage with the first input voltage VIN1. Here, the reference voltage is a voltage used to determine whether additional power supply from the second power module 1200 is required. Figure 4 The configuration and operation of comparator 1221 are described in detail.

[0056] Shift register 1222 can generate a result code "Q" based on the comparison signal CS. Here, the result code "Q" can be a binary code corresponding to the level of the current output by the second power module 1200. For example, if shift register 1222 is a 5-bit shift register, shift register 1222 can generate a 5-bit result code "Q" (e.g., "00000"). Shift register 1222 according to embodiments of this disclosure can be controlled by a separate controller (not shown) located inside or outside the second power module 1200. Although not explicitly stated... Figure 2A As shown, however, according to an embodiment of this disclosure, shift register 1222 may receive a signal for resetting the result code "Q". (Refer to...) Figure 4 and Figure 5 Provide a detailed description of the configuration and operation of shift register 1222.

[0057] Transistor array 1223 can generate a second output voltage VOUT2 based on the result code "Q" and the second input voltage VIN2. Transistor array 1223 may include multiple transistors. For example, transistor array 1223 can adjust the current level by turning transistors on or off. Here, the result code "Q" can be used to determine whether a transistor is on or off. (Refer to...) Figure 4 The configuration and operation of transistor array 1223 are described in detail.

[0058] The voltage controller 1300 can generate a feedback signal FS based on at least one of first current information ID1 and second current information ID2. For example, the voltage controller 1300 can determine the change in the level of the current flowing through the first power module 1100 based on the first current information ID1, or it can determine the change in the level of the current flowing through the second power module 1200 based on the second current information ID2. The voltage controller 1300 can generate the feedback signal FS based on the determined change in the current level, and the feedback signal FS is used to adjust the level of at least one of the first internal input voltage VIN1_INT, the first external input voltage VIN1_EXT, and the second input voltage VIN2 output by the power management integrated circuit 10.

[0059] Figure 2B This is a configuration diagram illustrating the current sensing mode of a power module according to an embodiment of the present disclosure. For convenience, refer to... Figure 2A The given description will be omitted to avoid redundancy.

[0060] According to embodiments of this disclosure, each of the first power module 1100 and the second power module 1200 may omit a separate current sensor for sensing current. In one embodiment, the shift register 1222 may generate second current information ID2. Here, the second current information ID2 may correspond to the result code "Q". That is, because the result code "Q" corresponds to the level of the current output by the second power module 1200, the second current information ID2 may correspond to information related to the level of the current output by the second power module 1200.

[0061] The voltage controller 1300 can generate a feedback signal FS based on the second current information ID2. The voltage controller 1300 can receive the second current information ID2 corresponding to the result code "Q" from the shift register 1222. Here, the period at which the voltage controller 1300 receives the second current information ID2 can be changed according to user request or manufacturer settings. The voltage controller 1300 can calculate the increment or decrement of the current level output by the second power module 1200 based on the result code "Q".

[0062] Figure 3A and Figure 3B It is shown in detail Figure 2A and Figure 2B The diagram shows the configuration of the analog LDO regulator 1120. (Refer to...) Figure 3A The analog LDO regulator 1120 may include a first error operational amplifier (OP-AMP) OP1, a pass transistor TR, a first resistor R1, and a second resistor R2. The analog LDO regulator 1120 can generate a first internal output voltage VOUT1_INT based on a first internal input voltage VIN1_INT.

[0063] The first error OP-AMP OP1 may include a (+) input terminal, a (-) input terminal, a positive power supply terminal, a negative power supply terminal, and an output terminal. A first reference voltage VREF1 may be applied to the (+) input terminal of the first error OP-AMP OP1, and a feedback voltage VFB may be applied to the (-) input terminal of the first error OP-AMP OP1. A first internal input voltage VIN1_INT may be applied to the positive power supply terminal of the first error OP-AMP OP1, and a ground node may be connected to the negative power supply terminal of the first error OP-AMP OP1. According to embodiments of this disclosure, although not in Figure 3A As shown, however, a charge pump (not shown) may also be disposed between the first node N1 and the positive power supply terminal. According to embodiments of this disclosure, with Figure 3A Unlike the example shown, a separate bias voltage can be applied to the positive power supply terminal.

[0064] Additionally, the first error OP-AMP OP1 can compare the first reference voltage VREF1 with the feedback voltage VFB. The first error OP-AMP OP1 can amplify the difference between the first reference voltage VREF1 and the feedback voltage VFB to output the gate voltage VG through the output terminal of the first error OP-AMP OP1.

[0065] The channel transistor TR may include a first terminal (e.g., source), a second terminal (e.g., drain), and a third terminal (e.g., gate). A first internal input voltage VIN1_INT is input to the first terminal, a first internal output voltage VOUT1_INT is output from the second terminal, and the third terminal is connected to the output terminal of the first error OP-AMP OP1. For example, the channel transistor TR may be a p-channel metal-oxide-semiconductor (PMOS) transistor, but this disclosure is not limited thereto. For example, the channel transistor TR may be implemented using any transistor capable of performing switching and / or amplification operations. The channel transistor TR may be driven based on the gate voltage VG input to the third terminal of the channel transistor TR.

[0066] A first resistor R1 can be connected between the second node N2 and the third node N3, and a second resistor R2 can be connected between the third node N3 and the ground node. The first resistor R1 and the second resistor R2 can divide the voltage (e.g., the first internal output voltage VOUT1_INT) of the second node N2 connected to the second terminal of the channel transistor TR, such that the feedback voltage VFB is transmitted to the (-) input terminal of the first error OP-AMP OP1. The values ​​of the first resistor R1 and the second resistor R2 can vary according to user requests or manufacturer settings. However, this disclosure is not limited thereto. For example, each of the first resistor R1 and the second resistor R2 can have a fixed value. Thus, a feedback loop can be implemented in which the first error OP-AMP OP1 receives the feedback voltage VFB to output the gate voltage VG to its output terminal, and the first internal output voltage VOUT1_INT of the second terminal of the channel transistor TR is divided. Additionally, the analog LDO regulator 1120 can transmit the first internal input voltage VIN1_INT to the multiplexer 1400 (see reference). Figure 2B ).

[0067] However, this disclosure is not limited thereto. The analog LDO regulator 1120 can transmit the voltage of the lines present therein to the multiplexer 1400. For example, as... Figure 3B As shown, the analog LDO regulator 1120 can transmit the first internal output voltage VOUT1_INT to the multiplexer 1400. Below, for convenience, as... Figure 3A The illustration is given under the assumption that the analog LDO regulator 1120 transmits the first internal input voltage VIN1_INT to the multiplexer 1400. However, this disclosure is not limited thereto.

[0068] Figure 4 It is shown in detail Figure 2A and Figure 2B The configuration diagram of the digital LDO regulator 1220 shown is provided. For convenience, refer to... Figure 2A and Figure 2B The given description will be omitted to avoid redundancy.

[0069] Comparator 1221 may include a second error OP-AMP OP2. For example, the second error OP-AMP OP2 may operate as an analog-to-digital converter (ADC). The second error OP-AMP OP2 may operate synchronously with a clock signal CLK. The second error OP-AMP OP2 may include a (+) input terminal, a (-) input terminal, and an output terminal. A second reference voltage VREF2 may be applied to the (+) input terminal of the second error OP-AMP OP2, and a first input voltage VIN1 may be applied to the (-) input terminal of the second error OP-AMP OP2. The second error OP-AMP OP2 may output a comparison signal CS through its output terminal.

[0070] The second error OP-AMP OP2 compares the level of the second reference voltage VREF2 with the level of the first input voltage VIN1. For example, when the level of the second reference voltage VREF2 is higher than the level of the first input voltage VIN1, the second error OP-AMP OP2 generates a comparison signal CS indicating a logic high value (e.g., "1"). Conversely, when the level of the second reference voltage VREF2 is not higher than the level of the first input voltage VIN1, the second error OP-AMP OP2 generates a comparison signal CS indicating a logic low value (e.g., "0").

[0071] Shift register 1222 can generate an N-bit result code Q[N:1] based on the comparison signal CS. Here, "N" is a natural number of 1 or greater. For example, when shift register 1222 is a 5-bit shift register, it can generate a 5-bit result code Q[5:1]. Shift register 1222 can operate synchronously with the clock signal CLK. Shift register 1222 can periodically check the comparison signal CS and generate the result code Q[N:1]. When the comparison signal CS is "1", the value of the result code Q[N:1] increases, and when the comparison signal CS is "0", the value of the result code Q[N:1] decreases. For example, when the N-bit result code Q[N:1] is a 5-bit result code Q[5:1], the 5-bit result code Q[5:1] can be "00000, 00001, 00010, 00011, ..., 11111". (Refer to...) Figure 5 Describe in detail the operation of shift register 1222 to generate an N-bit result code Q[N:1].

[0072] Although not in Figure 4 As shown in the figure, however, in one embodiment, shift register 1222 may generate a second current information ID2. Here, the second current information ID2 may correspond to an N-bit result code Q[N:1].

[0073] Transistor array 1223 can output a second output current IOUT2. Transistor array 1223 may include "n" transistors. Here, "n" is any natural number greater than 0. In one embodiment, "n" may be greater than or equal to "N". Each of the "n" transistors may include a first terminal (e.g., source), a second terminal (e.g., drain), and a third terminal (e.g., gate), with a second input voltage VIN2 input to the first terminal, a second output voltage VOUT2 output from the second terminal, and the third terminal connected to shift register 1222. For example, each of the "n" transistors may be a p-channel metal-oxide-semiconductor (PMOS) transistor, but this disclosure is not limited thereto. For example, each of the "n" transistors may be implemented using any transistor capable of performing switching and / or amplification operations.

[0074] The “n” transistors (e.g., first transistor TR1 to nth transistor TRn) can be turned on or off respectively based on the N-bit result code Q[N:1]. Therefore, the level of the second output current IOUT2 ​​can vary depending on the on / off combination of the first transistor TR1 to nth transistor TRn in the transistor array 1223. In one embodiment, the level of the second output current IOUT2 ​​can increase as the number of turned-on transistors among the first transistor TR1 to nth transistor TRn in the transistor array 1223 increases, and decrease as the number of turned-on transistors among the first transistor TR1 to nth transistor TRn in the transistor array 1223 decreases. For example, when the N-bit result code Q[N:1] is a 5-bit result code Q[5:1], the first transistor TR1 to the fifth transistor TR5 can be controlled by the 5-bit result code Q[5:1]. In the case where the sixth transistor TR6 to the nth transistor TRn are present in the transistor array 1223, the sixth transistor TR6 to the nth transistor TRn can remain off. Figure 4 An example of transistor array 1223 including PMOS transistors is shown. In this case, the transistor is turned on when the bit value is "0" and turned off when the bit value is "1". However, this disclosure is not limited thereto. For example, the correspondence between bit values ​​and transistor on or off can be changed by an inverter (not shown).

[0075] For example, when the 5-bit result code Q[5:1] is "11000", the bits constituting the 5-bit result code Q[5:1] can correspond to the first transistor TR1 to the fifth transistor TR5 respectively. The bits corresponding to the first transistor TR1 to the fifth transistor TR5 can be input to the third terminal of the first transistor TR1 to the fifth transistor TR5 respectively.

[0076] Figure 5 This is a timing diagram used to describe the operation of a digital LDO regulator according to embodiments of the present disclosure. (See also...) Figure 4and Figure 5 Comparator 1221 and shift register 1222 can operate synchronously with clock signal CLK. Comparator 1221 can generate a comparison signal CS synchronously with clock signal CLK. Shift register 1222 can receive the comparison signal CS from comparator 1221. Shift register 1222 can generate an N-bit result code Q[N:1] based on clock signal CLK and comparison signal CS. This will be referenced in the case that the N-bit result code Q[N:1] is a 5-bit result code Q[5:1]. Figure 5 Provide a description.

[0077] The shift register 1222 can check the value of the comparison signal CS based on the clock signal CLK, which is set for each period according to user request or manufacturer settings. The shift register 1222 can generate a 5-bit result code Q[5:1] by changing the code value according to the value of the comparison signal CS thus checked. For example, the default value of the 5-bit result code Q[5:1] can be set to "11111", but this disclosure is not limited thereto. Therefore, when the 5-bit result code Q[5:1] has the default value "11111", all transistors (e.g., TR1 to TRn) of the transistor array 1223 are turned off, and the level of the second output current IOUT2 ​​is "0".

[0078] Shift register 1222 can shift the bits of the 5-bit result code Q[5:1] one by one to the right or left, synchronously with the clock signal CLK. For example, when the compare signal CS is "1", shift register 1222 performs a 1-bit left shift operation. Furthermore, Q[5] is "0". For example, assuming shift register 1222 outputs the 5-bit result code Q[5:1] of "11111" in time period "t", shift register 1222 can output "11110" as the 5-bit result code Q[5:1] in time period "t+1". When the compare signal CS is set to "1" again, shift register 1222 can output "11100" as the 5-bit result code Q[5:1] in time period (t+2).

[0079] In contrast, when the comparison signal CS is "0", shift register 1222 performs a 1-bit right shift operation. For example, assuming shift register 1222 outputs the 5-bit result code Q[5:1] of "11000" in time period "t", shift register 1222 can output "11100" as the 5-bit result code Q[5:1] in time period "t+1". When the comparison signal CS is set to "0" again, shift register 1222 can output "11110" as the 5-bit result code Q[5:1] in time period (t+2).

[0080] Figure 6A and Figure 6BThis is a configuration diagram illustrating a power module operating in an internal power supply mode according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, a first input voltage can be used in at least one of an internal power supply mode and an external power supply mode. (Refer to...) Figure 6A and Figure 6B The power module 2000 can generate an output voltage VOUT in internal power supply mode. For convenience, refer to... Figures 1 to 4 The given description will be omitted to avoid redundancy.

[0081] Figure 6A An embodiment is shown in which the power module 2000 includes a separate current sensor in internal power supply mode. (See reference...) Figure 6A The first power module 2100 may include multiple current sensors 2110_1 and 2110_2, and the second power module 2200 may include multiple current sensors 2210_1 and 2210_2. In addition to the multiple current sensors 2110_1, 2110_2, 2210_1, and 2210_2, although not in... Figure 6A As shown, however, the current sensors can be located on internal or external lines of the power module 2000. Each of the plurality of current sensors 2110_1, 2110_2, 2210_1, and 2210_2 can sense the current flowing through the line. Specifically, current sensor 2110_1 can sense a first internal input current IIN1_INT. Current sensor 2110_2 can sense a first internal output current IOUT1_INT. Current sensor 2210_1 can sense a second input current IIN2. Current sensor 2210_2 can sense a second output current IOUT2. The plurality of current sensors 2110_1, 2110_2, 2210_1, and 2210_2 can provide first current information ID1 and second current information ID2 to voltage controller 2300 based on the sensed currents IIN1_INT, IOUT1_INT, IIN2, and IOUT2.

[0082] For example, in reference Figure 1 and Figure 2AAs described above, voltage controller 2300 can generate a feedback signal FS based on first current information ID1 and second current information ID2. According to embodiments of this disclosure, voltage controller 2300 can monitor the increment or decrement of the level of the second output current IOUT2 ​​based on the second current information ID2, and can generate the feedback signal FS, which includes information indicating whether the level of the first internal input voltage VIN1_INT is increased, decreased, or maintained in the next time period. Power management integrated circuit 10 can adjust (e.g., increase, decrease, or maintain) the level of the first internal input voltage VIN1_INT in the next time period based on the feedback signal FS. The adjusted first internal input voltage VIN1_INT can then be provided to the first power module 2100.

[0083] For example, in reference Figure 3A and Figure 3B As described above, the analog LDO regulator 2120 generates a first internal output current IOUT1_INT. The comparator 2221 in the digital LDO regulator 2220 generates a comparison signal CS based on the result of comparing the level of the second reference voltage VREF2 with the level of the first internal input voltage VIN1_INT. (As in the reference...) Figure 4 As described above, the digital LDO regulator 2220 can generate a second output current IOUT2 ​​via shift register 2222 and transistor array 2223. The first internal output current IOUT1_INT and the second output current IOUT2 ​​can form the output current IOUT at the output node NOUT. Therefore, the power supply module 2000 can provide the output current IOUT. The output current IOUT can provide the load current IL required by the system load 20. A load capacitor CL with load capacitance can be configured to maintain the level of the output voltage VOUT.

[0084] Figure 6B An example is shown where shift register 2222 generates the second current information ID2. (Refer to...) Figure 6B The first power module 2100 and the second power module 2200 may omit separate current sensors. For convenience, refer to... Figure 6A The given description will be omitted to avoid redundancy. According to embodiments of this disclosure, shift register 2222 can generate a second current information ID2 corresponding to an N-bit result code Q[N:1]. (See reference...) Figure 1 and Figure 2B As described above, the voltage controller 2300 can generate a feedback signal FS based on the second current information ID2.

[0085] This will be referenced under the assumption that the N-bit result code Q[N:1] is the same as the 5-bit result code Q[5:1]. Figure 6B With reference Figure 5The description is given together with the description. The voltage controller 2300 can periodically receive the second current information ID2 corresponding to the 5-bit result code Q[5:1]. When the 5-bit result code Q[5:1] is "11111" in time period "t" and "11110" in time period "t+1", the voltage controller 2300 can sense that the level of the second current increases between time periods "t" and "t+1". Therefore, when the increment of the level of the second current exceeds a first threshold, the voltage controller 2300 can generate a feedback signal FS for increasing the level of the first input voltage VIN1 output by the power management integrated circuit 10. When the 5-bit result code Q[5:1] is "11100" in time period "t" and "11110" in time period "t+1", the voltage controller 2300 can sense that the level of the second current decreases between time periods "t" and "t+1". Therefore, when the decrease in the level of the second current exceeds the second threshold, the voltage controller 2300 can generate a feedback signal FS to reduce the level of the first input voltage VIN1 output by the power management integrated circuit 10.

[0086] Figure 7A and Figure 7B This is a configuration diagram illustrating a power module operating in external power supply mode according to an embodiment of the present disclosure. (Refer to...) Figure 7A and Figure 7B The power module 3000 can generate an output voltage VOUT in external power supply mode. For convenience, refer to... Figures 1 to 4 and Figure 6A The given description will be omitted to avoid redundancy.

[0087] Figure 7A An embodiment is shown in which the power module 3000 includes a separate current sensor in external power supply mode. (Refer to...) Figure 7A The first power module 3100 may include a current sensor 3110, and the second power module 3200 may include multiple current sensors 3210_1 and 3210_2. In addition to the multiple current sensors 3110, 3210_1, and 3210_2, although not in... Figure 7A As shown, however, the current sensors can be located on internal or external lines of the power module 3000. Each of the plurality of current sensors 3110, 3210_1, and 3210_2 can sense the current flowing through the line. Specifically, current sensor 3110 can sense a first external input current IIN1_EXT. Current sensor 3210_1 can sense a second input current IIN2. Current sensor 3210_2 can sense a second output current IOUT2. The plurality of current sensors 3110, 3210_1, and 3210_2 can provide first current information ID1 and second current information ID2 to voltage controller 3300 based on the sensed currents IIN1_EXT, IIN2, and IOUT2.

[0088] When the first power module 3100 operates in external power supply mode, unlike in internal power supply mode, the first power module 3100 may not include components such as an analog LDO regulator. That is, the first power module 3100 according to embodiments of this disclosure may only include lines through which current flows. Therefore, in Figure 7A In this document, for ease of description, the first external input current IIN1_EXT and the first external output current IOUT1_EXT are labeled with different reference numbers, but refer to the same current flowing through the same line.

[0089] The comparator 3221 in the digital LDO regulator 3220 generates a comparison signal CS based on the result of comparing the level of the second reference voltage VREF2 with the level of the first external input voltage VIN1_EXT. (As in the reference...) Figure 4 As described above, the digital LDO regulator 3220 can generate a second output current IOUT2 ​​via shift register 3222 and transistor array 3223. The first external output current IOUT1_EXT and the second output current IOUT2 ​​can form the output current IOUT at the output node NOUT.

[0090] Figure 7B An example is shown where shift register 3222 generates the second current information ID2. (Refer to...) Figure 7B The first power module 3100 and the second power module 3200 may omit separate current sensors. For convenience, refer to... Figure 6A and Figure 7A The given description will be omitted to avoid redundancy.

[0091] Figure 8 This is a configuration diagram illustrating a power module operating in an internal power supply mode and an external power supply mode according to embodiments of the present disclosure. According to embodiments of the present disclosure, the power module 4000 can operate in both an internal power supply mode and an external power supply mode. (Refer to...) Figure 6A , Figure 6B , Figure 7A and Figure 7B Descriptions of the operation associated with the internal or external power supply modes will be omitted to avoid redundancy.

[0092] The power module 4000 may also include a multiplexer (MUX) 4400. The multiplexer 4400 may receive a first internal input voltage VIN1_INT and a first external input voltage VIN1_EXT. The multiplexer 4400 may select one of the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT based on a multiplexer control signal MCTR. Here, although the multiplexer control signal MCTR is not shown, it may be controlled (or generated) by a separate controller (not shown) located inside or outside the power module 4000. For example, the controller (not shown) may generate the multiplexer control signal MCTR to determine whether the first power module 4100 is operating in internal or external power supply mode, in order to match the power level required by the system load 20. Therefore, the multiplexer 4400 may output one selected from the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT.

[0093] The first power supply module 4100 can output a first output current IOUT1. Here, depending on the selected power supply mode, the first output current IOUT1 can correspond to one of a first internal output current IOUT1_INT and a first external output current IOUT1_EXT. The digital LDO regulator 4220 can generate a second output current IOUT2. The second power supply module 4200 can output the second output current IOUT2. Therefore, the first output current IOUT1 and the second output current IOUT2 ​​can form an output current IOUT at the output node NOUT. The voltage controller 4300 can generate a feedback signal FS based on at least one of a plurality of first current information ID1 and a plurality of second current information ID2.

[0094] Figure 9 This is a configuration diagram illustrating an electronic device according to another embodiment of the present disclosure. For convenience, refer to... Figure 1 The given description will be omitted to avoid redundancy.

[0095] The electronic device may include a power management integrated circuit 30, a power module 5000, and a system load 40. According to embodiments of this disclosure, the power module 5000 may output a first output voltage VOUT1 and a second output voltage VOUT2. The system load 40 may receive the first output voltage VOUT1 and the second output voltage VOUT2, and may internally utilize the received voltages VOUT1 and VOUT2. The level of the first output voltage VOUT1 may be adjusted in real time by a voltage controller 5300. The second output voltage VOUT2 may not be provided if the system load 40 can consume power sufficiently and efficiently by using only the first output voltage VOUT1.

[0096] Figure 10This is a graph showing the load current for each scenario according to embodiments of the present disclosure. Figure 10 In the diagram, the x-axis represents "n" scenarios over time, and the y-axis represents the flow to the system load 20 (refer to...). Figure 1 The load current IL is the level of the load current. In most scenarios, the load current can be specified within the normal range of the scenario. However, in the Kth scenario, the maximum load current IL is... MAX It can flow to the system load of 20. Maximum load current IL MAX The current may be significantly higher than the typical range for the scenario. Therefore, the power management integrated circuit 10 or power module 1000 that supplies voltage to the system load 20 should provide a sufficiently high voltage level for the system load 20 to operate properly.

[0097] However, continuously supplying a high-level voltage to the system load 20 to cope with the unusual maximum load current IL MAX This approach may be inefficient in terms of power consumption. Referring to Equation 1 above, the load current IL can be determined by the sum of the first current I1 and the second current I2. Therefore, the voltage controller 1300 can sense changes in the load current IL by monitoring the first current I1 and the second current I2. For example, in scenarios prior to scenario K (e.g., scenario K-1), the voltage controller 1300 can sense the increment in the level of the load current IL. When the increment in the level of the load current IL exceeds a first threshold determined according to a user request or manufacturer setting, the voltage controller 1300 can generate a feedback signal FS for increasing the level of the first input voltage VIN1 in the next time period. In contrast, in scenarios after scenario K (e.g., scenario K+1), the voltage controller 1300 can sense the decrement in the level of the load current IL. When the decrement in the level of the load current IL exceeds a second threshold determined according to a user request or manufacturer setting, the voltage controller 1300 can generate a feedback signal FS for decreasing the level of the first input voltage VIN1 in the next time period. According to embodiments of this disclosure, the system load 20 can consume power more efficiently when the level of the first input voltage VIN1 changes in real time. (Refer to...) Figure 12A and Figure 12B A detailed description of the power efficiency according to embodiments of the present disclosure is provided.

[0098] Figure 11 This is a graph illustrating the current sampling mode according to an embodiment of the present disclosure. (Refer to...) Figure 11 Current sensors 1110 and 1210 (refer to) Figure 1 Each of the current sensors 1110 and 1210 can periodically sense the current flowing through the line. The current sensed by each of the current sensors 1110 and 1210 can be periodically sampled by the current sensors 1110 and 1210 or the voltage controller 1300. Figure 11The top diagram shows the level of the current sensed in analog form by each of the current sensors 1110 and 1210. Figure 11 The bottom figure illustrates the value obtained by periodically sampling the analog current level by current sensors 1110 and 1210 or voltage controller 1300. According to embodiments of this disclosure, the sensing period and / or sampling period may be varied upon user request or manufacturer setting.

[0099] Figure 12A and Figure 12B This is a graph showing how much power is reduced according to embodiments of the present disclosure. According to embodiments of the present disclosure, Figure 12A This shows how much power is reduced compared to supplying the system load with only one voltage source. Figure 12B The power reduction is shown compared to a case where a voltage controller is not provided in this disclosure.

[0100] Reference Figure 1 and Figure 12A According to embodiments of this disclosure, power can be reduced compared to supplying power to the system load using only one voltage source (e.g., compared to not providing a second power supply module of this disclosure). Meanwhile, the x-axis represents the level of the load current (IL), and the y-axis represents the reduced power. Figure 12A In the diagram, the solid line graph (Auto) shows the power reduction according to an embodiment of the present disclosure. The remaining graphs, besides the solid line graph (Auto), are measured assuming the power module 1000 does not include the voltage controller 1300. The dashed line graph (1.1V) shows the power reduction when the level of the first input voltage VIN1 input to the first power module is fixed at 1.1V. The dotted-dash line graph (1.25V) shows the power reduction when the level of the first input voltage VIN1 input to the first power module is fixed at 1.25V. The double-dash line graph (1.4V) shows the power reduction when the level of the first input voltage VIN1 input to the first power module is fixed at 1.4V.

[0101] Referring to the trends of the remaining curves excluding the solid line (Auto), when the load current IL is low, the power reduction increases as the first input voltage VIN1 decreases. Conversely, when the load current IL is high, the power reduction increases as the first input voltage VIN1 increases. For example, when the load current IL is less than 0.1A, the power reduction is greatest when the first input voltage VIN1 is 1.1V. When the load current IL is greater than 0.1A and less than 0.2A, the power reduction is greatest when the first input voltage VIN1 is 1.25V. When the load current IL is greater than 0.2A, the power reduction is greatest when the first input voltage VIN1 is 1.4V. Therefore, when the first input voltage VIN1 is fixed, optimal power efficiency cannot be achieved when the load current IL fluctuates significantly.

[0102] Reference Figure 12A The trend of the solid line graph (Auto) shows that, regardless of the load current IL, the power reduction is always equal to or greater than the power reduction when the first input voltage VIN1 is fixed. Therefore, optimal power efficiency can always be achieved even when the load current IL fluctuates greatly.

[0103] Figure 12B The diagram shows the first input voltage VIN1 (reference). Figure 1 The voltage level is fixed at 1.4V (compared to...). Figure 12A The power difference of this disclosure is compared to the case shown in the double-dotted line graph (corresponding to the case shown in the figure). The x-axis represents the level of the load current IL, and the y-axis represents the power difference. According to embodiments of this disclosure, the level of the first input voltage VIN1 can be adjusted in real time based on changes in the level of the load current IL at each given time period. For example, when the level of the load current IL is low (e.g., 0.1A), the level of the first input voltage VIN1 can be lower than 1.4V. Therefore, compared to the case where the level of the first input voltage VIN1 is fixed at 1.4V, this disclosure consistently achieves optimal power efficiency.

[0104] Figure 13 This is a configuration diagram illustrating the communication structure of an electronic device according to an embodiment of the present disclosure. The electronic device may include a power supply device 50, a power module 6000, an application processor (AP) 16, an input / output interface 62, a memory 63, a storage device 64, a display driver integrated circuit (DDI) 65, and a communication circuit block 66. Additionally, the electronic device may include any other circuits, modules, or blocks that require power.

[0105] The power supply unit 50 may include a PMIC controller 51, a power management integrated circuit 52, and a battery 53. For example, the power supply unit 50 may be a separate device. The PMIC controller 51 may adjust the level of the voltage provided by the power management integrated circuit 52 based on feedback signals provided by the voltage controller 6300. The PMIC controller 51 may be located external to the power management integrated circuit 52; however, it may be located in conjunction with... Figure 13 Unlike other examples, the PMIC controller 51 can be integrated into the power management integrated circuit 52. The battery 53 provides power, enabling the power management integrated circuit 52 to generate voltage.

[0106] Power module 6000 may include a first power module 6100, a second power module 6200, and a voltage controller 6300. Voltage controller 6300 may communicate with PMIC controller 51 and / or power management integrated circuit 52. Voltage controller 6300 may request the voltage required by power module 6000 from PMIC controller 51 and / or power management integrated circuit 52. According to embodiments of this disclosure, voltage controller 6300 may be located within power module 6000, but this disclosure is not limited thereto. For example, with... Figure 13 Unlike other examples, the voltage controller 6300 may be located in any of the application processor 61, input / output interface 62, memory 63, storage device 64, display driver integrated circuit 65, and communication circuit block 66.

[0107] Figure 14 This is a configuration diagram illustrating a display device according to an embodiment of the present disclosure. The display device may also include a power management integrated circuit 7000, a display driver circuit 8000, and a display panel 9000. The power management integrated circuit 7000 can generate a first input voltage VIN1 and a second input voltage VIN2.

[0108] The display driver circuit 8000 may include a power supply module 8100, a timing controller 8200, a source driver integrated circuit (e.g., a source IC) 8300, and a gate driver integrated circuit (e.g., a gate IC) 8400. The display driver circuit 8000 can provide the power required by the display panel 9000 based on at least one of a first input voltage VIN1 and a second input voltage VIN2. The power supply module 8100 can generate voltages to achieve optimal power efficiency. For example, the power supply module 8100 can generate an analog supply voltage AVDD and gate drive voltages VGH and VGL. The power supply module 8100 can generate an output voltage VOUT (see reference) based on the different first input voltages VIN1 and second input voltages VIN2. Figure 1 (For example, analog power supply voltage AVDD and gate drive voltages VGH and VGL).

[0109] The power module 8100 can generate a first current I1 based on a first input voltage VIN1 (refer to Equation 1). When the first input voltage VIN1 decreases due to increased power consumption of the display panel 9000, the power module 8100 can output a second current I2 based on the first input voltage VIN1 and a second input voltage VIN2 (refer to Equation 1). According to embodiments of this disclosure, in order to adjust the level of the first input voltage VIN1, the power module 8100 can monitor the first current I1 and / or the second current I2. According to embodiments of this disclosure, the period during which the power module 8100 monitors and / or samples the first current I1 and / or the second current I2 can correspond to a frame unit of the image displayed by the display panel 9000. However, this disclosure is not limited thereto. For example, the period can be determined without considering frames. Furthermore, according to embodiments of this disclosure, the period during which the power module 8100 adjusts the level of the first input voltage VIN1 can correspond to a frame unit of the image displayed by the display panel 9000. However, this disclosure is not limited thereto. For example, the period can be determined without considering frames.

[0110] The timing controller 8200 controls the overall operation of the display driver circuit 8000. The timing controller 8200 receives image data RGB and control signals CT0 from an external source. The control signals CT0 may include a vertical synchronization signal for distinguishing frames, a horizontal synchronization signal for distinguishing lines, and a data enable signal that is high when data is output and indicates the area where data is received. The timing controller 8200 outputs a first control signal CT1, a second control signal CT2, and modulated image data RGB'. The timing controller 8200 generates the modulated image data RGB' by converting the data format of the image data RGB to an interface specification suitable for the source driver IC 8300, and provides the modulated image data RGB' to the source driver IC 8300. The first control signal CT1 represents a signal used to control the operation of the source driver IC 8300. The first control signal CT1 may include a horizontal start signal indicating the start of operation of the source driver IC 8300, and an output indication signal for determining the timing of the data voltage output from the source driver IC 8300. The second control signal CT2 represents a signal used to control the operation of the gate driver IC8400. The second control signal CT2 may include the gate clock and the vertical start signal.

[0111] The source driver IC 8300 outputs a data voltage to data lines D1 to Dm based on the first control signal CT1 and the modulated image data RGB'. The source driver IC 8300 can also perform a digital-to-analog conversion operation on the modulated image data RGB' to convert it into a data voltage.

[0112] The gate driver IC 8400 provides gate signals to gate lines G1 to Gn based on the second control signal CT2. The gate driver IC 8400 generates gate signals for driving gate lines G1 to Gn based on the second control signal CT2, and outputs the gate signals sequentially to gate lines G1 to Gn.

[0113] Display panel 9000 can display images. For example, display panel 9000 can be implemented in various panels, such as organic light-emitting diode (OLED) panels, active-matrix organic light-emitting diode (AMOLED) panels, liquid crystal display (LCD) panels, electrophoretic display panels, electrowetting display panels, and plasma display panels (PDP) panels. Display panel 9000 includes gate lines G1 to Gn, data lines D1 to Dm, and pixels PX. Each of the gate lines G1 to Gn receives a gate voltage from display driving circuit 8000. Each of the data lines D1 to Dm receives a data voltage from display driving circuit 8000. Gate lines G1 to Gn and data lines D1 to Dm are electrically isolated and cross each other. Each pixel PX can be connected to one of the gate lines G1 to Gn and one of the data lines D1 to Dm.

[0114] Figure 15 This is a flowchart illustrating a method of operating an electronic device according to an embodiment of the present disclosure. For ease of description, reference will be made to... Figure 8 To describe using reference marks / labels Figure 15 .

[0115] In operation S101, the first power supply module 4100 can generate a first output current IOUT1 based on a first input voltage VIN1 received from an external source. According to embodiments of this disclosure, the power supply module 4000 can select either an internal power supply mode or an external power supply mode based on the load current IL of the system load 20. Therefore, depending on the power supply mode, the first input voltage VIN1 can be either a first internal input voltage VIN1_INT or a first external input voltage VIN1_EXT. For example, in the internal power supply mode, the first power supply module 4100 can generate the first internal output current IOUT1_INT based on the first internal input voltage VIN1_INT using an analog LDO regulator 4120. Simultaneously, in the external power supply mode, the first power supply module 4100 can generate the first external output current IOUT1_EXT based on the first external input voltage VIN1_EXT.

[0116] In operation S102, the second power supply module 4200 can compare the level of the first input voltage VIN1 with the level of the second reference voltage VREF2.

[0117] In operation S103, comparator 4221 may generate a comparison signal CS based on the result of comparing the level of the first input voltage VIN1 with the level of the second reference voltage VREF2. For example, when the level of the second reference voltage VREF2 is higher than the level of the first input voltage VIN1, comparator 4221 may generate a comparison signal CS indicating a logic high value (e.g., "1"). Conversely, when the level of the second reference voltage VREF2 is lower than the level of the first input voltage VIN1, comparator 4221 may generate a comparison signal CS indicating a logic low value (e.g., "0").

[0118] In operation S104, shift register 4222 can generate a result code "Q" corresponding to the accumulated information of comparison signal CS based on comparison signal CS.

[0119] In operation S105, transistor array 4223 can generate a second output current IOUT2 ​​based on the result code "Q" and the second input voltage VIN2.

[0120] In operation S106, the power module 4000 can provide power to the system load 20 by generating an output current IOUT based on the first output current IOUT1 and the second output current IOUT2.

[0121] In operation S107, current sensors 4110_1, 4110_2, 4110_3, 4210_1, and 4210_2 can generate first current information ID1 and second current information ID2 by sensing the current flowing through the first power module 4100 and the second power module 4200. According to an embodiment of this disclosure, shift register 4222 can generate the second current information ID2 corresponding to the result code "Q".

[0122] In operation S108, the voltage controller 4300 may generate a feedback signal FS based on the first current information ID1 and the second current information ID2. The feedback signal FS includes information indicating whether the level of the first input voltage VIN1 and / or the second input voltage VIN2 is increased, decreased, or maintained in the next time period.

[0123] In operation S109, the voltage controller 4300 may send a feedback signal FS to an external device. The external device receiving the feedback signal FS may apply a first input voltage VIN1 and / or a second input voltage VIN2 with an regulated level (e.g., an increased, decreased, or maintained level) to the power supply module 4000.

[0124] In operation S110, it is determined whether system load 20 continuously requires power. When it is determined that system load 20 continuously requires power (yes), the process proceeds to operation S101. When it is determined that system load 20 does not require power (no), the process ends.

[0125] According to this disclosure, even if the level of the current flowing to the system load changes, the electronic device can always consume power with optimal efficiency by adjusting the level of the input voltage in real time.

[0126] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A power supply module comprising: a first power supply module configured to generate a first output current based on a first input voltage; a second power supply module configured to generate a second output voltage based on a second input voltage, generate a second output current based on the second output voltage, and generate the second output current when a level of the first input voltage is less than a level of a reference voltage; and a voltage controller configured to generate a feedback signal for adjusting at least one of the level of the first input voltage and the level of the second input voltage based on current information related to a current flowing in the power supply module.

2. The power module of claim 1, wherein, The second power supply module includes: a current sensor configured to sense the current flowing in the second power supply module and generate information related to the current flowing in the second power supply module, wherein the current information includes the information related to the current flowing in the second power supply module.

3. The power module of claim 2, wherein, The current information includes a set of values obtained by sampling a level of the current flowing in the second power supply module.

4. The power module of claim 3, wherein, The voltage controller is configured to: based on the current information, calculate an increase or decrease in the level of the current flowing in the second power supply module by comparing the level of the current in a current period to the level of the current in a next period; generate the feedback signal for increasing the level of the first input voltage when the increase in the level of the current flowing in the second power supply module exceeds a first threshold value; and generate the feedback signal for decreasing the level of the first input voltage when the decrease in the level of the current flowing in the second power supply module exceeds a second threshold value.

5. The power module of claim 4, wherein, The voltage controller is configured to determine at least one of a period in which the sampling is performed, a period in which the feedback signal is generated, a period in which the level of the first input voltage is increased or decreased, and a period in which the current information is received.

6. The power module of claim 1, wherein, The first power supply module includes a first current sensor configured to sense a first current flowing in the first power supply module and generate information about the first current, wherein the second power supply module includes a second current sensor configured to sense a second current flowing in the second power supply module and generate information about the second current, wherein the current information includes the information about the first current and the information about the second current.

7. The power module of claim 1, wherein, The second power supply module includes: a comparator configured to generate a comparison signal based on a comparison result of comparing the first input voltage with the reference voltage; a shift register configured to generate a result code based on the comparison signal; and a transistor array configured to generate the second output current based on the result code and the second input voltage.

8. The power module of claim 7, wherein, The result code includes a plurality of bits, and the result code corresponds to a level of the second output current.

9. The power module of claim 8, wherein, The comparator generates the comparison signal having a first bit value when the first input voltage is greater than the reference voltage, and generates the comparison signal having a second bit value when the first input voltage is not greater than the reference voltage, wherein the shift register shifts the result code in a first direction when the comparison signal has the first bit value, and shifts the result code in a second direction when the comparison signal has the second bit value.

10. The power module of claim 9, wherein, The transistor array includes a plurality of transistors corresponding to the plurality of bits, respectively, Each of the plurality of bits has a value corresponding to a turn-on or turn-off of a corresponding transistor of the plurality of transistors.

11. The power module of claim 10, wherein, The level of the second output current increases as the number of turned-on transistors among the plurality of transistors increases, and decreases as the number of turned-on transistors among the plurality of transistors decreases.

12. The power module of claim 11, wherein, The shift register generates current information, and provides the current information to the voltage controller, wherein the current information corresponds to the result code.

13. The power module of claim 12, wherein, The voltage controller is configured to: based on the current information corresponding to the result code, calculate an increase or decrease in the level of the second output current by comparing the level of the second output current in the current period with the level of the second output current in the next period; when the increase in the level of the second output current exceeds a first threshold, generate a feedback signal for increasing the level of the first input voltage; and when the decrease in the level of the second output current exceeds a second threshold, generate a feedback signal for decreasing the level of the first input voltage.

14. A method of power supply, the method comprising: generating a first output current based on a first input voltage; comparing a level of the first input voltage with a level of a reference voltage; generating a comparison signal based on a comparison result of comparing the level of the first input voltage with the level of the reference voltage; generating a result code corresponding to accumulated information of the comparison signal; generating a second output current based on the result code and a second input voltage; supplying power to an external device based on the first output current and the second output current; sensing at least one of the first output current and the second output current to generate current information; generating a feedback signal for adjusting a level of at least one of the first input voltage and the second input voltage based on the current information; and adjusting and outputting the level of the at least one of the first input voltage and the second input voltage based on the feedback signal.

15. The method of claim 14, wherein, The current information includes information on the second output current.

16. The method of claim 15, wherein, The step of generating the feedback signal for adjusting the level of the at least one of the first input voltage and the second input voltage based on the current information comprises: when the increase in the second output current exceeds a first threshold, generating the feedback signal for increasing the level of the first input voltage; and when the decrease in the second output current exceeds a second threshold, generating the feedback signal for decreasing the level of the first input voltage.

17. A display device comprising: a display panel configured to display an image; a power management integrated circuit configured to generate a first input voltage and a second input voltage; and a display driving circuit configured to generate gate signals to a plurality of gate lines and to generate data voltages to a plurality of data lines, wherein the display driving circuit comprises: a power module configured to provide power required for the display panel based on at least one of the first input voltage and the second input voltage, wherein the power module is configured to: generate a first current based on the first input voltage, generate a second current based on the first input voltage and the second input voltage when a drop of the first input voltage occurs, and ​ The first current and the second current are monitored to generate a feedback signal for adjusting a level of at least one of the first input voltage and the second input voltage based on at least one of the first current and the second current.

18. The display device of claim 17, wherein, The power module monitors that a period of the first current and the second current corresponds to a frame period in which the display panel displays an image.

19. The display device of claim 17, wherein, The power module generates a set of values obtained by sampling a level of the first current and a level of the second current, wherein a period of the sampling corresponds to a frame unit in which the display panel displays an image.

20. The display device of claim 17, wherein, The power management integrated circuit adjusts the level of the at least one of the first input voltage and the second input voltage to generate the first input voltage and the second input voltage, wherein a period of the level being adjusted corresponds to the frame period in which the display panel displays the image.

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