A server power-off control method and device, a terminal and a storage medium

By setting monitoring events in the input/output system of the ARM server and calling control commands of the UEFI and PSCI/SCMI protocols, the problem that the ARM server cannot be shut down by short-pressing the power button is solved, realizing convenient power control and saving user operation time.

CN115525133BActive Publication Date: 2026-02-06INSPUR SUZHOU INTELLIGENT TECH CO LTD
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Patent Information

Application Number
CN202211214526.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-09-30
Publication Date
2026-02-06
Estimated Expiration
2042-09-30

AI Technical Summary

Technical Problem

Because ARM servers do not support SMI interrupt types, they cannot be shut down by briefly pressing the power button, which makes operation inconvenient.

Method used

In the ARM server's input/output system, a monitoring event is set up. The power-off control function is called through the UEFI (Unique Fibre and Power Interface) on the microprocessor. The control command based on the Power State Coordination Interface (PSCI) protocol is sent to the microprocessor and converted into the System Control Management Protocol (SCMI) control command to perform the power-off operation of the server.

Benefits of technology

This implementation enables the ARM server to shut down via a short press of the power button, facilitating real-time shutdown for users during R&D and operation maintenance, and saving users time in manually shutting down the server.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application discloses a kind of server power off control method, device, terminal and storage medium, wherein the method is applied to ARM server, monitoring event is set in the input-output system of ARM server, whether power button is in pressing state is judged by monitoring event, and after determining that power button is in short press state, shutdown control function is called by the extensible firmware interface on microprocessor, to send the first control instruction based on power state coordination interface protocol PSCI to the microprocessor, and is converted into the second control instruction based on system control management protocol SCMI, so that server power executes shutdown operation according to the second control instruction.Using the above technical scheme, the shutdown function of short press of power button can be realized by monitoring event for ARM server, which is beneficial to the real-time shutdown demand of equipment during the development and operation and maintenance of ARM server, and saves the time of user operating server shutdown.
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Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server testing, and in particular to a server power-off control method and device, a terminal and a storage medium. BACKGROUND

[0002] The start, shutdown and restart operations of a server in a data center all need to be implemented quickly through a power button. At present, the power button function of most servers is by default implemented through a power signal to realize the start and shutdown actions of the server, and by default through a power distribution unit or a power supply unit to control the power-on or power-off of alternating current, thereby realizing the cycle power-on and power-off.

[0003] Due to the large size and large resource occupation of the server in the data center, during the usual research and development and operation and maintenance process, when a user has a power-off demand, manual plugging and unplugging needs to be performed on site, resulting in inconvenient operation. At present, some servers can be remotely controlled through the input / output system firmware connected with the server, but for an ARM (Advanced RISC Machine) server, since the ARM server generally does not support the SMI interrupt type, the ARM server cannot currently realize shutdown through short pressing of the power button, resulting in inconvenient operation of the ARM server. SUMMARY

[0004] In view of the above problems, the present application embodiments are proposed in order to provide a server power-off control method and a corresponding server power-off control device, terminal and storage medium which overcome the above problems or at least partially solve the above problems.

[0005] In order to solve the above problems, on the one hand, the present application embodiments disclose a server power-off control method applied to an ARM (Advanced RISC Machine) server, wherein the ARM server comprises a microprocessor and a power button, and the method comprises the following steps:

[0006] setting a monitoring event in an input / output system of the ARM server, wherein the monitoring event is whether the cumulative time length of the power button in a pressed state is less than a preset time threshold; the power button in the pressed state comprises that the power button is converted from a high level to a low level and then from the low level to the high level again;

[0007] monitoring whether the monitoring event occurs through the input / output system when the microprocessor is in a working state;

[0008] when it is monitored that the monitoring event occurs, determining that the power button is in a short pressed state, calling a shutdown control function through a UEFI (Unified Extensible Firmware Interface) on the microprocessor to send a first control instruction based on a PSCI (Power State Coordination Interface) to the microprocessor.

[0009] convert, by the microprocessor, the first control instruction into a second control instruction based on a system control management protocol (SCMI), and perform a shutdown operation of a server power supply according to the second control instruction.

[0010] Optionally, the ARM server comprises at least one mainboard and a bottom plate, the mainboard and the bottom plate are connected with a power supply of the server, the microprocessor is arranged on the mainboard, a bottom plate controller is arranged on the bottom plate, the bottom plate controller is connected with the power button, and the method further comprises:

[0011] When the bottom plate controller receives a server power supply power-off instruction, the bottom plate controller starts the power button, so that when the power button is in a pressed state.

[0012] Optionally, a timer is further arranged on the ARM server, and the timer is used to count a cumulative duration of the power button in the pressed state.

[0013] Optionally, the process of counting the cumulative duration of the power button in the pressed state comprises:

[0014] When the power button is converted from a high level to a low level, a first time when the timer starts timing is recorded;

[0015] After the timer starts timing, when the power button is converted from a low level to a high level, the timer stops timing, and a second time when the timer stops timing is recorded;

[0016] The cumulative duration between the first time and the second time is calculated.

[0017] Optionally, the preset time threshold is 3 seconds.

[0018] In another aspect, the embodiment of the application discloses a server power supply power-off control device applied to an ARM (Advanced RISC Machines) server, the ARM server comprising a microprocessor and a power button, and the device comprising:

[0019] A monitoring event creation module is configured to set a monitoring event in an input / output system of the ARM server, the monitoring event being whether a cumulative duration of the power button in a pressed state is less than a preset time threshold; the power button in the pressed state comprising that the power button is converted from a high level to a low level and then from a low level to a high level;

[0020] A monitoring event monitoring module is configured to monitor whether the monitoring event occurs through the input / output system when the microprocessor is in a working state.

[0021] The first data processing module is configured to determine that the power button is in a short pressing state when the monitoring event is monitored, and to call a shutdown control function through an extensible firmware interface (UEFI) on the microprocessor to send a first control instruction based on a power state coordination interface (PSCI) protocol to the microprocessor.

[0022] The second data processing module is configured to convert the first control instruction into a second control instruction based on a system control management protocol (SCMI) through the microprocessor, and to perform a shutdown operation of the server power supply according to the second control instruction.

[0023] Optionally, the ARM server comprises at least one mainboard and a bottom plate, the mainboard and the bottom plate are connected with the power supply of the server, the microprocessor is arranged on the mainboard, a bottom plate controller is arranged on the bottom plate, the bottom plate controller is connected with the power button, and the device further comprises:

[0024] The power button starting module is configured to start the power button by the bottom plate controller when the bottom plate controller receives a server power supply power-off instruction, so that the power button is in a pressing state.

[0025] Optionally, a timer is further arranged on the ARM server, and the timer is configured to count the cumulative duration of the power button in the pressing state.

[0026] Optionally, the monitoring event creating module comprises:

[0027] The first timing sub-module is configured to record a first time when the power button is converted from a high level to a low level.

[0028] The second timing sub-module is configured to end the timing of the timer and record a second time when the power button is converted from the low level to the high level after the timer starts timing.

[0029] The third timing sub-module is configured to calculate the cumulative duration between the first time and the second time.

[0030] Optionally, the preset time threshold is 3 seconds.

[0031] In another aspect, an embodiment of the present application further provides a terminal, which comprises a processor, a memory, and a computer program stored on the memory and capable of running on the processor, and the computer program is executed by the processor to implement the steps of the server power supply power-off control method.

[0032] In another aspect, the embodiment of the present application also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the server power-off control method.

[0033] The embodiment of the present application discloses a server power-off control method, which is applied to an ARM server, the ARM server comprising a microprocessor and a power button, a monitoring event is set in an input-output system of the ARM server, whether the power button is in a pressed state is judged through the monitoring event, and after it is determined that the power button is in a short-pressed state, a shutdown control function is called through an extensible firmware interface on the microprocessor to send a first control instruction based on a power state coordination interface protocol (PSCI) to the microprocessor through the shutdown control function and convert the first control instruction into a second control instruction based on a system control management protocol (SCMI), so that the server power performs a shutdown operation according to the second control instruction. By using the above technical scheme, the ARM server can realize the shutdown function of the short-pressed power button through the monitoring event, which is beneficial to the real-time shutdown requirement of the device during the research and development and operation and maintenance of the ARM server, saves the time of the user for operating the server to shut down, and is convenient for the user to use. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A step flow chart of a server power-off control method provided by the embodiment of the present application is provided.

[0035] Figure 2 A structure block diagram of a server power-off control device provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0036] In order to make the above objectives, features and advantages of the present application more apparent, further specific embodiments of the present application will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0037] At present, the power button function of most servers in a data center is realized by default through the GPD3_PWRBTN_N signal of the PCH to realize the power-on and power-off actions of the server. When the power of the server needs to be powered off, the power button is short pressed to trigger the power-off action, which is triggered by the SCI interrupt to trigger the system kernel to perform a soft power-off action. Long pressing the power button can trigger a hardware power-off action. When the server is in a non-operating system, short pressing the power button can also trigger the system power-off function. At this time, the triggering mechanism is triggered by the BIOS internally according to the GPD3_PWRBTN_N signal to trigger the system management interrupt (SMI) mechanism. The SMI interrupt mechanism is a hardware interrupt mechanism principle, that is, when the power button is short pressed, a hardware interrupt is generated to trigger the system management mode (SMM) of the BIOS internal SMI interrupt. The SMM program needs the CPU to enter the system management mode in advance. The specific operation process is that the CPU needs a memory area SMRAM. Before the CPU enters the SMM, the values of the registers are stored in the SMRAM, and then the program is jumped to the SMIENTRY POINT to execute, and after the processing is completed, the RSM instruction is used to jump back to the original place to continue execution, and the values of the CPU registers are restored. The SMM program will write the power-off value to the CPU internal register through the IO port to perform the power-off action after the server power button is short pressed.

[0038] At present, X86 processors or ARM (Advanced RISC Machine) processors are generally used in servers. The X86 processor refers to the central processor instruction set architecture based on Intel8086 and backward compatible, which supports the above-mentioned SMI interrupt mechanism. Compared with the X86 processor, the ARM processor has the advantages of multiple cores, small size, low power consumption, low cost and high performance, and the processing of the business will be more efficient and faster. Based on the above advantages, the server based on the ARM processor is more and more widely used. However, due to the small size of the ARM processor, it needs to rely on the external SCP firmware for startup and running. In order to ensure the safe startup of the ARM server, the SCP firmware of the ARM processor needs to be checked when the ARM server starts. For the ARM server, there is no BIOS firmware on the ARM server and it does not support the SMI interrupt type, so the ARM server cannot realize the power-off by short pressing the power button at present, which leads to the inconvenience of the ARM server operation.

[0039] In order to solve the problem that the ARM server cannot realize the power-off by short pressing the power button at present, Figure 1A flow chart of steps of a server power-off control method is provided for an embodiment of the present application. The method is applied to an ARM server, which includes a microprocessor and a power button. The method includes the following steps:

[0040] In step 101, a monitoring event is set in an input / output system of the ARM server. The monitoring event is whether the cumulative time length of the power button in a pressed state is less than a preset time threshold. The power button in the pressed state includes the power button being converted from high level to low level and then from low level to high level.

[0041] The input / output system can be a BIOS system (Basic Input Output System). A BIOS code is used to create the monitoring event on the input / output system. Specifically, a signal acquisition circuit can be provided in the ARM server. The signal acquisition circuit is connected with the power button and is used to acquire a level signal output by the power button. In the embodiment of the present application, the signal acquisition circuit can be an ADC acquisition circuit. For example, the model of the ADC acquisition circuit can be LTC2440.

[0042] In use, the microprocessor is connected with the signal acquisition circuit. The microprocessor is used to analyze the voltage signal acquired by the signal acquisition circuit and determine the use state of the power button. The power button can have a high level state and a low level state. The power button in the pressed state can include the power button being converted from high level to low level and then from low level to high level, or the power button being converted from low level to high level and then from high level to low level.

[0043] The ARM server is also provided with a timer, which is used to count the cumulative time length of the power button in the pressed state after determining that the power button is in the pressed state. The process of calculating the cumulative time length of the power button in the pressed state can include: when the power button is converted from high level to low level, the first time when the timer starts timing is recorded; after the timer starts timing, when the power button is converted from low level to high level, the timer stops timing, and the second time when the timer stops timing is recorded; the cumulative time length between the first time and the second time is calculated. In this embodiment, the preset time threshold can be 3 seconds. When the cumulative time length of the power button in the pressed state is less than 3 seconds, it is considered that the power button is in the short press state. When the cumulative time length of the power button in the pressed state is greater than or equal to 3 seconds, it is considered that the power button is in the long press state. It should be noted that generally the high level of the power button is the normal state, and the low level of the power button is the pressed state. Of course, the user can also set it as the default power button low level as the normal state and the power button high level as the pressed state. At the same time, the user can set the preset time threshold according to the power control demand of the user, and the specific value of the preset time threshold is not limited in the application.

[0044] Step 102, monitoring whether the monitoring event occurs through the input and output system when the microprocessor is in the working state;

[0045] When the microprocessor is in the working state, the level signal of the power button can be switched between the high level signal and the low level signal. In the process of monitoring and recording the level use state of the power button, the input and output system judges whether the monitoring event occurs.

[0046] Step 103, when it is monitored that the monitoring event occurs, it is determined that the power button is in the short press state, and a shutdown control function is called through the extensible firmware interface (UEFI) on the microprocessor to send a first control instruction based on the power state coordination interface protocol (PSCI) to the microprocessor;

[0047] After it is determined that the power button is in the short press state, a shutdown control function is called through the UEFI (Unified Extensible Firmware Interface). The shutdown control function can be an SMC function, the power management protocol can be a power state coordination interface protocol (PSCI), and the PSCI is a power management interaction protocol between Linux and ATF, which can be used for power management. The extensible firmware interface on the microprocessor calls the SMC function to send the first control instruction based on the PSCI to the microprocessor through the SMC function.

[0048] In step 104, the microprocessor converts the first control instruction into a second control instruction based on a system control and management interface (SCMI) protocol, and performs a shutdown operation of the server power supply according to the second control instruction.

[0049] The microprocessor converts the first control instruction into a system control and management interface (SCMI) protocol, so that the server power supply performs a shutdown operation of the server power supply according to the second control instruction. The application processor on the ARM server includes an operating system (OSPM) and a PSCI power management component (PSCICPUpowerdomains), wherein the OSPM includes a processor power (CPUPOWER), a device performance (DeviceorCPUperformance), a device power domain (Devicepowerdomains) and a sensor (Sensors), the CPUPOWER is connected with the SCMI through the PSCICPUpowerdomains, the DeviceorCPUperformance, the Devicepowerdomains and the Sensors are all connected with the SCMI, and the DeviceorCPUperformance, the Devicepowerdomains and the Sensors all interact with the system processor through the SCMI protocol. The PSCI is a power management interaction protocol between Linux and ATF, and can be used for power management. The microprocessor executes a PSCI_SYSTEM_OFF instruction, and controls the server power supply through the SCMI protocol. The SCMI protocol includes a protocol layer and a transmission layer. The protocol layer is used for describing supported commands, and the transmission layer defines a transmission mode of the commands, so as to realize the shutdown operation of the server power supply.

[0050] It should be noted that the SMC function can pass a PSCI protocol shutdown instruction PSCI_SYSTEM_OFF to the microprocessor. The microprocessor executes the PSCI_SYSTEM_OFF instruction, and controls the server power supply through the SCMI protocol. The SCMI protocol includes a protocol layer and a transmission layer. The protocol layer is used for describing supported commands, and the transmission layer defines a transmission mode of the commands, so as to realize the shutdown operation of the server power supply, thereby realizing the shutdown function in the setup interface and the Shell of the input and output system.

[0051] The embodiment of the application discloses a server power-off control method, which is applied to an ARM server, the ARM server comprising a microprocessor and a power button, a monitoring event is set in an input-output system of the ARM server, whether the power button is in a pressing state is judged through the monitoring event, and after it is determined that the power button is in a short pressing state, a shutdown control function is called through an extensible firmware interface on the microprocessor, a first control instruction based on a power state coordination interface protocol (PSCI) is sent to the microprocessor, and the first control instruction is converted into a second control instruction based on a system control management protocol (SCMI), so that the server power performs a shutdown operation according to the second control instruction. By adopting the technical scheme, the ARM server can realize the shutdown function of the short pressing of the power button through the monitoring event, which is beneficial to the real-time shutdown requirement of the equipment during the research and development and operation and maintenance of the ARM server, saves the time of the user for operating the server to be shut down, and is convenient for the use of the user.

[0052] At present, servers are very common in life and are widely used in the education industry, the financial industry, the telecommunication industry, the military and political industry and the like. The server in the network era plays an increasingly important role. In the daily use process, the server is generally autonomously operated, but when the server has a running fault, the server needs to be managed and maintained. In order to reduce the loss of the server and improve the service life of the server, the power button function of most servers is by default realized through a power signal to realize the power-on and power-off actions of the server, and by default, the power-on and power-off actions of the server are realized through a power distribution unit or a power distribution unit to control the power-on or power-off of alternating current, so as to realize the cycle power-on and power-off. In the process of managing and maintaining the server, if the user goes to the scene, a large amount of time cost and transportation cost will be consumed. When the number of servers is large, such as the servers in a data center, the number of servers can be as high as several hundred to several thousand, and the power-on and power-off actions of the servers are realized through manual operation, which needs to consume a large amount of time.

[0053] In some embodiments, the real-time and long-distance transmission function of the Internet provides a good platform for us. Based on the TCP / IP protocol, control signals can be transmitted to all over the world through the Internet. If the information of a computer can be transmitted to a remote control terminal in real time through a device, the management of a remote server can be the same as the on-site control of each server. In order to solve the problem of time-consuming power management of the server, the embodiment of the application remotely controls the controlled terminal through the control terminal. The controlled terminal is arranged on the ARM server, and a control program is arranged on the controlled terminal, and the control program is fixed in the embedded system of the ARM server of the control terminal. When the ARM embedded system is controlled through the control terminal, a very complex operation is not needed, and the WEB-based control platform of the ARM embedded system can be entered through the network. For example, the ARM server includes at least one group of mainboards and backplanes, the mainboards and the backplanes are connected with the power supply of the server, a microprocessor is arranged on the mainboard, a backplane controller is arranged on the backplane, and the backplane controller is connected with the power button. When a user needs to perform remote power-off operation, the control terminal establishes a control link with the controlled terminal through the IP address of the control device connected with the controlled terminal, and sends the operation instructions of the mouse and the keyboard of the control terminal to the backplane controller. The network card module of the backplane controller acquires the operation instructions and sends them to the processor for processing. The control terminal sends a power-off instruction to the backplane controller in the ARM server, and when the backplane controller receives the server power-off instruction, the backplane controller starts the power button, so that the power button is in a pressed state. It should be noted that the embodiment of the application does not have special requirements for the control terminal, and only requires a browser and the ability to remotely connect with the controlled terminal, so that the remote control can be performed through any networked computer at any time and anywhere. The embodiment of the application supplies power to the backplane controller through an external power supply, so that the backplane controller can operate independently of the state of the controlled terminal. Whether the power supply of the controlled terminal works or not, the ARM embedded system on the backplane controller can operate. Even if the controlled terminal cannot automatically restart in the case of abnormal power failure, the controlled terminal can be cold-started through the remote control terminal. The embodiment of the application sets a BMC module on the control device, connects the controlled terminal through an IPMB interface, and feeds back the running information of the mainboard of the ARM server to the management personnel of the control terminal. By using the above technical solution, the user can remotely control the power supply of the ARM server through the control terminal, which saves the time of the management personnel and improves the control efficiency.

[0054] In some embodiments, the ARM server is running and has a control system to maintain the server when support is needed, which can be achieved by remote management software. The management of the server cannot only stop at the level of the operating system, but also allows its upper layer software to communicate with the hardware layer through a certain standard from the bottom layer, and more complete and transparent management of the server. Intelligent Platform Management Interface (IPMI) is derived from the server field, and its purpose is to provide device management, sensor event management, user management, remote maintenance and other functions for servers. IPMI has the characteristics of standardization, separation of management channel and service channel, rich command set, security, etc. The feature of separation of management channel and service channel of IPMI makes IPMI have high applicability, makes the power supply of IPMI subsystem independent, makes IPMI not dependent on the business management system, and even in the case of business system failure, it still has operability. Moreover, IPMI is an intelligent management platform interface based on Internet, and the core of IPMI is a server processor or a baseboard management controller (BMC), which does not depend on the server processor, BIOS or operating system to work. The baseboard management controller can be a separate agentless management subsystem running in the system. As long as there is a BMC and IPMI firmware, it can start to work, and the BMC chip can be set on the mainboard of the ARM server, and the BMC provides IPMI support for the server mainboard. The good autonomous feature of IPMI overcomes the limitations of the previous management mode based on the operating system, for example, it can still perform operations such as power on / off, information extraction, etc. in the case of non-response or non-loading of the operating system.

[0055] In some embodiments, the server power input is generally 220V alternating current, and the 220V alternating current is connected to the server power input through the power line. Inside the server power, the 220V alternating current is converted into two kinds of direct current, P12V_main and P12V_STBY. Both of these two kinds of electricity are 12V voltage, the difference is that P12V_main provides larger current, and in addition, P12V_main needs to receive a power enable signal to convert the system main power into voltage for other chips or components. The current provided by P12V_STBY is smaller, and P12V_STBY automatically outputs voltage after the AC line is inserted, without power enable signal control.

[0056] It should be noted that, for the method embodiments, the series of acts complement each other to achieve the purpose of this embodiment, therefore, this embodiment is not limited to the order of the acts of the methods described. Secondly, those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the acts involved are not necessarily the necessary acts of the embodiments.

[0057] In order to realize the above-mentioned server power-off control method, Figure 2 The application provides a structural block diagram of a server power-off control device, which is applied to an ARM server and comprises:

[0058] A monitoring event creation module 201 is configured to set a monitoring event in an input / output system of the ARM server, and the monitoring event is whether the cumulative time length of the power button in a pressed state is less than a preset time threshold; the power button in the pressed state comprises that the power button is converted from high level to low level and then from low level to high level;

[0059] A monitoring event monitoring module 202 is configured to monitor whether the monitoring event occurs through the input / output system when the microprocessor is in a working state;

[0060] A first data processing module 203 is configured to determine that the power button is in a short press state when the monitoring event is monitored to occur, and call a shutdown control function through an UEFI on the microprocessor to send a first control instruction based on a PSCI to the microprocessor;

[0061] A second data processing module 204 is configured to convert the first control instruction into a second control instruction based on a SCMI through the microprocessor, and perform a server power-off operation according to the second control instruction.

[0062] The embodiment of the application discloses a server power-off control device, which is applied to an ARM server, the ARM server comprises a microprocessor and a power button, a monitoring event is arranged in an input / output system of the ARM server, whether the power button is in a pressing state is judged through the monitoring event, after it is determined that the power button is in a short pressing state, a shutdown control function is called through an extensible firmware interface on the microprocessor, a first control instruction based on a power state coordination interface protocol (PSCI) is sent to the microprocessor, and a second control instruction based on a system control management protocol (SCMI) is converted, so that the server power performs a shutdown operation according to the second control instruction. By adopting the technical scheme, the ARM server can realize the shutdown function of the short pressing of the power button through the monitoring event, which is beneficial to the real-time shutdown requirement of the equipment during the research and development and operation and maintenance of the ARM server, saves the time of the user for operating the server to shut down, and is convenient for the use of the user.

[0063] In an alternative embodiment, the ARM server comprises at least one mainboard and a bottom plate, the mainboard and the bottom plate are connected with the power supply of the server, the microprocessor is arranged on the mainboard, a bottom plate controller is arranged on the bottom plate, the bottom plate controller is connected with the power button, and the device further comprises:

[0064] A power button starting module is configured to start the power button by the bottom plate controller when the bottom plate controller receives a server power-off instruction, so that the power button is in a pressing state.

[0065] In an alternative embodiment, a timer is further arranged on the ARM server, and the timer is configured to count the cumulative duration of the power button in the pressing state.

[0066] In an alternative embodiment, the monitoring event creation module 201 can comprise:

[0067] A first timing sub-module is configured to record a first time when the power button is converted from a high level to a low level.

[0068] A second timing sub-module is configured to end the timing of the timer and record a second time when the power button is converted from a low level to a high level after the timer starts timing.

[0069] A third timing sub-module is configured to calculate the cumulative duration between the first time and the second time.

[0070] In an optional embodiment, the shutdown control function is an SMC function, the power management protocol is a power state coordination interface protocol PSCI, and the first data processing module 203 can further be configured to invoke the SMC function through an extensible firmware interface on the microprocessor, and send the first control instruction based on the PSCI to the microprocessor through the SMC function, and the microprocessor converts the first control instruction into a second control instruction based on a system control management protocol SCMI, so that the server power performs a shutdown operation of the server power according to the second control instruction.

[0071] In an optional embodiment, the preset time threshold is 3 seconds.

[0072] In an optional embodiment, the ARM server is further provided with a controlled terminal, which is connected with a controlling terminal through a network and receives a control instruction sent by the controlling terminal.

[0073] In an optional embodiment, the controlled terminal is arranged on a baseboard controller of the bottom plate.

[0074] In another aspect, the embodiments of the present application further provide a terminal, which comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, and the computer program implements the steps of the server power shutdown control method when executed by the processor. The memory is used for storing execution instructions and can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as a static access memory (SRAM), an erasable programmable read-only memory (EPROM) and the like. The processor is a control center of the storage terminal, links all parts of the electronic terminal through various interfaces and lines, runs software programs in the memory to call data in the memory, so as to execute the functions of the electronic terminal, such as an integrated circuit (Integrated Circuit). The communication unit is used for establishing a communication channel, so that the storage terminal and other terminals can communicate, receive or send data and the like.

[0075] In another aspect, the embodiments of the present application further provide a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the server power shutdown method when executed by a processor.

[0076] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between each embodiment can be referred to each other.

[0077] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0078] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0079] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0081] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0082] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0083] The above describes in detail the method and device of the server power supply power failure control provided by the present application, and the principles and implementation modes of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A server power failure control method, characterized in that, An application is made to a server employing the Advanced Reduced Instruction Set Computing (ARM) architecture. The ARM server includes a microprocessor, a power button, and at least one motherboard and a baseboard. Both the motherboard and the baseboard are connected to the server's power supply. The microprocessor is mounted on the motherboard, and a baseboard controller is mounted on the baseboard and connected to the power button. The method includes: A monitoring event is set in the input / output system of the ARM server. The monitoring event is whether the cumulative duration of the power button being pressed is less than a preset time threshold. The power button being pressed includes the power button changing from a high level to a low level and then changing from a low level to a high level. When the microprocessor is in operation, the input / output system monitors whether the monitoring event has occurred. When the monitoring event is detected, it is determined that the power button is in a short press state. The power-off control function is called through the UEFI (Unique Fibre and Power Interface) on the microprocessor to send the first control command based on the Power State Coordination Interface Protocol (PSCI) to the microprocessor. The microprocessor converts the first control instruction into a second control instruction based on the System Control Management Protocol (SCMI), and performs a power-off operation on the server according to the second control instruction. The System Control Management Protocol (SCMI) includes a protocol layer and a transport layer. The protocol layer is used to define the second control instruction, and the transport layer is used to define the transmission method of the second control instruction. When the baseboard controller receives a power-down command from the server, it activates the power button so that the power button is pressed.

2. The method according to claim 1, characterized in that, The ARM server is also equipped with a timer, which is used to count the cumulative duration of the power button being in the pressed state.

3. The method according to claim 2, characterized in that, The process of calculating the cumulative duration of the power button being in the pressed state includes: When the power button changes from a high level to a low level, record the first time when the timer starts counting. After the timer starts counting down, when the power button changes from a low level to a high level, the timer stops counting down, and the second time when the timer stops counting down is recorded. Calculate the cumulative duration between the first time and the second time.

4. The method according to claim 1, characterized in that, The preset time threshold is 3 seconds.

5. A server power failure control device, characterized in that, An application is provided for an Advanced Reduced Instruction Set Computing (ARM) server. The ARM server includes a microprocessor, a power button, and at least one motherboard and a baseboard. Both the motherboard and the baseboard are connected to the server's power supply. The microprocessor is mounted on the motherboard, and a baseboard controller is mounted on the baseboard and connected to the power button. The device includes: The monitoring event creation module is used to set monitoring events in the input / output system of the ARM server. The monitoring event is whether the cumulative duration of the power button being pressed is less than a preset time threshold. The power button being pressed includes the power button changing from a high level to a low level and then from a low level to a high level. The monitoring event monitoring module is used to monitor whether the monitoring event has occurred through the input / output system when the microprocessor is in working state; The first data processing module is used to determine that the power button is in a short-press state when the monitoring event is detected, and to call the power-off control function through the UEFI (Unique Fibre and Power Interface) on the microprocessor to send the first control command based on the Power State Coordination Interface Protocol (PSCI) to the microprocessor. The second data processing module is used to convert the first control instruction into a second control instruction based on the System Control Management Protocol (SCMI) through the microprocessor, and to perform a power-off operation on the server according to the second control instruction; the System Control Management Protocol (SCMI) includes a protocol layer and a transport layer, the protocol layer is used to define the second control instruction, and the transport layer is used to define the transmission method of the second control instruction; The power button activation module is used to activate the power button when the baseboard controller receives a power-down command from the server, so that the power button is in the pressed state.

6. The apparatus according to claim 5, characterized in that, The monitoring event creation module includes: The first timing submodule is used to record the first time when the power button changes from a high level to a low level; The second timing submodule is used to stop the timer from timing when the power button changes from low level to high level after the timer starts timing, and to record the second time when the timer ends timing; The third timing submodule is used to calculate the cumulative duration between the first time and the second time.

7. A terminal, characterized in that, include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the method as described in any one of claims 1-4.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of the method as described in any one of claims 1-4.

Citation Information

Patent Citations

  • ARM server power key shutdown method and system, terminal and storage medium

    CN112230753A