Memory failure processing method, apparatus and device

Abstract

Embodiments of the present application provide a memory fault processing method, device and equipment, the method comprising: obtaining first fault information of a fault occurred in a memory; determining a first memory address according to the first fault information, the memory at the first memory address being a first memory; isolating the first memory when it is determined that the first memory is in a fault state. Through the above method, false positives of memory faults of a computer system can be avoided, thereby reducing the repair cost of memory faults and saving memory repair resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a memory fault processing method, device and equipment. BACKGROUND

[0002] The memory fault prediction and repair system can process memory faults. The memory fault prediction and repair system can include a prediction module and a self-recovery module.

[0003] The prediction module can obtain fault errors of the memory, determine fault decision information according to the fault errors, and send the fault decision information to the self-recovery module. The self-recovery module can report the fault decision information to the computer system to enable the computer system to self-recover the fault position.

[0004] In the above fault prediction and repair method, when an error occurs at a certain position of the memory, the prediction module receives a large amount of error information at the position in a short time, and determines repeated fault decision information according to the error information. Therefore, the self-recovery module repeatedly receives a large amount of same fault decision information in a short time, and can repeatedly report a large amount of same fault decision information to the computer system. However, for any fault position, when the fault position has been successfully self-recovered, and the computer system receives the fault decision information at the fault position again, the computer system will mistakenly report that the fault position fails to be self-recovered, and request manual repair, thereby wasting memory repair resources and causing high memory fault repair cost.

[0005] Therefore, how to avoid the false report of the computer system and reduce the memory fault repair cost becomes a problem to be solved. SUMMARY

[0006] The present application provides a memory fault processing method, device and equipment, which can avoid the false report of the computer system on the memory fault, thereby reducing the repair cost of the memory fault and saving the memory repair resources.

[0007] In a first aspect, the present application provides a memory fault processing method, comprising:

[0008] Obtaining first fault information of a fault occurred in a memory;

[0009] Determining a first memory address according to the first fault information, wherein the memory at the first memory address is a first memory;

[0010] Isolating the first memory when it is determined that the first memory is in a fault state.

[0011] In the technical solution, the first memory address can be determined according to the first fault information of the memory that has occurred a fault, and the memory at the first memory address is the first memory. The memory state of the first memory can be determined, and the first memory can be isolated when the first memory is in a fault state. Through the technical solution, the computer system can be prevented from falsely reporting a memory fault, thereby reducing the repair cost of the memory fault and saving the memory repair resources.

[0012] In a possible implementation, when it is determined that the first memory is in a fault state, the first memory is isolated, including:

[0013] The memory state of the first memory is determined according to the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses, and the memory state is a fault state or a non-fault state.

[0014] When it is determined that the memory state of the first memory is a fault state, the first memory is isolated.

[0015] The technical solution can determine the state of the first memory and isolate the first memory when the first memory is in a fault state. The non-fault memory is prevented from being processed, and the computer system is prevented from falsely reporting a memory fault.

[0016] In a possible implementation, the memory state of the first memory is determined according to the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses, including:

[0017] The upper-level memory address corresponding to the first memory address is determined.

[0018] The memory state of the first memory is determined according to the first memory address, the upper-level memory address, and the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses.

[0019] The technical solution can determine the memory state of the first memory, so as to isolate the first memory according to the memory state of the first memory.

[0020] In a possible implementation, the memory state of the first memory is determined according to the first memory address, the upper-level memory address, and the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses, including:

[0021] If the storage space does not include the first memory address and the upper-level memory address, the memory state of the first memory is determined to be a fault state; or

[0022] If the storage space includes the first memory address, the memory state of the first memory is determined according to the repair result corresponding to the first memory address; or

[0023] If the upper memory address is included in the storage space, a memory state of the first memory is determined according to a repair result corresponding to the upper memory address.

[0024] The above technical solution can determine the memory state of the first memory according to the first memory address and / or the upper memory address, or according to the repair result corresponding to the first memory address / upper memory address, thereby achieving the purpose of determining the memory state of the first memory before processing the first memory.

[0025] In a possible implementation, the memory state is determined according to the repair result corresponding to the first memory address, including:

[0026] If the repair result corresponding to the first memory address is repair success, the memory state of the first memory is a non-fault state; or,

[0027] If the repair result corresponding to the first memory address is repair failure, the memory state of the first memory is a fault state.

[0028] The above technical solution can determine the memory state of the first memory according to the repair result corresponding to the first memory address, thereby achieving the purpose of determining the memory state of the first memory.

[0029] In a possible implementation, the memory state of the first memory is determined according to the repair result corresponding to the upper memory address, including:

[0030] If the repair result corresponding to the upper memory address is repair success, the memory state of the first memory is a non-fault state; or,

[0031] If the repair result corresponding to the upper memory address is repair failure, the memory state of the first memory is a fault state.

[0032] The above technical solution can determine the memory state of the first memory according to the repair result corresponding to the upper memory address, thereby achieving the purpose of determining the memory state of the first memory.

[0033] In a possible implementation, after isolating the memory at the first memory address, the method further includes:

[0034] Obtaining a first repair result of the first memory;

[0035] Storing the first memory address and the first repair result corresponding to the first memory address to the storage space.

[0036] The above technical solution can store the first memory address and the first repair result, so as to facilitate determining the memory state before processing the memory fault.

[0037] In a second aspect, the present application provides a memory fault processing apparatus, the apparatus comprising an obtaining module, a predicting module and a self-recovery module, wherein,

[0038] The obtaining module is configured to obtain first fault information of a fault that has occurred in a memory.

[0039] The predicting module is further configured to determine a first memory address according to the first fault information, the memory at the first memory address being a first memory.

[0040] The self-recovery module is configured to isolate the first memory when the determining module determines that the first memory is in a fault state.

[0041] In the above technical solution, the first memory address can be determined according to the first fault information of a fault that has occurred in a memory, and the memory state of the first memory can be determined, and the first memory can be isolated when the first memory is in a fault state. Through the above technical solution, the computer system can be prevented from falsely reporting a memory fault, thereby reducing the repair cost of a memory fault and saving memory repair resources.

[0042] In a possible implementation, the self-recovery module is specifically configured to,

[0043] determine the memory state of the first memory according to the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses, the memory state being a fault state or a non-fault state;

[0044] isolate the first memory when it is determined that the memory state of the first memory is a fault state.

[0045] The above technical solution can determine the state of the first memory and isolate the first memory when the first memory is in a fault state. This avoids processing the memory in a non-fault state and thereby avoids the computer system falsely reporting a memory fault.

[0046] In a possible implementation, the self-recovery module is specifically configured to,

[0047] determine a superior memory address corresponding to the first memory address;

[0048] determine the memory state of the first memory according to the first memory address, the superior memory address, and the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses.

[0049] The above technical solution can determine the memory state of the first memory, so as to isolate the first memory according to the memory state of the first memory.

[0050] In a possible implementation, the self-recovery module is specifically configured to,

[0051] If the first memory address and the upper memory address are not included in the storage space, the memory state of the first memory is determined as a failure state; or,

[0052] If the first memory address is included in the storage space, the memory state of the first memory is determined according to the repair result corresponding to the first memory address; or,

[0053] If the upper memory address is included in the storage space, the memory state of the first memory is determined according to the repair result corresponding to the upper memory address.

[0054] The above technical solution can determine the memory state of the first memory according to the first memory address and / or the upper memory address, or according to the repair result corresponding to the first memory address / upper memory address, thereby achieving the purpose of determining the memory state of the first memory before processing the first memory.

[0055] In a possible implementation, the self-recovery module is specifically configured to,

[0056] If the repair result corresponding to the first memory address is successful, the memory state of the first memory is a non-failure state; or,

[0057] If the repair result corresponding to the first memory address is a failure, the memory state of the first memory is a failure state.

[0058] The above technical solution can determine the memory state of the first memory according to the repair result corresponding to the first memory address, thereby achieving the purpose of determining the memory state of the first memory.

[0059] In a possible implementation, the self-recovery module is specifically configured to,

[0060] If the repair result corresponding to the upper memory address is successful, the memory state of the first memory is a non-failure state; or,

[0061] If the repair result corresponding to the upper memory address is a failure, the memory state of the first memory is a failure state.

[0062] The above technical solution can determine the memory state of the first memory according to the repair result corresponding to the upper memory address, thereby achieving the purpose of determining the memory state of the first memory.

[0063] In a possible implementation, the memory failure processing apparatus further includes a storage module, wherein,

[0064] The acquisition module is further configured to acquire a first repair result of the first memory.

[0065] The storage module is configured to store the first memory address and the first repair result correspondingly in the storage space.

[0066] The above technical solution can store the first memory address and the first repair result, so as to determine the memory state before processing the memory fault.

[0067] In a third aspect, the present application provides a memory fault processing device, comprising a processor and a memory connected with the processor in communication;

[0068] The memory stores a computer program.

[0069] The processor executes the computer program to implement the method according to any one of the first aspect.

[0070] In the above technical solution, the first memory address can be determined according to the first fault information of the memory that has occurred a fault, and the memory at the first memory address is the first memory. The memory state of the first memory can be determined, and the first memory can be isolated when the first memory is in a fault state. Through the above technical solution, the computer system can be prevented from misreporting the memory fault, thereby reducing the repair cost of the memory fault and saving the memory repair resources.

[0071] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program. The computer program is executed by a computer to implement the method according to any one of the first aspect.

[0072] In the above technical solution, the first memory address can be determined according to the first fault information of the memory that has occurred a fault, and the memory at the first memory address is the first memory. The memory state of the first memory can be determined, and the first memory can be isolated when the first memory is in a fault state. Through the above technical solution, the computer system can be prevented from misreporting the memory fault, thereby reducing the repair cost of the memory fault and saving the memory repair resources. BRIEF DESCRIPTION OF DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0074] Figure 1 A memory structure diagram is provided for the embodiments of the present application.

[0075] Figure 2 A memory collection schematic diagram provided for an embodiment of the present application;

[0076] Figure 3 A computer system architecture schematic diagram provided for an embodiment of the present application;

[0077] Figure 4 A memory fault processing method in the related art;

[0078] Figure 5 A memory fault processing schematic diagram provided for an embodiment of the present application;

[0079] Figure 6 A flowchart schematic diagram of a memory fault processing method provided for an embodiment of the present application;

[0080] Figure 7 A flowchart schematic diagram of a method for judging a memory state provided for an embodiment of the present application;

[0081] Figure 8 A flowchart schematic diagram of another memory fault processing method provided for an embodiment of the present application;

[0082] Figure 9 A structure schematic diagram of a memory fault processing apparatus provided for an embodiment of the present application;

[0083] Figure 10 A structure schematic diagram of another memory fault processing apparatus provided for an embodiment of the present application;

[0084] Figure 11 A hardware structure schematic diagram of a memory fault processing device provided for the present application. DETAILED DESCRIPTION

[0085] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals refer to like elements, unless the context of use indicates otherwise. The following description of exemplary embodiments is not representative of all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0086] It should be noted that the terms "comprising", "containing", or any other similar words in this document are intended to encompass non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0087] The present application relates to a memory structure, in order to facilitate the understanding of the embodiments of the present application, first in combination Figures 1-2 , through specific examples, the structure of the memory is described in detail.

[0088] Figure 1 A memory structure diagram is provided for the embodiments of the present application. Please refer to Figure 1 , the memory 1 includes 2 ranks, which are rank 0 and rank 1.

[0089] For any one of the above ranks, the rank includes a plurality of devices. Please refer to Figure 1 Take rank 1 of memory 1 as an example, rank 1 includes device 0, device 1, …, device 6 and device 7.

[0090] Optionally, rank 1 can also include error checking and correction (ECC) devices.

[0091] It should be understood that electric field, magnetic field or other interference will cause the change of single bit value in the memory. The change of single bit value may cause the byte garbled code which is very important for the computer system to run, so that the computer system is down or other failures. The ECC device can check and correct the change of single bit value in the memory, so as to avoid the computer system failure caused by the change of single bit value, and ensure the stability and reliability of the computer system.

[0092] For any one of the above devices, the device includes a plurality of banks. Please refer to Figure 1 Take device 2 in rank 1 as an example, device 2 includes bank 0, bank 1, …, bank 14 and bank 15.

[0093] For any one of the above banks, the bank is a storage array. Please refer to Figure 1 Take bank 1 of device 2 in rank 1 as an example, bank 1 includes a plurality of storage units, which can be arranged in an array. A storage unit can be uniquely determined by row address and column address.

[0094] For any of the above storage units, the storage unit includes several bit locations. Please refer to [link to relevant documentation]. Figure 1 Taking x8 memory as an example, a storage unit can include 8 bit positions, which are bit 1, bit 2... bit 7 and bit 8 from left to right.

[0095] In the memory structure described above, a physical region in memory can be determined by any face number, particle number, block number, row number, column number, storage cell number, or bit number. This number is the physical address of the corresponding physical region.

[0096] For any two physical addresses, if the physical region corresponding to physical address A falls within the physical region corresponding to physical address B, then physical address A is a subset of physical address B. In this case, physical address A is a sub-memory address of physical address B, and physical address B is the parent memory address of physical address A.

[0097] For example, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a memory collection provided in an embodiment of this application. Please refer to [link / reference]. Figure 2 Based on the order of the corresponding physical regions from largest to smallest, the memory structure can be in the following order: memory, face, particle, block, row / column, and storage unit. For any face, all particles within that face are subsets of that face; that is, the particle address of a particle is a sub-memory address of the face address, and the face address is the parent memory address of the particle address.

[0098] Assuming physical address A is: channel 1-memory 0-face 2-particle 6-array 0-row 11, and physical address B is: channel 1-memory 0-face 2-particle 6-array 0, then physical address A is a sub-memory address of physical address B, and physical address B is the parent memory address of physical address A.

[0099] To facilitate understanding, the following will be combined with Figure 3 The computer system architecture involved in the embodiments of this application will be described.

[0100] Figure 3 This is a schematic diagram of a computer system architecture provided for an embodiment of this application. Figure 3 As shown, the computer system 300 includes: a processor 301, underlying firmware 302, a management unit 303, and several memory units.

[0101] Processor 301 can repair the memory in computer system 300. Processor 301 can be the control center of computer system 300. For example, processor 301 can be a central processing unit (CPU).

[0102] The processor 301 includes a memory controller 304. The memory controller 304 can interact with the ECC granules of the memory to obtain memory fault information of the corresponding memory from the ECC granules. For example, the memory fault information can be the state of each bit on the memory. The state of each bit on the memory can be a normal state or an error state.

[0103] The underlying firmware 302 can obtain the memory fault information from the memory controller 304, and can send the memory fault information to the management unit 303. The underlying firmware 302 can also obtain the memory address at the memory that needs to be repaired from the management unit 303, and send the memory address to the processor 301, so that the processor 301 can repair the memory at the memory address. For example, the underlying firmware 302 can be a Basic Input / Output System (BIOS), or a Unified Extensible Firmware Interface (UEFI) firmware, etc.

[0104] The management unit 303 can include a memory fault prediction and self-recovery management system 305 to facilitate analysis and prediction of memory faults. The management unit 303 communicates with the underlying firmware 302 through a dedicated interface. The management unit 303 can be a management module of non-service modules in the computer system 300. For example, the management unit 303 can be a Baseboard Management Controller (BMC).

[0105] The memory fault prediction and self-recovery management system 305 can include a prediction module 306 and a self-recovery module 307.

[0106] The prediction module 306 can receive the memory fault information sent by the underlying firmware 302, and perform fault prediction and analysis according to the memory fault information to obtain the memory address at the memory that needs to be repaired. The prediction module 306 can also send the memory address at the memory that needs to be repaired to the self-recovery module 307.

[0107] The self-recovery module 307 can receive the memory address sent by the prediction module 306, and forward the memory address to the underlying firmware 302.

[0108] It can be understood that the computer system illustrated in the embodiments of the present application does not constitute a specific limitation on the computer system 300. The computer system 300 can include more or fewer components than illustrated, or combine certain components, or split certain components, or different arrangement of components. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0109] In the following, the embodiments of the present application will be described in detail with reference to the drawings.Figure 4 An example is shown in a memory fault processing method.

[0110] Figure 4 A memory fault processing method in the related art is provided. Figure 4 As shown, the underlying firmware can collect error information of the memory in the computer system, and can send the error information to the prediction module. The prediction module can analyze the memory fault according to the received error information, determine the fault location of the memory, obtain the fault address, and can send the fault address to the self-healing module. After receiving the fault address, the self-healing module can forward the fault address to the underlying firmware. After receiving the fault address, the underlying firmware can forward the fault address to the processor. The processor can isolate and repair the memory at the fault location according to the received fault address.

[0111] When the above method is used to process the memory fault, for any fault address, when the processor has successfully repaired the memory corresponding to the fault address, if the computer system receives the fault address sent by the prediction module again, it will cause the computer system to falsely report that the memory corresponding to the fault address has failed and request manual repair. However, when an error occurs at a certain location in the memory, the prediction module will receive a large amount of error information at the location within a short time, and determine a plurality of repeated fault addresses according to the error information. This causes the self-healing module to repeatedly receive the same fault address within a short time, and can repeatedly report a large amount of the same fault address to the computer system. Therefore, the above method can cause the computer system to have a high false reporting rate of faults, waste memory repair resources, and result in a high cost of repairing the memory fault.

[0112] To solve the above technical problems, the embodiment of the present application provides a memory fault processing method. As shown in Figure 5 , Figure 5 is a memory fault processing diagram provided by the embodiment of the present application.

[0113] Please refer to Figure 5 , on the basis of Figure 3 , Figure 5 In the embodiment, a storage space 308 is added in the management unit 303. The storage space 308 can be used to cache the running data of the memory fault prediction and self-healing management system 305; or the storage space 308 can also be used to store the repair result of the faulty memory.

[0114] For example, the storage space 308 is used to store the repair result of the failed memory. For any one fault address, the processor 301 can send the repair result to the underlying firmware 302 after isolating and repairing the memory corresponding to the fault address. After receiving the repair result, the underlying firmware 302 can send the repair result to the self-healing module 307, so that the self-healing module 307 can store the fault address and the repair result at the fault address to the storage space 308. When the self-healing module 307 receives the fault address from the prediction module 306, the self-healing module 307 can query whether the fault address is repaired successfully in the storage space 308. If the fault location is not repaired successfully, the self-healing module 307 forwards the fault address to the underlying firmware 302; if the fault location is repaired successfully, the memory failure processing ends this time. Through the above method, false positives of the computer system can be avoided, thereby reducing the repair cost of the memory failure and saving the memory repair resources.

[0115] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0116] Figure 6 A flowchart of a memory failure processing method provided by an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the method can include the following steps. Figure 6

[0117] S601, the underlying firmware obtains first fault information of a fault occurred in the memory.

[0118] The first fault information is error information of a correctable error that has occurred in the memory. For example, the error information of the correctable error can include the time when the correctable error occurs and the physical address where the correctable error occurs.

[0119] The underlying firmware can obtain the first fault information from the memory controller.

[0120] S602, the underlying firmware sends the first fault information to the prediction module.

[0121] S603, the prediction module determines a first memory address according to the first fault information.

[0122] Correspondingly, the prediction module obtains the first fault information from the underlying firmware.

[0123] The first memory address is a physical address of a memory that may fail on the memory.

[0124] The memory at the first memory address is the first memory.

[0125] ​The prediction module can determine the location where the fault will occur on the memory according to the first fault information by using a memory fault analysis method.

[0126] For example, assuming that the prediction module analyzes the first fault information and determines that the location where the fault will occur on the memory is grain A, the first memory address is the physical address of grain A; assuming that the prediction module analyzes the first fault information and determines that the location where the fault will occur on the memory is row B, the first memory address is the physical address of row B.

[0127] It should be noted that the memory fault analysis method can be any method that can determine the first memory address, and the embodiments of the present application do not limit the memory fault analysis method. For example, the memory fault analysis method can be a function fitting method, an empirical diagnosis method, etc.

[0128] S604, the prediction module sends the first memory address to the self-recovery module.

[0129] S605, the self-recovery module determines the upper memory address corresponding to the first memory address.

[0130] Correspondingly, the self-recovery module obtains the first memory address from the prediction module.

[0131] It should be noted that in the embodiment, the upper memory address includes all upper memory addresses corresponding to the first memory address.

[0132] For example, assuming that the first memory address is memory 1-face 1-grain 5, the upper memory address includes memory 1-face 1 and memory 1. Assuming that the first memory address is memory 0-face 1-grain 4-block 9-row 7, the upper memory address includes memory 0-face 1-grain 4-block 9, memory 0-face 1-grain 4, memory 0-face 1 and memory 0.

[0133] S606, the self-recovery module determines whether the first memory is in a fault state according to the first memory address and the upper memory address.

[0134] If yes, S607 is performed.

[0135] If no, the fault handling of the first memory ends.

[0136] The memory state can include a fault state or a non-fault state. If the memory state of a certain physical address on the memory is a fault state, the memory at the physical address needs to be repaired. If the memory state of a certain physical address on the memory is a non-fault state, the memory at the physical address has been successfully repaired and does not need to be repaired again.

[0137] It should be noted that in the embodiment shown in Figure 7 The method for determining the memory state is described in detail in the embodiment shown in FIG. 6, which will not be described again here.

[0138] S607, the self-recovery module sends the first memory address to the underlying firmware.

[0139] When the first memory is in a failure state, the self-recovery module can send the first memory address to the underlying firmware to facilitate repair of the first memory.

[0140] S608, the underlying firmware sends the first memory address to the processor.

[0141] S609, the processor isolates the first memory.

[0142] The processor can determine the corresponding isolation strategy according to the first memory address, and isolate and repair the first memory.

[0143] If the first memory address is a bit-level address, the processor isolates the first memory by bits. If the first memory address is a row-level address, the processor isolates the first memory by rows. For example, the first memory address is: memory 2-face 0-granule 4-block 9-row 7, and the processor isolates the row corresponding to the first address by rows.

[0144] S610, the processor sends the first repair result of the first memory to the underlying firmware.

[0145] The first repair result can include repair success and repair failure.

[0146] After the processor isolates and repairs the first memory, the processor can send the repair result to the underlying firmware. For example, if the processor successfully repairs the first memory, the processor sends repair success to the underlying firmware; if the processor fails to repair the first memory, the processor sends repair failure to the underlying firmware.

[0147] S611, the underlying firmware sends the first repair result of the first memory to the self-recovery module.

[0148] After receiving the first repair result, the underlying firmware can send the first memory address and the first repair result to the self-recovery module to facilitate the self-recovery module to query during the memory failure processing process.

[0149] Optionally, S611 can further include S612. It should be understood that if S612 is not included, the first memory address and the first repair result can be cached to the storage space as the running data of the memory failure prediction and self-recovery management system.

[0150] S612, the self-recovery module stores the first memory address and the first repair result corresponding to the storage space.

[0151] Correspondingly, the self-recovery module obtains the first memory address and the first repair result from the underlying firmware.

[0152] The self-recovery module can store the first memory address and the first repair result in the storage space, so as to facilitate query in the memory fault processing.

[0153] In this embodiment, before the self-recovery module sends the first memory address to the underlying firmware, the self-recovery module can determine the memory state of the first memory according to the storage space. If the memory state of the first memory is a non-fault state, the self-recovery module no longer sends the first memory address to the underlying firmware, and the memory fault processing ends this time. If the memory state of the first memory is a fault state, the self-recovery module sends the first memory address to the underlying firmware, so that the processor isolates and repairs the first memory. Through the above method, when the first memory is in a non-fault state, the self-recovery module no longer sends the first memory address to the underlying firmware, thereby avoiding false positives of the computer system, saving memory repair resources, and reducing memory repair costs.

[0154] Next, the self-recovery module will be described in conjunction with Figure 7 The method for the self-recovery module to determine the memory state of the first memory will be described.

[0155] Figure 7 A flowchart of a method for determining a memory state according to an embodiment of the present application is shown in FIG. 7. As shown in FIG. 7, the method can include the following steps. Figure 7 The method can include the following steps.

[0156] S701, determine whether the storage space includes the first memory address and / or the upper-level memory address.

[0157] If not, perform S702.

[0158] If yes, perform S703.

[0159] In one possible implementation, the storage space is used to store repair results of faulty memories. The storage space can include a plurality of memory addresses and repair results corresponding to each memory address. For example, the storage space can store a plurality of memory addresses and repair results corresponding to each memory address in the form of a table.

[0160] For example, the storage space can be as shown in Table 1.

[0161] Table 1

[0162] Memory address Repair result Address A Repair success Address B Repair failure Address C Repair success …… ……

[0163] The self-recovery module can search the storage space for the first memory address and all upper-level memory addresses corresponding to the first memory address. If the storage space includes the first memory address or any one of the upper-level memory addresses corresponding to the first memory address, the self-recovery module determines that the storage space includes the first memory address and / or the upper-level memory address.

[0164] In another possible implementation, the storage space is used to cache the operational data of the memory fault prediction and self-healing management system.

[0165] It should be understood that the operational data of the memory fault prediction and self-healing management system may include data on the repair results of faulty memory.

[0166] The self-healing module can search the storage space for the first memory address and all its corresponding parent memory addresses using methods such as searching. If the storage space contains the first memory address or any of its corresponding parent memory addresses, the self-healing module determines that the storage space contains the first memory address and / or its parent memory addresses.

[0167] S702, Determine that the first memory is in a fault state.

[0168] S703. Determine whether the storage space includes the first memory address.

[0169] If so, execute S704.

[0170] If not, execute S705.

[0171] S704. Determine the memory status based on the repair result corresponding to the first memory address.

[0172] The self-healing module queries the storage space for the repair result corresponding to the first memory address. If the repair result corresponding to the first memory address is successful, the memory status is non-faulty; if the repair result corresponding to the first memory address is unsuccessful, the memory status is faulty.

[0173] S705. Determine the memory status based on the repair results corresponding to the upper-level memory address.

[0174] The method for determining the memory status based on the repair result corresponding to the upper memory address is similar to the method for determining the memory status based on the repair result corresponding to the first memory address. For details, please refer to S703, which will not be repeated here.

[0175] The method for determining memory status provided in this embodiment can determine the memory status of the first memory based on the first memory address or the parent memory address corresponding to the first memory address.

[0176] Based on any of the above embodiments, the following is combined with Figure 8 This application describes the memory fault handling method shown in the present application.

[0177] Figure 8 This is a flowchart illustrating another memory fault handling method provided in an embodiment of this application. Figure 8 As shown, the method in this embodiment includes:

[0178] S801, acquire first fault information of a fault occurred in the memory.

[0179] The execution subject of the embodiment can be a computer system or a memory fault processing device in the computer system. Optionally, the memory fault processing device can be implemented by software or by a combination of software and hardware.

[0180] In the embodiment, the memory can include an ECC grain. The computer system can acquire the first fault information of the fault occurred in the memory from the ECC grain.

[0181] S802, determine a first memory address according to the first fault information, and the memory at the first memory address is the first memory.

[0182] After acquiring the first fault information, the computer system can analyze the first fault information by a memory fault analysis method, and determine the physical address of the memory that can be faulty on the memory, i.e., the first memory address.

[0183] S803, determine the memory state of the first memory.

[0184] The computer system can determine the memory state of the first memory according to the plurality of memory addresses included in the storage space and the repair results corresponding to the memory addresses, and the memory state is a fault state or a non-fault state.

[0185] It should be noted that the method of determining the memory state of the first memory can refer to S701-S705, which will not be described here.

[0186] S804, isolate the first memory when the first memory is in a fault state.

[0187] The method of isolating the first memory can refer to S609, which will not be described here.

[0188] Optionally, the computer system can include a bottom firmware, a prediction module, a self-recovery module, and a processor. S801-S804 can be specifically: the bottom firmware can acquire the first fault information of the fault occurred in the memory, and send the first fault information to the prediction module. The prediction module can determine the first memory address according to the first fault information, and send the first memory address to the self-recovery module. The self-recovery module can determine the memory state of the first memory, and send the first memory address to the bottom firmware when the first memory is in a fault state, so that the bottom firmware can send the first memory address to the processor. The processor can isolate the first memory.

[0189] In this embodiment, the first memory address can be determined according to the first fault information of the memory that has occurred a fault, and the memory at the first memory address is the first memory. The memory state of the first memory can be determined, and the first memory can be isolated when the first memory is in a fault state. Through the above method, the false alarm of the memory fault of the computer system can be avoided, thereby reducing the repair cost of the memory fault and saving the memory repair resources.

[0190] Figure 9 A structural schematic diagram of a memory fault processing apparatus provided in the embodiment is shown in Figure 9 The memory fault processing apparatus 10 includes an acquisition module 11, a prediction module 12, and a self-recovery module 13, wherein

[0191] The acquisition module 11 is configured to acquire first fault information of a memory that has occurred a fault.

[0192] The prediction module 12 is configured to determine a first memory address according to the first fault information, and the memory at the first memory address is a first memory.

[0193] The self-recovery module 13 is configured to isolate the first memory when the determination module determines that the first memory is in a fault state.

[0194] The memory fault processing apparatus provided in the embodiment can be used to execute the technical solutions shown in any of the method embodiments, and has similar implementation principles and technical effects, which will not be described herein.

[0195] In a possible implementation, the self-recovery module 13 is specifically configured to

[0196] determine a memory state of the first memory according to a plurality of memory addresses included in the storage space and a repair result corresponding to each memory address, wherein the memory state is a fault state or a non-fault state;

[0197] isolate the first memory when it is determined that the memory state of the first memory is the fault state.

[0198] In a possible implementation, the self-recovery module 13 is specifically configured to

[0199] determine a superior memory address corresponding to the first memory address;

[0200] determine a memory state of the first memory according to the first memory address, the superior memory address, and a plurality of memory addresses included in the storage space and a repair result corresponding to each memory address.

[0201] In a possible implementation, the self-recovery module 13 is specifically configured to

[0202] if the first memory address and the upper memory address are not included in the storage space, determining that the memory state of the first memory is a failure state; or

[0203] if the first memory address is included in the storage space, determining the memory state of the first memory according to a repair result corresponding to the first memory address; or

[0204] if the upper memory address is included in the storage space, determining the memory state of the first memory according to a repair result corresponding to the upper memory address.

[0205] In a possible implementation, the self-recovery module 13 is specifically configured to,

[0206] if the repair result corresponding to the first memory address is repair success, the memory state of the first memory is a non-failure state; or

[0207] if the repair result corresponding to the first memory address is repair failure, the memory state of the first memory is a failure state.

[0208] In a possible implementation, the self-recovery module 13 is specifically configured to,

[0209] if the repair result corresponding to the upper memory address is repair success, the memory state of the first memory is a non-failure state; or

[0210] if the repair result corresponding to the upper memory address is repair failure, the memory state of the first memory is a failure state.

[0211] Figure 10 For another structure of the memory failure processing apparatus provided by the embodiment of the present application, please refer to Figure 10 The memory failure processing apparatus 10 further includes a storage module 14, wherein,

[0212] The acquisition module 11 is further used to acquire a first repair result of the first memory.

[0213] The storage module 14 is used to store the first memory address and the first repair result correspondingly in the storage space.

[0214] The memory failure processing apparatus provided by the embodiment can be used to execute the technical solutions shown in any of the method embodiments, and has similar implementation principles and technical effects, which will not be described here.

[0215] Figure 11 For a hardware structure of a memory failure processing apparatus provided by the present application, please refer to Figure 11The memory failure processing device 20 can include a processor 21 and a memory 22, wherein the processor 21 and the memory 22 can communicate; for example, the processor 21 and the memory 22 communicate through a communication bus 23, the memory 22 is configured to store program instructions, and the processor 21 is configured to invoke the program instructions in the memory to execute the memory failure processing method shown in any method embodiment.

[0216] Optionally, the memory failure processing device 20 can further include a communication interface, and the communication interface can include a transmitter and / or a receiver.

[0217] Optionally, the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the present application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor.

[0218] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a computer to implement the memory failure processing method executed by any method embodiment as above, and the implementation principle and technical effects are similar, and will not be repeated here.

[0219] The embodiments of the present application further provide a computer program product, which includes a computer program, and the computer program is executed by a computer to implement the memory failure processing method executed by any method embodiment as above, and the implementation principle and technical effects are similar, and will not be repeated here.

[0220] All or part of the steps of the above method embodiments can be completed by program instruction related hardware. The foregoing program can be stored in a readable memory. When the program is executed, the steps of the foregoing method embodiments are executed; and the foregoing memory (storage medium) includes a read-only memory (English: read-only memory, abbreviation: ROM), a RAM, a flash memory, a hard disk, a solid state disk, a magnetic tape (English: magnetic tape), a floppy disk (English: floppy disk), an optical disc (English: optical disc), and any combination thereof.

[0221] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable processing unit to produce a machine, so that the instructions executed by the computer or other programmable processing unit generate a device that implements the functions specified in the flowcharts and / or block diagrams. Figure One one or more flows and / or blocks Figure One one or more flows and / or blocks

[0222] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable processing unit to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams. Figure One one or more flows and / or blocks Figure One one or more flows and / or blocks

[0223] These computer program instructions can also be loaded onto a computer or other programmable processing unit, so that a series of operation steps are performed on the computer or other programmable processing unit to produce a computer-implemented process, so that the instructions executed on the computer or other programmable processing unit provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure One one or more flows and / or blocks Figure One one or more flows and / or blocks

[0224] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

[0225] In the present application, the term "includes" and its variants can refer to non-limiting inclusion; the term "or" and its variants can refer to "and / or". In the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. In the present application, "multiple" refers to two or more. "And / or", which describes the relationship between the associated objects, means that there can be three relationships, for example, A and / or B, which means that there are three cases: A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects.

Claims

1. A memory failure handling method, characterized by, The method comprises: obtaining first failure information of a memory that has failed; determining a first memory address according to the first failure information, the memory at the first memory address being a first memory; determining a memory state of the first memory according to a plurality of memory addresses included in a storage space and a repair result corresponding to each memory address, the memory state being a failure state or a non-failure state; isolating the first memory when it is determined that the memory state of the first memory is the failure state.

2. The method of claim 1, wherein, The method of determining the memory state of the first memory according to the plurality of memory addresses included in the storage space and the repair result corresponding to each memory address comprises: determining a superior memory address corresponding to the first memory address; determining the memory state of the first memory according to the first memory address, the superior memory address, and the plurality of memory addresses included in the storage space and the repair result corresponding to each memory address.

3. The method of claim 2, wherein, The method of determining the memory state of the first memory according to the first memory address, the superior memory address, and the plurality of memory addresses included in the storage space and the repair result corresponding to each memory address comprises: if the storage space does not include the first memory address and the superior memory address, determining that the memory state of the first memory is the failure state; or if the storage space includes the first memory address, determining the memory state of the first memory according to the repair result corresponding to the first memory address; or if the storage space includes the superior memory address, determining the memory state of the first memory according to the repair result corresponding to the superior memory address.

4. The method of claim 3, wherein, The method of determining the memory state according to the repair result corresponding to the first memory address comprises: if the repair result corresponding to the first memory address is a repair success, the memory state of the first memory is the non-failure state; or if the repair result corresponding to the first memory address is a repair failure, the memory state of the first memory is the failure state.

5. The method of claim 3, wherein, The method of determining the memory state of the first memory according to the repair result corresponding to the superior memory address comprises: if the repair result corresponding to the superior memory address is a repair success, the memory state of the first memory is the non-failure state; or if the repair result corresponding to the superior memory address is a repair failure, the memory state of the first memory is the failure state.

6. The method according to any one of claims 1 to 5, characterized in that, After isolating the memory at the first memory address, the method further comprises: obtaining a first repair result of the first memory; storing the first memory address and the first repair result corresponding thereto to the storage space.

7. A memory failure handling apparatus characterized by comprising: The apparatus comprises an obtaining module, a predicting module, and a self-recovery module, wherein: the obtaining module is configured to obtain first failure information of a memory that has failed; the predicting module is configured to determine a first memory address according to the first failure information, the memory at the first memory address being a first memory; The self-recovery module is configured to determine a memory state of the first memory according to a plurality of memory addresses included in the storage space and a repair result corresponding to each memory address, the memory state being a fault state or a non-fault state; and isolate the first memory when it is determined that the memory state of the first memory is the fault state.

8. A memory failure handling device, characterized by comprising: The memory is in communication connection with the processor. The memory stores a computer program. The processor executes the computer program to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a computer to implement the method according to any one of claims 1 to 6.

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