Method and apparatus for multistage encoding approximation calculation of tanh function

Abstract

The application discloses a method and device for approximating calculation of a Tanh function through multi-stage coding, and belongs to the field of integrated circuit design. The method realizes the approximation calculation of the Tanh function through multi-stage coding: in the first stage coding, grouping and mapping of input code values are realized, and the specific logic block to be executed by the second stage coding part is selected according to the grouping condition; in the second stage coding, the logic operation is completed with the mapped signal as the input; and in the third stage coding, further approximation processing is performed and the function value is output. The hardware device realized by the method of the application only uses a small amount of simple logic gates, and avoids the use of complex digital circuit units such as full adders, multipliers, registers and lookup tables, thereby greatly reducing the hardware overhead in terms of area, power consumption and delay while maintaining high accuracy.

Description

TECHNICAL FIELD

[0001] The application relates to a method and a device for approximating calculation of a Tanh function in multiple levels, and belongs to the field of integrated circuit design. BACKGROUND

[0002] In a neural network, only a model with multiplication and addition operations can perform linear fitting regardless of the size. In order to improve the expression ability of a neural network model and enable the neural network to better solve relatively complex problems, an activation function is often inserted into the neural network to improve the nonlinearity of the model.

[0003] The Tanh function is one of the most widely used activation functions, the value range of the vertical axis of which is (-1, 1), the average value is 0, and the Tanh function has the characteristics of an odd function and excellent effect in the case of obvious feature gap. However, due to the involvement of exponential operation and division operation, the Tanh function has high difficulty in mapping to hardware, and a large amount of hardware resource overhead is required to maintain ideal fitting accuracy, for example, a large number of adders, multipliers, registers and lookup tables are required. A large amount of hardware resource overhead also leads to a large area and high power consumption, and the delay of calculation will also be longer, which is unacceptable in ASIC.

[0004] A computing device and method for a nonlinear function are disclosed in patent CN107590105B, which uses an adder and a multiplier to calculate after converting the nonlinear function into a linear function. A nonlinear activation function computing device based on Newton iteration is disclosed in patent CN112051980A, which uses addition, subtraction and shifting operations to complete hardware mapping after polynomial approximation by Newton iteration. Patent CN110879697A realizes approximate calculation through a series of operation units by approximate transformation of integer part, decimal part and special value. Patent CN108647045A stores the difference between the residual sampling value and the reference sampling value in the lookup table, and the storage bit width consumed by the difference is smaller than the bit width consumed by the residual sampling value corresponding to the difference, so as to compress the storage space. Patent CN110288087A realizes the Tanh function through logical transformation, but the bit width of the output binary code decimal point in the patent is fixed and cannot change with the algorithm accuracy.

[0005] Ashkan Hosseinzadeh Namin et al. combined piecewise linear and address range variable lookup table, reduced the overhead of lookup table by storing the fitting error between simple piecewise function and Tanh function into lookup table, but the hardware implementation needs an additional comparator and subtracter (A. H. Namin et al., "Efficient hardware implementation of the hyperbolic tangent sigmoid function," 2009 IEEE International Symposium on Circuits and Systems, 2009, pp. 2117-2120, doi: 10.1109 / ISCAS.2009.5118213.). Fadzilatul Husna Adnan directly fitted the function expression by Taylor series expansion into polynomial, and proposed two hardware architectures, ring and tree. But this method uses more multipliers, adders and subtracters, and has large power consumption and delay (F. H. Adnan, M. F. O. Mahmud and W. F. H. Abdullah, "Hyperbolic tangent activation function integrated circuit implementation for perceptrons," 2012 IEEE Student Conference on Research and Development (SCOReD), 2012, pp. 84-87, doi: 10.1109 / SCOReD.2012.6518616.). Huaqing Sun et al. proposed a piecewise fitting method with unequal division, stored the slope and intercept of each segment in lookup table, and then completed the hardware implementation by indexing the input value.The method has good universality and can effectively control the fitting error, but the generation of the index number needs to use more subtractors, and the operation of the slope and the intercept also needs the multiplier and the adder to be realized together (H. Sun et al., "A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 1, pp. 177-188, Jan. 2020, doi: 10.1109 / TCSI.2019.2939563.). Zhang Bowen et al. proposed an approximate calculation method combining second-order approximation and error compensation, which first performs log transformation to facilitate hardware implementation, and then compensates for the fitting error. The method finally needs to use registers and multipliers (Zhang Bowen, Chen Gang, Chen Xu, Lu Huaxiang. Hardware Implementation of Tanh Function Based on Second-order Approximation and Error Compensation [J]. Microelectronics, 2021, 51(06): 905-909. DOI: 10.13911 / j.cnki.1004-3365.210031.).

[0006] The above patents and papers all effectively implement the approximate calculation and hardware mapping of the Tanh function, and propose methods to reduce hardware overhead under the premise of ensuring the required fitting accuracy from different aspects, but the optimized hardware overhead is still large. With the increasing demand for computing power in the field of artificial intelligence, the size of neural networks is also increasingly large, and the number of Tanh function modules in a single artificial intelligence chip also increases. Under the condition of limited hardware resources, it is more urgent to further reduce the hardware overhead of the Tanh function. In addition, the piecewise linear approximation and polynomial fitting methods are relatively complex, increasing the development difficulty of artificial intelligence chips. SUMMARY

[0007] To solve the problem of large hardware overhead of the Tanh function module in the integrated circuit, the present application provides a method and device for approximating the Tanh function by multi-level encoding, and the specific technical solutions are as follows:

[0008] The first object of the present application is to provide a method for approximating the Tanh function by multi-level encoding, which comprises:

[0009] Step one: perform fixed-point processing on the input value to be calculated, and the bit number of the processed input code value is Input_Bits;

[0010] Step two: first level encoding for the input code value after fixed-point processing, if the input value is negative, the negative code value is mapped to the corresponding positive code value by using the odd function characteristics, and then output; if the input value is positive, the code value is unchanged, and directly output;

[0011] Step three: according to the high N-1 bits of the output code value after the first level encoding except the sign bit, the logic block of the second level encoding is selected to output the calculation result, and the remaining low M bits of the code value are input into the logic block for logical operation; wherein, M = Input_Bits-N.

[0012] Step four: third level encoding for the code value output by the logic block, and further approximation processing is performed on the output code value,

[0013] The process of approximation processing includes: if the input of step one is positive, the value obtained by logical operation is unchanged; if the input of step one is negative, the value obtained by logical operation is operated by bit inversion except the sign bit.

[0014] Optionally, the overall logic design process of the method includes:

[0015] Step 1: determine the selected range [-m, +m] of the horizontal axis of the Tanh function of the approximate calculation, define the bit number Input_Bits of the function input code value of the approximate calculation and the bit number Output_Bits of the output code value;

[0016] Step 2: in the range of positive horizontal half axis [0, +m], 2^(Input_Bits-1) points are selected for the Tanh function, and the horizontal coordinate value and the vertical coordinate value of the selected points are respectively subjected to fixed-point processing, and the bit number of the processed horizontal and vertical coordinate code values is Input_Bits and Output_Bits respectively; based on the odd function characteristics of the Tanh function, the horizontal and vertical coordinate values in the range of negative horizontal half axis [-m, 0) are obtained by inverting the horizontal and vertical coordinate values of the positive horizontal half axis;

[0017] Step 3: select the high N-1 bits of the horizontal coordinate code value except the sign bit, which is used to determine the grouping number of the horizontal coordinate code value, i.e. the input code value, and specify the logic block to be executed for each group, and the positive input and negative input under the same group execute the same logic block; the negative input code value is mapped to the positive code value in the same group by the first level encoding, and the logic block to be executed for the group is specified;

[0018] Step 4: the remaining M bits of the input code value and the corresponding vertical coordinate code value are simplified by logic to determine the specific expression of each logic block in the second level encoding in the form of maximum term or minimum term, wherein M = Input_Bits-N.

[0019] Optionally, the input value and the output value are in the form of two's complement, denoted as SXpY.

[0020] Wherein, S represents a sign bit, X indicates the number of integer bits, Y indicates the number of decimal bits, and p represents a decimal point; the sum of the number of the sign bit, the integer bit and the decimal bit is equal to the bit number Input_Bits of the input value and the bit number Output_Bits of the output value respectively at the input end and the output end.

[0021] Optionally, in the step 2, the fixed-point processing of the Tanh function corresponding to the range [0, +m] of the positive semi-axis horizontal axis comprises the following steps:

[0022] Step 21: in the range [0, +m] of the positive semi-axis horizontal axis, based on the code value format of the input value, 2^(Input_Bits-1) horizontal axis points are selected, and the Tanh function values on the corresponding vertical axis are calculated;

[0023] Step 22: based on the code value format of the output value, the Tanh function values obtained above are completed fixed-point value taking according to the nearest principle;

[0024] Step 23: the decimal decimal values of the horizontal axis points and the vertical axis points are converted into two's complement, and the fixed-point processing is completed.

[0025] Optionally, the number of groups of the input code values in the step 3 is 2^N.

[0026] Optionally, the number of the logic blocks is 2^(N-1).

[0027] Optionally, the specific operation of mapping the negative code value to the corresponding positive code value in the step 3 comprises:

[0028] When it is detected that the highest bit of the input code value, i.e. the sign bit, is “1”, it is determined that the input code value is negative, and the logical inversion is taken for all bits except the sign bit; when it is detected that the highest bit of the input code value, i.e. the sign bit, is “0”, it is determined that the input code value is positive, and all code values remain unchanged.

[0029] The second object of the application is to provide a device for multi-level encoding approximate calculation of a Tanh function, which adopts the multi-level encoding approximate calculation method of the Tanh function to perform approximate calculation of the Tanh function, and the device comprises a first level encoding module, a second level encoding module and a third level encoding module.

[0030] The input end of the first level encoding module is connected with an external input code value, and the input code value is output after mapping processing.

[0031] The second stage coding module comprises a plurality of logic blocks and a multiplexer; the high N-1 bits of the first stage coding module except the sign bit are connected to the input end of the multiplexer for selecting the logic block of the calculation result to be output; and the low M bits of the first stage coding module are connected to the input end of the logic block of the second stage coding module to complete the logic operation.

[0032] The input end of the third stage coding module is connected to the output end of the second stage coding module, the sign bit of the input code value is connected to the selection end of the third stage coding module, and the third stage coding module is used for converting the output of the second stage coding module into a binary decimal complement format, and the conversion process comprises:

[0033] If the input code value is positive, the value obtained by the logic operation is kept unchanged; and if the input code value is negative, the value except the sign bit is operated by bit inversion.

[0034] The sign bit of the input code value is connected to the output of the multi-stage coding approximate calculation Tanh function device as the highest bit of the output of the multi-stage coding approximate calculation Tanh function device.

[0035] The output of the third stage coding module is used as the output of the multi-stage coding approximate calculation Tanh function device except the highest bit.

[0036] The third object of the present application is to provide a chip comprising the multi-stage coding approximate calculation Tanh function device.

[0037] The fourth object of the present application is to provide a system for realizing the calculation of the Tanh function, comprising a host computer, an input circuit, an output circuit and the chip; and the chip is connected to the host computer, the input circuit and the output circuit.

[0038] The present application has the following advantages:

[0039] The multi-stage coding approximate calculation Tanh function method and device provided by the present application avoid the complex processing required by the multi-segment linear fitting or polynomial approximation method, the logic block used is obtained by logic simplification, has the characteristics of convenient implementation, and reduces the development difficulty of the artificial intelligence chip. The horizontal axis range, input bit number and output bit number in the approximate calculation method can be adjusted according to the system requirements.

[0040] According to the technical scheme of the present application, only a small amount of simple logic gates are used in the hardware implementation process, and the use of complex digital circuit units such as full adders, multipliers, registers and lookup tables is avoided, so that the hardware circuit area is smaller, the power consumption is lower, and the delay is lower under the condition of maintaining the ideal accuracy of the fitting calculation result, and the design requirements of the current artificial intelligence chip for computing power, energy efficiency ratio and surface efficiency ratio can be met. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0042] Figure 1 is the architecture diagram of the device of the present application.

[0043] Figure 2 is the function image comparison diagram of the approximate calculation Tanh function and the original function of the method and device of embodiment three of the present application.

[0044] Figure 3 is the fitting error distribution when the method and device of embodiment three of the present application are used for approximate calculation. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0046] Embodiment one:

[0047] The present embodiment provides a method for multi-stage encoding approximate calculation of Tanh function, which comprises:

[0048] Step one: the input value to be calculated is subjected to fixed-point processing, and the bit number of the processed input code value is Input_Bits;

[0049] Step two: the input code value after fixed-point processing is subjected to first-stage encoding, if the input value is negative, the negative code value is mapped to the corresponding positive code value and then outputted by using the odd function characteristics; if the input value is positive, the code value is unchanged and directly outputted;

[0050] Step three: according to the high N-1 bits of the output code value after the first-stage encoding except the sign bit, the logic block of the calculation result to be outputted by the second-stage encoding is selected, and the remaining low M bit code value is inputted into the logic block for logic operation; wherein M = Input_Bits-N.

[0051] Step four: third level encoding is performed on the code value output by the logic block, and the output code value is further approximated,

[0052] The approximation process includes: if the step one input is positive, the logic operation result is kept unchanged; if the step one input is negative, the logic operation result is bitwise inverted except the sign bit.

[0053] Embodiment two:

[0054] The embodiment provides a multi-level encoding approximate calculation Tanh function device, and adopts the multi-level encoding approximate calculation Tanh function method in embodiment one to perform approximate calculation on the Tanh function, and the device comprises a first level encoding module, a second level encoding module and a third level encoding module.

[0055] The input end of the first level encoding module is connected with an external input code value, and the input code value is mapped and output.

[0056] The second level encoding module comprises a plurality of logic blocks and a multiplexer, the high N-1 bits of the first level encoding module except the sign bit are connected to the input end of the multiplexer, and are used for selecting the logic block of the calculation result to be output; and the low M bits of the first level encoding module are connected to the logic block input end of the second level encoding module, and logic operation is completed.

[0057] The input end of the third level encoding module is connected with the output end of the second level encoding module, the sign bit of the input code value is connected to the selection end of the third level encoding module, and the third level encoding module is used for converting the output of the second level encoding module into a binary fraction complement format, and the conversion process comprises:

[0058] If the input code value is positive, the logic operation result is kept unchanged; if the input code value is negative, the logic operation result is bitwise inverted except the sign bit.

[0059] The sign bit of the input code value is connected to the output of the multi-level encoding approximate calculation Tanh function device, and is used as the highest bit of the multi-level encoding approximate calculation Tanh function device.

[0060] Embodiment three:

[0061] The embodiment provides a multi-level encoding approximate calculation Tanh function device and method, and the device structure is referred to Figure 1 .

[0062] This embodiment takes 8-bit signal input and 8-bit signal output as the target, and approximates the Tanh function in the horizontal axis range [-4, +4], and completes the design of the hardware circuit. That is, the input code value bit number of the approximation calculation is 8, and the output value bit number is 8.

[0063] Because the horizontal axis is selected in the range [-4, +4], the input binary fraction complement format is S2p5, that is, the integer bit number at the input end is 2, and the fraction bit number is 5; the Tanh function output is in the range (-1, +1), so the output binary fraction complement format is S0p7, that is, the integer bit number at the output end is 0, and the fraction bit number is 7.

[0064] Considering the normalization between the encoding parts at each level, and in order to avoid the occurrence of extreme critical paths in the hardware circuit, the first level encoding input bit number N is selected as 4 bits, named as signals B4, B3, B2, B1 respectively, wherein B4 is the most significant bit (MSB) and represents the sign bit in the binary fraction complement format. Thus, the remaining code value bit number M can be determined as 4, named as signals b4, b3, b2, b1 respectively.

[0065] On the original Tanh function image in the horizontal axis range [0, +4], 128 points are selected, and the horizontal and vertical coordinate values of the 128 points are fixed-point processed, and the input code value and the output code value in the binary fraction complement format are obtained after processing.

[0066] The logic blocks are grouped by the first level encoding part, and the grouping conditions are shown in Table 1:

[0067] Table 1 Grouping conditions

[0068]

[0069]

[0070] In Table 1, the calculation results of the input code values of group 01 and group 02 are output by logic block 1, the calculation results of the input code values of group 03 and group 04 are output by logic block 2, and other grouping conditions are similar.

[0071] The first level encoding module is as shown in Figure 1 , which is composed of a plurality of simple logic gates, and its function is to map the input negative code value to the corresponding positive code value by using the odd function characteristics of the Tanh function.

[0072] The specific operation of the mapping is as follows: when it is detected that the highest bit of the input code value, that is, the sign bit, is "1", it can be determined that the input code value is negative, and the logic inversion is taken for all bits except the sign bit; when it is detected that the highest bit of the input code value, that is, the sign bit, is "0", it can be determined that the input code value is positive, and all code values remain unchanged.

[0073] The mapped signals are named S7, S6, S5, S4, S3, S2, S1, S0 respectively, wherein S7 and S0 are the highest and lowest bits respectively, and the specific expressions of the mapping operation are shown in Table 2:

[0074] Table 2 Specific expressions of mapping operation

[0075]

[0076]

[0077] Note: wherein "~" is a logical NOT operation, "~B4" represents a NOT operation on B4, "X" represents a logical AND operation, and "+" represents a logical OR operation.

[0078] The second-level encoding module is composed of logic blocks and a multiplexer, and S3, S2, S1, S0 are inputs of all the logic blocks, and logical operations are performed. In the embodiment, the output bit number of each logic block is 7 bits. S6, S5, S4 are inputs of the multiplexer, and are used to select the output results of the logic blocks. After the logical blocks and the multiplexer, the output signals of the second-level encoding module are named T6, T5, T4, T3, T2, T1, T0 respectively.

[0079] The logic block is composed of simple logic gates, and the specific logical expression in the logic block is influenced by the parameters of the horizontal axis range [-m, +m], Input_Bits, Outputs_Bits, M, N, and is obtained by logical simplification of the remaining M bits (M = Input_Bits - N) of the fixed-point processed input code value and the corresponding vertical coordinate code value, and is expressed in the form of the largest term or the smallest term. In the embodiment, the specific logical expression is shown in Table 3:

[0080] Table 3 Specific logical expression

[0081]

[0082]

[0083] Note: wherein "1' b0" represents a binary number 0; and "1' b1" represents a binary number 1.

[0084] The third level coding module comprises several two-way selectors, each of which is connected with a logic block in the second level coding module, and the two-way selector is used to perform further approximation operation, and the process of approximation processing comprises: selecting by a sign bit (the highest bit MSB), if the input code value is positive, the value obtained by the logic block operation is kept unchanged, and if the input code value is negative, the value obtained by the logic operation is subjected to a bitwise inversion operation except the sign bit.

[0085] In the prior art, for negative input, the data bits except the sign bit are subjected to a bitwise inversion operation and then a binary addition operation. The embodiment can approximate the processing process to a bitwise inversion operation of the data bits, thereby avoiding the use of an adder in the implementation of the hardware circuit, and the approximation result is as shown in FIG. 4, wherein the approximation error of the third level coding module in the coding method of the embodiment is low, and the coding method has good feasibility. Figure 3

[0086] The function images of the Tanh function obtained by the method and the device in the embodiment and the original function are as shown in FIG. 5, wherein the original Tanh function image is drawn by a curve segment, and the Tanh function image obtained by the approximation calculation is drawn by scattered points in "+" form. Figure 2 Figure 2 It can be seen that the method and the device of the embodiment have good fitting characteristics for the Tanh function.

[0087] The fitting error distribution when the method and the device of the embodiment perform approximation calculation is as shown in FIG. 6. In order to quantitatively represent the approximation calculation accuracy, the maximum error value MAE and the average error value E a are calculated based on the fitting error distribution. Figure 3

[0088] MAE = max | h (x) - f (x) |

[0089]

[0090] Wherein, h (x) is the original function, which represents the original Tanh function in the embodiment; f (x) is the function obtained by the approximation calculation, which represents the Tanh function obtained by the approximation calculation in the embodiment. The error value is negatively correlated with the approximation calculation accuracy.

[0091] Through calculation, the maximum error value of the embodiment is 0.03251, and the average error value is 0.0060. It can be seen from FIG. 6 that the method and the device of the embodiment have low fitting error. Figure 3

[0092] Based on the 55 nm integrated circuit production process, the hardware circuit in the embodiment is subjected to logic synthesis, and the obtained hardware overhead is as shown in Table 4:​​​​

[0093] Table 4 Hardware overhead

[0094]

[0095] As can be seen from Table 4, the method and device of the present embodiment have very low hardware overhead, and are very suitable for use in the design of large-scale and super-large-scale artificial intelligence chips, and are suitable for use in application scenarios such as embedded terminals with high real-time performance.

[0096] In order to further illustrate the beneficial effects of the present application, the hardware overhead of the present embodiment is compared with the hardware overhead data in some representative literature. The comparison indicators include: bit width, maximum error, average error, process node, area, power consumption, and delay.

[0097] Since no specific hardware overhead data is given in the currently granted related patents, the compared literature is all journal papers that have been published.

[0098] For the convenience of illustration, the compared scheme literature is numbered, and the numbering order follows the order of appearance in the background art part. The first mentioned is scheme 1, and the last mentioned is scheme 4. Specifically:

[0099] Scheme 1: A.H. Namin et al., "Efficient hardware implementation of the hyperbolic tangent sigmoid function," 2009 IEEE International Symposium on Circuits and Systems, 2009, pp. 2117-2120, doi: 10.1109 / ISCAS.2009.5118213.

[0100] Scheme 2: F.H. Adnan, M.F.O. Mahmud and W.F.H. Abdullah, "Hyperbolic tangent activation function integrated circuit implementation for perceptrons," 2012 IEEE Student Conference on Research and Development (SCOReD), 2012, pp. 84-87, doi: 10.1109 / SCOReD.2012.6518616.

[0101] Scheme 3: H. Sun et al., "A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 1, pp. 177-188, Jan. 2020, doi: 10.1109 / TCSI.2019.2939563.

[0102] Scheme 4: Zhang Bowen, Chen Gang, Chen Xu, Lu Huaxiang. Hardware Implementation of Tanh Function Based on Second-order Approximation and Error Compensation [J]. Microelectronics, 2021, 51(06): 905-909. DOI: 10.13911 / j.cnki.1004-3365.210031.

[0103] The comparison is shown in Table 5:

[0104] Table 5 Comparison of hardware overhead data

[0105]

[0106] Corresponding to the data in Table 5, Figure 3 The error distribution in this embodiment is shown, and the maximum error occurs near the zero point on the positive half axis, which is caused by the mapping of negative value code to positive value code. The error value meets the tolerance requirement of the neural network algorithm, and the value can be further reduced by increasing the bit width of the input data and the output data. At the same time, as shown in Table 5, the average error value of this embodiment is small, indicating that the approximate calculation result has good fitting effect on the whole.

[0107] As shown in Table 5, after considering the difference of process nodes, this embodiment still has very low hardware overhead, and performs excellently in area and power consumption indicators, which is very suitable for large-scale array application scenarios in artificial intelligence chips, and helps to improve the key performance of artificial intelligence chips in energy efficiency ratio and surface efficiency ratio. In addition, this embodiment has very low delay, so that it can work at a higher clock frequency, which helps to improve the computing power performance.

[0108] Some steps in the embodiments of the application can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0109] The above merely describes preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for approximating the Tanh function using multi-level coding, characterized in that, The method includes: Step 1: Perform fixed-point conversion on the input value to be calculated. The number of bits in the processed input code value is Input_Bits. Step 2: Perform first-level encoding on the input code value after fixed-point processing. If the input value is negative, use the properties of odd functions to map the negative code value to the corresponding positive code value and then output it; if the input value is positive, the code value remains unchanged and is output directly. Step 3: Select the logic block for the second-level encoding to output the calculation result based on the high N-1 bits (excluding the sign bit) of the output code value after the first-level encoding, and input the remaining low M bits of the code value into the logic block for logical operation; where M = Input_Bits – N; Step 4: Perform third-level encoding on the code value output by the logic block, and further approximate the output code value; The approximation process includes: if the input in step one is positive, the value obtained from the logical operation remains unchanged; if the input in step one is negative, the value obtained from the logical operation, except for the sign bit, is bitwise inverted. The overall logical design process of the method includes: Step 1: Determine the range of the horizontal axis [-m, +m] for the approximate calculation of the Tanh function, and define the number of bits for the input code value (Input_Bits) and the number of bits for the output code value (Output_Bits) of the approximate calculation function; Step 2: Select an average of 2^(Input_Bits-1) points for the Tanh function within the positive horizontal axis [0, +m], and perform fixed-point processing on the x and y coordinates of the selected points respectively. The number of bits for the processed x and y coordinate codes are Input_Bits bits and Output_Bits bits respectively. Based on the odd function characteristic of the Tanh function, the x and y coordinates within the negative horizontal axis [-m, 0) are obtained by inverting the x and y coordinates of the positive horizontal axis respectively. Step 3: Select the high N-1 bits of the horizontal coordinate code value excluding the sign bit to determine the number of groups of the horizontal coordinate code value, i.e., the input code value, and specify the logic block to be executed for each group. Positive and negative inputs in the same group execute the same logic block; map the negative input code value to the positive code value in the same group through the first level encoding, and specify the logic block to be executed for that group. Step 4: The remaining M bits of the input code value and the corresponding ordinate code value are logically simplified to determine the specific expression of each logic block in the second-level encoding, which is represented in the form of max-term or min-term, where M = Input_Bits - N; Step 2, performing fixed-point processing on the Tanh function corresponding to the positive half-axis range [0, +m], includes the following steps: Step 21: Within the positive half-axis horizontal range [0, +m], select 2^(Input_Bits-1) horizontal axis points based on the code value format of the input value, and calculate the corresponding Tanh function value on the vertical axis; Step 22: Based on the code value format of the output value, perform fixed-point value retrieval of the obtained Tanh function value according to the nearest principle; Step 23: Convert the decimal values ​​of the horizontal and vertical axis points into binary two's complement to complete the fixed-point conversion process.

2. The method for approximating the Tanh function using multi-level coding according to claim 1, characterized in that, The input and output values ​​are in binary two's complement form, denoted as SXpY; Where S represents the sign bit, X represents the number of integer bits, Y represents the number of decimal bits, and p represents the decimal point; at the input and output terminals, the sum of the number of sign bits, integer bits, and decimal bits is equal to the number of bits in the input value (Input_Bits) and the number of bits in the output value (Output_Bits), respectively.

3. The method for approximating the Tanh function using multi-level coding according to claim 1, characterized in that, In step 3, the number of input code value groups is 2^N.

4. The method for approximating the Tanh function using multi-level coding according to claim 1, characterized in that, The number of logic blocks is 2^(N-1).

5. The method for approximating the Tanh function using multi-level coding according to claim 1, characterized in that, The specific operations in step 3 of mapping negative code values ​​to corresponding positive code values ​​include: When the highest bit of the input code value, i.e. the sign bit, is detected to be "1", the input code value is determined to be negative, and all bits except the sign bit are logically inverted; when the highest bit of the input code value, i.e. the sign bit, is detected to be "0", the input code value is determined to be positive, and all code values ​​remain unchanged.

6. A device for multi-level coding approximate calculation of the Tanh function, characterized in that, The device performs approximate calculation of the Tanh function using the multi-level coding approximation calculation method as described in any one of claims 1-5, and the device includes: a first-level coding module, a second-level coding module, and a third-level coding module; The input terminal of the first-level encoding module is connected to an external input code value, and the input code value is mapped and then output. The second-level encoding module includes several logic blocks and a multiplexer; the high N-1 bits of the first-level encoding module, excluding the sign bit, are connected to the input of the multiplexer to select the logic block from which the calculation result is to be output; the low M bits of the first-level encoding module are connected to the input of the logic block of the second-level encoding module to complete the logical operation. The input terminal of the third-level encoding module is connected to the output terminal of the second-level encoding module, and the sign bit of the input code value is connected to the selection terminal of the third-level encoding module. The third-level encoding module is used to convert the output of the second-level encoding module into binary two's complement format. The conversion process includes: If the input code value is positive, the value obtained from the logical operation remains unchanged; if the input code value is negative, the other values ​​except the sign bit are bitwise inverted. The sign bit of the input code value is connected to the output of the device for multi-level coding approximation calculation of the Tanh function, and serves as the highest bit of the output of the device for multi-level coding approximation calculation of the Tanh function. The output of the third-level encoding module serves as the output of the bits other than the highest bit of the device for approximating the Tanh function using multi-level encoding.

7. A chip, characterized in that, The chip includes: a device for multi-level encoding approximation calculation of the Tanh function as described in claim 6.

8. A system for calculating the Tanh function, characterized in that, It includes a host computer, an input circuit, an output circuit, and the chip as described in claim 7; the chip is connected to the host computer, the input circuit, and the output circuit.

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