A High-Level Synthesis Tool Optimization Method and System Based on Difference Constraint System

Abstract

The present invention relates to the technical field of hardware circuit structure design, and proposes a high-level synthesis tool optimization method and system based on a differential constraint system. The method includes the following steps: converting an IP core into several basic blocks bb k The present invention can specify a specific IP core module for function implementation and can also automatically identify and apply IP cores in scheduling optimization, effectively improving the development efficiency of high-level synthesis tools and having broad application in the field of hardware circuit structure design.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware circuit structure design, and more specifically, to a high-level synthesis tool optimization method and system based on a differential constraint system. Background Art

[0002] The goal of high-level synthesis is to obtain a hardware circuit structure within a given set of targets that satisfies the algorithmic-level behavioral description and constraints of a given digital system. The generated hardware circuit structure can be a register transfer-level hardware description language or a netlist. The basic process of high-level synthesis includes compilation and conversion, operator scheduling, resource allocation, register allocation, and wiring network generation and optimization. Operator scheduling, or the scheduling algorithm, is the most important step in the high-level synthesis process. It allocates each operation and calculation in the control data flow graph generated by compilation and conversion to each control step, thereby achieving the optimal or relatively optimal operator scheduling solution that meets the constraints.

[0003] A key factor limiting the timing quality of high-level synthesis output is the difficulty in accurately estimating interconnect delays, forcing design tools to use conservative estimates for reliability. Interconnects crossing module boundaries introduce a significant delay increase, especially for IP cores such as PCIe and DDR controllers embedded in programmable logic. These IP cores typically have fixed locations near dedicated I / O banks and consume significant amounts of nearby programmable resources. Consequently, these dedicated IP cores often force signals to follow longer paths. Furthermore, modules interacting with these fixed-location IP cores are subject to greater restrictions on their placement. This, in turn, results in longer communication paths with other modules. These factors often combine to further reduce the final clock frequency.

[0004] Common high-level synthesis tools generally only consider basic operations such as addition, subtraction, multiplication, and division as basic operators for scheduling. This is because basic operators can be easily converted to intermediate code converted from high-level languages and hardware description languages in a one-to-one correspondence. However, current high-level synthesis tools are unable to perform high-level synthesis design for IP cores. They cannot specify the use of specific IP core modules for function implementation in behavioral-level inputs, cannot consider the IP core's underlying hardware information during operator scheduling optimization, and cannot automatically identify and replace IP cores during operator scheduling optimization. This means that in some applications, designers must manually rewrite and replace IP core modules in the code before and after synthesis, reducing the development efficiency of high-level synthesis. Summary of the Invention

[0005] In order to overcome the defects of the above-mentioned prior art high-level synthesis tools that cannot perform high-level synthesis design for IP cores and have low development efficiency, the present invention provides a high-level synthesis tool optimization method and system based on a differential constraint system.

[0006] In order to solve the above technical problems, the technical solutions of the present invention are as follows:

[0007] A high-level synthesis tool optimization method based on a differential constraint system includes the following steps:

[0008] Obtain the circuit description of the input IP core, as well as the scheduling constraints and weights of the IP core;

[0009] Convert the IP core into several basic blocks k , and converting the constraints of the IP core into differential constraint formulas;

[0010] Based on the differential constraint formula, a differential constraint system is used to generate a control data flow graph and perform resource pre-allocation;

[0011] Scanning, replacing, and scheduling operators in the control data flow graph based on pattern matching and operator mobility to optimize the control data flow graph;

[0012] Resources are allocated according to the optimized control data flow graph to generate the hardware circuit structure.

[0013] Furthermore, the present invention also proposes a high-level synthesis tool optimization system based on a differential constraint system, applying the high-level synthesis tool optimization method based on a differential constraint system of the present invention; wherein the system includes:

[0014] The data acquisition module is used to obtain the circuit description of the IP core, as well as the scheduling constraints and weights of the IP core;

[0015] Differential constraint system for converting IP cores into basic blocks k , and converting the constraints of the IP core into differential constraint formulas;

[0016] A resource pre-allocation module, configured to generate a control data flow graph and perform resource pre-allocation using a differential constraint system based on the differential constraint formula;

[0017] A control data flow graph optimization module, configured to scan, replace, and schedule operators in the control data flow graph based on pattern matching and operator mobility, thereby optimizing the control data flow graph;

[0018] The resource allocation module is used to allocate resources according to the optimized control data flow graph and generate the hardware circuit structure.

[0019] Furthermore, the present invention also proposes a computer device, including a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the high-level synthesis tool optimization method based on the differential constraint system of the present invention are implemented.

[0020] Furthermore, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the high-level synthesis tool optimization method based on a differential constraint system of the present invention.

[0021] Compared with the prior art, the beneficial effects of the technical solution of the present invention are as follows: the present invention is a high-level synthesis tool optimization algorithm for IP cores. By constructing IP cores into operators based on a differential constraint system, and scanning, replacing, and scheduling operators based on pattern matching and operator mobility, it can specify specific IP core modules for function implementation and automatically identify and apply IP cores in scheduling optimization, solving the congestion problem during IP core scheduling, effectively improving the development efficiency of high-level synthesis tools, and effectively improving the performance and reliability of circuits generated by high-level synthesis tools. The present invention can be widely used in the field of hardware circuit structure design. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a flowchart of a high-level synthesis tool optimization method based on a differential constraint system according to Example 1.

[0023] Figure 2 A schematic diagram of the control data flow graph.

[0024] Figure 3 Schematic diagram of IP core pattern matching and replacement.

[0025] Figure 4 This is a schematic diagram of IP core partitioning.

[0026] Figure 5 This is a schematic diagram of an unused IP core operator.

[0027] Figure 6 It is a schematic diagram of the optimization method using the high-level synthesis tool of Example 1.

[0028] Figure 7 This is a hardware resource comparison chart.

[0029] Figure 8 This is an architectural diagram of a high-level synthesis tool optimization system based on a differential constraint system according to Example 2.

[0030] Figure 9 Schematic diagram of the balancing delay process. DETAILED DESCRIPTION

[0031] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0032] It is understandable to those skilled in the art that some well-known structures and descriptions thereof may be omitted in the drawings.

[0033] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0034] Example 1

[0035] This embodiment proposes a high-level synthesis tool optimization method based on a differential constraint system, such as Figure 1 , which is a flow chart of the high-level synthesis tool optimization method based on the differential constraint system of this embodiment.

[0036] The high-level synthesis tool optimization method based on the differential constraint system proposed in this embodiment includes the following steps:

[0037] S1. Obtain the circuit description of the input IP core, as well as the scheduling constraints and weights of the IP core.

[0038] S2. Convert the IP core into several basic blocks bb k , and converting the constraints of the IP core into differential constraint formulas.

[0039] S3. Based on the differential constraint formula, a differential constraint system is used to generate a control data flow graph and perform resource pre-allocation.

[0040] S4. Based on pattern matching and operator mobility, the operators in the control data flow graph are scanned, replaced and scheduled to optimize the control data flow graph.

[0041] S5. Allocate resources according to the optimized control data flow graph and generate a hardware circuit structure.

[0042] Among them, this embodiment is a high-level synthesis tool optimization algorithm for IP cores. It can specify a specific IP core for the implementation of a function, and can also automatically identify and apply the IP core in scheduling optimization, solving the problems of congestion and low development efficiency during IP core scheduling, and effectively improving the performance and reliability of circuits generated by high-level synthesis tools.

[0043] The control dataflow graph (CDFG) of this embodiment is the execution operation object of the scheduling algorithm. It is a directed graph that contains relevant information such as data operations, data dependencies, control jumps, etc. in the circuit description input to the system. The control dataflow graph can be divided into two parts: nodes (scheduling units) and edges (relationships between scheduling units). Among them, nodes include operation nodes (Operation node) and basic blocks (Basic block). Operation nodes refer to the set of operation operations that appear in the input circuit description, and according to different control relationships, one or more operation node sets can constitute a basic block. For example Figure 2 The figure below shows a schematic diagram of a control data flow graph. The solid lines represent data dependency edges, the dashed lines represent control dependency edges, each ellipse represents an operation node, and each box represents a basic block. Every circuit description can be represented by such a directed graph.

[0044] In a specific embodiment, a data flow graph is established through the LLVM compilation system, and information such as instruction types, data dependencies, and control jumps are abstracted into a model to construct a control data flow graph to facilitate various optimization tasks including scheduling, resource allocation, and reuse.

[0045] In an optional embodiment, step S1 includes the following steps:

[0046] S1.1. Obtain the hardware circuit interface of the IP core based on the stub code of the IP core;

[0047] S1.2. Obtain the input and output behavior and input and output timing of the IP core based on the prototype code or simulation code of the IP core;

[0048] S1.3. Specify the constraints of the IP core through LUA scripts;

[0049] S1.4. Specify the weight of the IP core through the LUA script.

[0050] The IP core's stub code is used to instantiate the IP core. This stub code itself doesn't execute, but it provides interface information for the instantiated IP core, including port number, port and bit width input / output definitions, and the handshake protocol used by the interface. Obtaining the IP core's hardware circuit interface automatically generates the correct hardware structure during syntax tree reconstruction, eliminating the need for manual interface modification. This reduces manual intervention throughout the high-level synthesis process and improves automation.

[0051] IP core prototype or simulation code is typically provided as a C language model. This C language model is bit-accurate and fully expresses the behavioral dependencies within the IP core. Some IP cores also provide a cycle-accurate C language model that accurately expresses the timing relationships within the IP core, such as the output waveform for each cycle.

[0052] This embodiment specifies the high-level synthesis tool parameters such as the constraints and weights of the IP core through the LUA script. Among them, the weight represents the degree of performance / resource optimization that the IP core can bring. The greater the weight, the greater the benefit of replacing the IP core. IP cores with large weights tend to consume a lot of hardware resources and require complex surrounding interaction logic. The high-level synthesis tool will optimize the conversion of IP cores with large weights and partition them to reduce wiring congestion. In the LUA script, you can also specify the use of a specific IP core module for the implementation of the function in the behavioral level input. The specified code will be directly converted into the corresponding IP core operator in the resource pre-allocation link, and then the operator scheduling will be performed.

[0053] Furthermore, in an optional embodiment, the constraint conditions include at least one of data dependency constraints, timing dependency constraints, and resource constraints. Then, in step S2, the constraint conditions of the IP core are converted into a differential constraint formula, including the following steps:

[0054] S2.1, mapping the corresponding input and output ports of the IP core to basic blocks bb k Internal scheduling variable sv, also basic block bb k Add super source node ssrc(bb k ) and super drain node ssnk(bb k ).

[0055] S2.2. Generate a first differential constraint formula based on the data dependency constraint of the IP core; its expression is as follows:

[0056]

[0057] Where, node v i ,v j As the basic block bb k There are two operation nodes with data dependency constraints inside, and node v i Must be at node v j Scheduling is completed before scheduling; e(v i ,v j ) represents node v i and v j The data dependency constraint edge, Represents the basic block bb in the control data flow graphk The set of data dependency constraint edges in sv end (v i ) represents node v i The final value of the scheduling variable, sv beg (v j ) represents node v j The starting value of the scheduling variable. Generally, the node v i ,v j Corresponding to the input and output ports respectively.

[0058] S2.3. Based on the timing dependency constraint of the IP core, generate a second differential constraint formula; its expression is as follows:

[0059] sv beg (ssrc(bb k ))-sv end (ssnk(bb k ))≤-T lat,min

[0060] sv end (ssnk(bb k ))-sv beg (ssrc(bb k ))≤T lat,max

[0061] Where sv beg (ssrc(bb k )) represents the basic block bb k The starting value of the scheduling variable, sv end (ssnk(bb k )) represents the basic block bb k The final value of the scheduling variable T lat,max Represents the basic block bb k The number of clock cycles of the internal maximum delay path, T lat,min Represents the basic block bb k The number of clock cycles of the internal minimum delay path. The delay path information is related to the IP core itself.

[0062] S2.4. Based on the resource constraints of the IP core, generate a third differential constraint formula; its expression is as follows:

[0063]

[0064] In the formula, the node and nodes Represents a pair of nodes that do not belong to the IP core operator but have the same resources. Representation node The starting value of the scheduling variable, Representation node The starting value of the scheduling variable, Representation node The time required for execution, Representation node and The data dependency constraint edge of the basic block bb k The resources do not participate in the scheduling reuse based on the differential constraint system.

[0065] This embodiment converts the IP core into a basic block based on the differential constraint system, so that the IP core can continue to be scheduled as a scheduling operator. Combined with the differential constraint formula, the high-level synthesis tool can generate the correct operator pattern for matching and replacing operators during scheduling optimization.

[0066] Furthermore, in an optional embodiment, step S3 uses a differential constraint system to generate a control data flow graph and perform resource pre-allocation, including the following steps:

[0067] S3.1. Based on the circuit description of the IP core, a compiler front end is used to generate intermediate code from the high-level language code described at the behavioral level from the source code.

[0068] S3.2. Based on the differential constraint formula, a differential constraint system is used to generate a control data flow graph, and the basic operators and dependency relationships of the intermediate code are mapped into nodes, control edges and basic blocks of the control data flow graph.

[0069] S3.3. Bind the corresponding types of hardware resources according to the nodes and basic blocks of the control data flow graph, obtain preliminary hardware resource usage, and complete resource pre-allocation.

[0070] Furthermore, in an optional embodiment, scanning, replacing, and scheduling operators in the control data flow graph in step S4 includes the following steps:

[0071] S4.1. Calculate the mobility of operators in the control data flow graph.

[0072] S4.2. Based on pattern matching and a breadth-first search algorithm, scan the operators in descending order of weight, replacing the set of operators that match the pattern with a sequence of operators that matches the timing behavior information of the corresponding IP core. For each operator combination that satisfies the pattern matching, add an IP core operator that matches the timing behavior information of the corresponding IP core, connect the corresponding control edge to the input and output nodes of the IP core operator, cut off all control edges of the original operator, and delete the original operator combination.

[0073] S4.3. Repeat steps S4.1 to S4.2 until there are no alternative operators. Then, based on the cut set concept, partition the high-weight IP cores and use a pipeline solution to balance the parallel path delays to complete the optimization of the control data flow graph.

[0074] The definition of operator mobility is as follows: Assuming v is an operation, CSASAP(v) is the control step number of operation v in ASAP (As Soon As Possible) scheduling, and CSLSAP(v) is the control step number of operation v in ASAP scheduling, then the mobility of operator v is expressed as:

[0075] M(v)=CSLSAP(v)-CSASAP(v)+1.

[0076] In this embodiment, the physical meaning of operator mobility is: the mobility M(v) of operator v means that operator v can change in M(v) control steps.

[0077] The Breadth-First Search (BFS) algorithm is a blind search method that aims to systematically expand and check all nodes in the graph to find the result.

[0078] In this embodiment, based on pattern matching and breadth-first search algorithms, scanning is performed from high to low according to the weight of the operator. This is for performance priority considerations, and priority is given to finding usage patterns that meet the requirements of large-weight IP cores.

[0079] like Figure 3 Figure 2 shows a schematic diagram of IP core pattern matching and replacement. Taking operator mobility into consideration, this embodiment uses a breadth-first search algorithm and pattern matching to find an operator sequence that matches the timing behavior of the corresponding IP core, sorted by operator weight from high to low. This sequence is then replaced. The total operator mobility of each control step will decrease after replacement. However, the default IP core is a high-performance, reliable circuit, and replacement can improve overall circuit performance.

[0080] In step S4.3 of this embodiment, high-weight IP cores are partitioned, all edges crossing partition boundaries are pipelined, and then the delays of parallel paths are balanced based on the cut-set pipeline concept.

[0081] A cut set is a set of edges that can be removed from a graph to create two disconnected subgraphs. If all edges in a cut set have the same direction, an equal amount of delay can be added to each edge, and the throughput of the design will not be affected. This embodiment optimizes the control data flow graph based on the cut set concept, enabling pipeline optimization without compromising throughput.

[0082] In a specific embodiment, if Figure 4 The following is a schematic diagram of the IP core partitioning of this embodiment. In the figure, 1 to 7 are all IP cores, r0, r1, and r 00 、r 01 、r 10 、r 11 They represent the partitioned areas respectively.

[0083] This embodiment partitions the large-weight IP cores to reduce the congestion of the circuit. IP core modules usually have fixed positions near dedicated I / O banks and consume a large amount of nearby programmable resources. Therefore, these dedicated IPs often divert signals to longer paths. In addition, modules that interact with these fixed-position IPs are also more restricted in their layout. Large-weight IP cores can serve as markers for the area. Based on the idea of floor planning, targeted insertion of FIFO partitioning pipelines can greatly improve the parallelism of the circuit. Small-weight IP cores, as supplements to basic operators, do not need to be partitioned. Figure 4 The basic idea behind mid-partitioning is to separate the two most heavily weighted IPs, then cluster other larger IPs based on control and data dependencies, continuously partitioning. The basic idea is to keep heavily weighted IP cores farther apart and IP cores with closer dependencies closer together.

[0084] Furthermore, in step S4.3, based on the cut set concept, high-weight IP cores are partitioned, and the steps of balancing parallel path delays using a pipeline solution include:

[0085] S4.3.1. Given a partitioned and pipelined control data flow graph G<V,E> , each vertex v∈V represents a function in the data flow design, and each edge e∈E represents a FIFO channel between functions; for each edge e∈E, the total delay of each path is expressed as:

[0086]

[0087] where e.lat represents the extra delay inserted in the previous pipeline step, e.balance represents the balanced delay in the current step, and {p1, p2} represents a pair of reconverging paths.

[0088] S4.3.2. For each edge e∈E, consider S i ≥S j +e ij.lat , then the additional balancing delay e ij.balance Expressed as:

[0089] e ij.balance =(S i -S j -e ij.lat)

[0090] Where S i -S j Represents vertex v i and v j The maximum delay between all paths, e ij.lat Indicates that the previous pipeline step is at vertex v i and v j The additional delay inserted in the longest path between ij.balance Indicates that the current pipeline step is at vertex v i and v j The balanced delay inserted in the longest path between them.

[0091] S4.3.3. Minimize the total area cost as the optimization goal, while considering the bit width cost of each edge, and construct the objective function; its expression is as follows:

[0092]

[0093] Where, e ij.width Indicates that the current pipeline step is at vertex v i and v j Maximum data bit width between ij Represents vertex v i and v j The longest path edge between them.

[0094] S4.3.4, the constraint condition S i ≥S j +e ij.lat A differential constraint system is formed with the objective function, and the differential constraint system is treated as an integer linear programming problem and solved by a solver to obtain an optimized control data flow graph.

[0095] Among them, S i Represents vertex v i The maximum path delay between the sink and the node, S j Represents vertex v j The maximum path delay between the node and the sink; a sink is a point in the directed graph where deg-(v) = 0. In this embodiment, the constraints and objective function essentially constitute a differential constraint system. Therefore, the differential constraint model for balancing parallel path delays can be solved as an integer linear programming problem. Given the constraints and objective function, and requiring the solution to be an integer, a solver can be used to solve the problem.

[0096] In one specific embodiment, the open-source solver lpsolve is used to solve an integer linear programming problem consisting of a differential constraint system. lpsolve, an open-source project available on SourceForge, is a mixed-integer linear programming solver that can solve purely linear, (mixed) integer / binary, semi-continuous, and special ordered set models. It has been proven to be highly efficient in practice.

[0097] like Figure 9 As shown, Figure 9 (a) represents the cut-set1 cut set in the balanced delay process; Figure 9 (b) Cut-set 2 and cut-set 3 are shown during the delay balancing process. Edges e13, e37, and e27 are pipelined based on the floorplan partitioning principle, and each edge carries an insertion delay of 1 unit. It is also assumed that the bit width of e14 is 2, and that of all other edges is 1. During the delay balancing step, the optimal solution is to add 2 units of delay to each of edges e47, e57, and e67, and 1 unit of delay to each of edges e12. e27 and e37 can exist in the same cut-set.

[0098] In this embodiment, IP core operators with high weights are partitioned and connected based on FIFO (First Input First Output) channels to enable pipelined operation. Using FIFO channels allows for direct scheduling of matching interface signals without affecting functionality, and provides parallelism for circuit functions.

[0099] Furthermore, in an optional embodiment, performing resource allocation according to the optimized control data flow graph in step S5 includes the following steps:

[0100] S5.1. Create a directed acyclic graph based on the optimized control data flow graph and establish a resource constraint list.

[0101] S5.2. Find the longest path in the directed acyclic graph based on a breadth-first algorithm, and put each node involved in the longest path into the resource constraint list in sequence.

[0102] S5.3. Remove the nodes and edges of the longest path from the control data flow graph and the directed acyclic graph to obtain a new control data flow graph and directed acyclic graph.

[0103] S5.4. Repeat the above steps until all nodes in the control data flow graph and the directed acyclic graph are placed in the resource constraint list, then generate the hardware circuit structure according to the resource constraint list, and adjust the hardware circuit interface involving the IP core operator.

[0104] This embodiment can automatically call the corresponding IP core in the high-level synthesis design without the need for manual design by the designer, thereby improving the development efficiency of the high-level synthesis and the performance of the circuit implementation.

[0105] In a specific embodiment, a multiplier IP core is used as an example for detailed description. Assume that the design needs to implement a 64-bit by 64-bit multiplication, where shang_mult is the built-in multiplication function of this embodiment, and mult_gen is the IP core of Xilinx Vivado.

[0106] like Figure 5 As shown, this is the case where the IP core operator is not used. Its hardware resources are as follows Figure 7 (a) For multiplication operations, high-level synthesis tools default to using built-in basic operators, equivalent to using the multiplication symbol "*" to implement multiplication. The integrated wiring process uses this default method to implement multiplication operations. At the hardware description language (RTL) design level, the generated hardware cannot be manipulated, potentially resulting in the use of LUTs to implement large-bitwidth multiplications.

[0107] like Figure 6 As shown, this is the case of using the high-level synthesis tool optimization method of this embodiment, and its hardware resources are as follows: Figure 7 (b) The high-level synthesis tool in this embodiment invokes a specific IP core, specifically the Xilinx Vivado Multiplier 12.0 IP core. Because Multiplier is invoked, implementation utilizes the DSP48E slice hardware unit within the FPGA, resulting in superior performance. The DSP48E slice improves flexibility and utilization, enhances application efficiency, reduces overall power consumption, and increases maximum frequency.

[0108] Further, by Figure 7 As shown in the hardware resource comparison diagram, the high-level synthesis tool optimization method of this embodiment can enable the high-level synthesis tool to use more DSP slices as expected by the designer, thereby achieving higher timing performance.

[0109] Example 2

[0110] This embodiment proposes a high-level synthesis tool optimization system based on a differential constraint system, and applies the high-level synthesis tool optimization method based on a differential constraint system proposed in Example 1. Figure 8 , which is an architecture diagram of a high-level synthesis tool optimization system based on a differential constraint system according to this embodiment.

[0111] The high-level synthesis tool optimization system based on the differential constraint system proposed in this embodiment includes:

[0112] The data acquisition module is used to obtain the circuit description of the IP core, as well as the scheduling constraints and weights of the IP core.

[0113] Differential constraint system for converting IP cores into basic blocks k , and converting the constraints of the IP core into differential constraint formulas.

[0114] The resource pre-allocation module is used to generate a control data flow graph and perform resource pre-allocation based on the differential constraint formula and the differential constraint system.

[0115] The control data flow graph optimization module is used to scan, replace and schedule operators in the control data flow graph based on pattern matching and operator mobility, and optimize the control data flow graph.

[0116] The resource allocation module is used to allocate resources according to the optimized control data flow graph and generate the hardware circuit structure.

[0117] In an optional embodiment, during operation, the data acquisition module obtains the hardware circuit interface of the IP core based on the stub code of the IP core; obtains the input and output behavior and input and output timing of the IP core based on the prototype code or simulation code of the IP core; specifies the constraints of the IP core through the LUA script; and specifies the weight of the IP core through the LUA script.

[0118] In an optional embodiment, the constraint condition includes at least one of a data dependency constraint, a timing dependency constraint, and a resource constraint.

[0119] Furthermore, during operation, the differential constraint system maps the corresponding input and output ports of the IP core to basic blocks bb k Internal scheduling variable sv, also basic block bb k Add super source node ssrc(bb k ) and super drain node ssnk(bb k ); based on the data dependency constraints, timing dependency constraints and / or resource constraints of the IP core, convert them into corresponding differential constraint formulas.

[0120] Furthermore, in an optional embodiment, during operation, the resource pre-allocation module uses a compiler front end to generate intermediate code from the source code of the high-level language code described at the behavioral level according to the circuit description of the IP core; based on the differential constraint formula, a differential constraint system is used to generate a control data flow graph, and the basic operators and dependencies of the intermediate code are mapped to nodes, control edges and basic blocks of the control data flow graph; according to the nodes and basic blocks of the control data flow graph, corresponding types of hardware resources are bound to obtain preliminary hardware resource usage and complete resource pre-allocation.

[0121] Furthermore, in an optional embodiment, the control data flow graph optimization module calculates the mobility of the operators in the control data flow graph during operation; based on pattern matching and breadth-first search algorithms, it scans in descending order of operator weights, and replaces the set of operators that meet the pattern with an operator sequence that is consistent with the timing behavior information of the corresponding IP core; wherein, for the operator combination that meets the pattern matching, an IP core operator that is consistent with the timing behavior information of the corresponding IP core is added, the corresponding control edge is connected to the input and output nodes of the IP core operator, all control edges of the original operator are cut off, and the original operator combination is deleted.

[0122] The control data flow graph optimization module repeats the above steps until there are no alternative operators, and then partitions the high-weight IP cores based on the cut set idea, uses a pipeline solution to balance the parallel path delay, and completes the optimization of the control data flow graph.

[0123] Furthermore, the control data flow graph optimization module takes minimizing the total area overhead as the optimization goal, while considering the bit width overhead of each edge, and constructs an objective function for optimizing the control data flow graph by adopting a pipeline solution to balance the parallel path delay.

[0124] Furthermore, in an optional embodiment, during operation, the resource allocation module establishes a directed acyclic graph based on the optimized control data flow graph and establishes a resource constraint list; based on the breadth-first algorithm, it searches for the longest path in the directed acyclic graph and sequentially places each node involved in the longest path into the resource constraint list; in the control data flow graph and directed acyclic graph, it removes the nodes and edges of the longest path to obtain a new control data flow graph and directed acyclic graph. The resource allocation module repeats the above steps until all nodes in the control data flow graph and directed acyclic graph are placed in the resource constraint list, and then generates a hardware circuit structure based on the resource constraint list, and adjusts the hardware circuit interface involving the IP core operator.

[0125] Example 3

[0126] This embodiment provides a computer device including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the steps of the high-level synthesis tool optimization method based on the differential constraint system described in Example 1 are implemented.

[0127] Example 4

[0128] This embodiment provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the high-level synthesis tool optimization method based on the differential constraint system described in Example 1 are implemented.

[0129] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A high-level synthesis tool optimization method based on a differential constraint system, characterized in that: The following steps are involved: Obtain the circuit description of the input IP core, as well as the scheduling constraints and weights of the IP core; Convert the IP core into several basic blocks k , and converting the constraints of the IP core into differential constraint formulas; Based on the differential constraint formula, a differential constraint system is used to generate a control data flow graph and perform resource pre-allocation; Scanning, replacing, and scheduling operators in the control data flow graph based on pattern matching and operator mobility to optimize the control data flow graph; Resources are allocated according to the optimized control data flow graph to generate the hardware circuit structure.

2. The high-level synthesis tool optimization method based on the differential constraint system according to claim 1, characterized in that: The step of obtaining the input circuit description of the IP core, as well as the constraints and weights of the IP core, includes the following steps: Obtain the hardware circuit interface of the IP core according to the stub code of the IP core; Obtain the input and output behavior and input and output timing of the IP core based on the prototype code or simulation code of the IP core; Specify the constraints of the IP core through LUA scripts; Specify the weight of the IP core through the LUA script.

3. The high-level synthesis tool optimization method based on the differential constraint system according to claim 2, characterized in that: The constraint conditions include at least one of data dependency constraints, timing dependency constraints, and resource constraints; converting the constraint conditions of the IP core into a differential constraint formula includes the following steps: Map the corresponding input and output ports of the IP core to basic blocks bb k Internal scheduling variable sv, also basic block bb k Add super source node ssrc(bb k ) and super drain node ssnk(bb k ); Based on the data dependency constraint of the IP core, a first differential constraint formula is generated; its expression is as follows: Where, node v i ,v j As the basic block bb k There are two operation nodes with data dependency constraints inside, and node v i Must be at node v j Scheduling is completed before scheduling; e(v i ,v j ) represents node v i and v j The data dependency constraint edge, Represents basic block bb in the control data flow graph k The set of data dependency constraint edges in sv end (v i ) represents node v i The final value of the scheduling variable, sv beg (v j ) represents node v j The starting value of the scheduling variable; Based on the timing dependency constraint of the IP core, a second differential constraint formula is generated; its expression is as follows: sv beg (ssrc(bb k ))-sv end (ssnk(bb k ))≤-T lat,min sv end (ssnk(bb k ))-sv beg (ssrc(bb k ))≤T lat,max Where sv beg (ssrc(bb k )) represents the basic block bb k The starting value of the scheduling variable, sv end (ssnk(bb k )) represents the basic block bb k The final value of the scheduling variable T lat,max Represents the basic block bb k The number of clock cycles of the internal maximum delay path, T lat,min Represents the basic block bb k The number of clock cycles of the internal minimum delay path; Based on the resource constraints of the IP core, a third differential constraint formula is generated; its expression is as follows: In the formula, the node and nodes Represents a pair of nodes that do not belong to the IP core operator but have the same resources. Representation node The starting value of the scheduling variable, Representation node The starting value of the scheduling variable, Representation node The time required for execution, Representation node and Data dependency constraint edge; basic block bb k The resources do not participate in the scheduling reuse based on the differential constraint system.

4. The high-level synthesis tool optimization method based on differential constraint system according to claim 1, characterized in that: The method of using a differential constraint system to generate a control data flow graph and perform resource pre-allocation includes the following steps: Based on the circuit description of the IP core, a compiler front end is used to generate intermediate code from the high-level language code described at the behavioral level from the source code; Based on the differential constraint formula, a differential constraint system is used to generate a control data flow graph, and basic operators and dependency relationships of the intermediate code are mapped into nodes, control edges and basic blocks of the control data flow graph; According to the nodes and basic blocks of the control data flow graph, corresponding types of hardware resources are bound to obtain preliminary hardware resource usage and complete resource pre-allocation.

5. The high-level synthesis tool optimization method based on differential constraint system according to claim 4, characterized in that: Scanning, replacing, and scheduling operators in the control data flow graph includes the following steps: calculating the mobility of operators in the control data flow graph; Based on pattern matching and breadth-first search algorithms, the operator weights are scanned in descending order, and the operator set that meets the pattern is replaced with an operator sequence that matches the timing behavior information of the corresponding IP core. For operator combinations that meet the pattern matching, the IP core operator that matches the timing behavior information of the corresponding IP core is added, the corresponding control edge is connected to the input and output nodes of the IP core operator, all control edges of the original operator are cut off, and the original operator combination is deleted. Repeat the above steps until there are no alternative operators; then, based on the cut set idea, partition the high-weight IP cores, use the pipeline solution to balance the parallel path delays, and complete the optimization of the control data flow graph.

6. The high-level synthesis tool optimization method based on differential constraint system according to claim 5, characterized in that: The steps of partitioning high-weight IP cores based on the cut set concept and balancing parallel path delays using a pipeline solution include: Given a partitioned and pipelined control data flow graph G<V,E> , each vertex v∈V represents a function in the data flow design, and each edge e∈E represents a FIFO channel between functions; for each edge e∈E, the total delay of each path is expressed as: Where e.lat represents the extra delay inserted in the previous pipeline step, e.balance represents the balanced delay in the current step; {p1, p2} represents a pair of reconverging paths; For each edge e∈E, consider S i ≥S j +e ij.lat , then the additional balancing delay e ij.balance Expressed as: yes ij.balance =(S i -S j -e ij.lat ) Where S i -S j Represents vertex v i and v j The maximum delay between all paths, e ij.lat Indicates that the previous pipeline step is at vertex v i and v j The additional delay inserted in the longest path between ij.balance Indicates that the current pipeline step is at vertex v i and v j The balanced delay inserted in the longest path between them; Taking minimizing the total area overhead as the optimization goal and considering the bit width overhead of each edge, the objective function is constructed; its expression is as follows: Where, e ij.width Indicates that the current pipeline step is at vertex v i and v j Maximum data bit width between ij Represents vertex v i and v j The longest path edge between them; The constraint S i ≥S j +e ij.lat A differential constraint system is formed with the objective function, and the differential constraint system is treated as an integer linear programming problem and solved by a solver to obtain an optimized control data flow graph.

7. The high-level synthesis tool optimization method based on a differential constraint system according to any one of claims 1 to 6, characterized in that: The resource allocation according to the optimized control data flow graph includes the following steps: Create a directed acyclic graph based on the optimized control data flow graph and a resource constraint list; Finding the longest path in the directed acyclic graph based on a breadth-first algorithm, and sequentially placing each node involved in the longest path into the resource constraint list; Eliminating the nodes and edges of the longest path from the control data flow graph and the directed acyclic graph to obtain a new control data flow graph and directed acyclic graph; Repeat the above steps until all nodes in the control data flow graph and the directed acyclic graph are placed in the resource constraint list, then generate the hardware circuit structure according to the resource constraint list, and adjust the hardware circuit interface involving the IP core operator.

8. A high-level synthesis tool optimization system based on a differential constraint system, characterized in that: A high-level synthesis tool optimization method based on a differential constraint system according to any one of claims 1 to 7 is applied; wherein the system comprises: The data acquisition module is used to obtain the circuit description of the IP core, as well as the scheduling constraints and weights of the IP core; Differential constraint system for converting IP cores into basic blocks k , and converting the constraints of the IP core into differential constraint formulas; A resource pre-allocation module, configured to generate a control data flow graph and perform resource pre-allocation using a differential constraint system based on the differential constraint formula; A control data flow graph optimization module, configured to scan, replace, and schedule operators in the control data flow graph based on pattern matching and operator mobility, thereby optimizing the control data flow graph; The resource allocation module is used to allocate resources according to the optimized control data flow graph and generate the hardware circuit structure.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the high-level synthesis tool optimization method based on the differential constraint system according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the high-level synthesis tool optimization method based on a differential constraint system according to any one of claims 1 to 7 are implemented.

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