A method for regulating multi-value storage in non-volatile memory

Abstract

The present invention provides a method for regulating multi-value storage in a non-volatile memory, belonging to the field of semiconductor and CMOS hybrid integrated circuit technology. The present invention controls the voltage difference between the source and drain terminals of a transistor, continuously searches for the maximum amplitude of the transistor's gate voltage, and regulates the transistor's gate voltage using a linear rapid drop method, with the drop endpoint and speed set to 0 to 1 / 2 Vg and 1 ps to 10 ns, respectively. The resistance state of the resistive memory is changed through a set or reset operation, thereby achieving multi-value storage in the non-volatile memory. Because the present invention uses a non-constant voltage method to regulate the rapid drop of the gate voltage and utilizes the transistor's ability to turn off extremely quickly, the current is promptly controlled, thereby controlling the resistance range of the resistive memory. Furthermore, the low resistance range is conducive to reducing the operating voltage, thereby slowing down the degradation of device characteristics.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and CMOS hybrid integrated circuits, and in particular relates to a method for regulating and controlling multi-value storage in a non-volatile memory. Background Art

[0002] In recent times, with the rapid growth of data volumes and the approaching limit of Moore's Law, the drawbacks of the von Neumann architecture have become increasingly apparent. The fundamental reason lies in the architecture's separation of storage and computation, as well as the significant mismatch in speed between the two. Existing computing architectures consume a significant amount of time simply moving data. Consequently, demand for new non-volatile memory and computation-integrated devices has steadily increased. Among these, memristor-based deep neural network applications have been gaining increasing attention. These devices are compatible with current CMOS processes, offering simplified processing that facilitates high-density on-chip integration, while also enabling the efficient and low-power performance of complex neural network functions.

[0003] Among various new memristors, resistive random access memory (RRAM) is gaining industry favor due to its numerous advantages, including a simple three-layer architecture, low power consumption and high efficiency, fast read / write speeds, and multi-bit storage. Oxygen vacancy RRAM (OxRRAM) undergoes state changes at low operating voltages. Under the action of an electric field, oxygen vacancies (oxygen ions) undergo directional migration to form conductive filaments. The thickness and degree of fracture of the CF determine the device's state, such as 'high resistance HRS', 'low resistance LRS', and 'intermediate configuration MRS', enabling multi-bit storage. During operation, current limiting (Compliance Current) is often employed to ensure the device maintains the correct resistance state. Device resistance changes are primarily achieved through set operations (changing high resistance to low resistance / intermediate resistance) and reset operations (changing intermediate resistance / low resistance to high resistance).

[0004] At present, array-level RRAM usually adopts a cross-array structure. Although the passive cross-array can achieve the highest integration, it is also affected by crosstalk current interference, which leads to read and write errors and accelerates the degradation of device characteristics. Therefore, it is necessary to introduce a selector in series with the device in the cross-array, such as 1T1R, 1D1R, and 1S1R. Among them, 1T1R is widely used due to the maturity of the design and manufacturing process of transistors. On the one hand, the transistor is turned on to select the device to be operated. On the other hand, the transfer characteristic curve of T can be used to limit the current, so that the device is accurately placed in the corresponding state. For example, by changing the gate voltage to adjust the maximum current allowed to pass through the Drain / Source end. Figure 1As shown, the forward voltage operating terminal of the Set is set at the Drain terminal. If the RRAM is placed at the Source terminal, it is a reverse-connected device; if the RRAM is placed at the Drain terminal, it is a forward-connected device. In the prior art, when the source-side Set device is set to a low resistance, the gate-source potential difference is raised by ΔV because the high-resistance RRAM is located at the drain terminal of the transistor. However, when the drive voltage increases to a certain amplitude, causing the RRAM to be Set to a low resistance, the excessively high gate voltage causes the device to be placed in a nearly unlimited current state, thereby setting the RRAM to a lower resistance again.

[0005] Although in recent years, many scholars have made various types of adjustments to transistors from the perspective of operation, such as Figure 2 As shown in Figure 1, by applying DC operation mode, continuous pulse operation, etc. to operate the 1T1R structure, a continuously adjustable resistance change can be achieved. However, due to the many limitations of RRAM devices such as intrinsic fluctuations between devices and fluctuations between cycles, relying solely on a single voltage control method cannot ensure the precise resistance control of array-level memory devices. In addition, as Figure 3 As shown, the saturation current of a fixed aspect ratio transistor designed in pursuit of high density is often too large, which can further reduce the medium and high resistance ranges and switching ratios that can be selected for memory devices. Summary of the Invention

[0006] The object of the present invention is to provide a method for regulating multi-value storage in a non-volatile memory, which completes the device resistance state change through a set operation (high resistance is set to low resistance / middle resistance) and a reset operation (middle resistance / low resistance is set to high resistance), thereby realizing multi-value storage in a non-volatile memory.

[0007] The technical solutions provided by the present invention are as follows:

[0008] A method for regulating multi-value storage in a non-volatile memory, the non-volatile memory comprising a transistor and a resistive random access memory (RRAM), characterized in that a Set or Reset forward voltage operation terminal is set at the drain terminal of the transistor, the RRAM is placed at the source or drain terminal of the transistor, a linearly increasing forward voltage is applied to the drain terminal and gate of the transistor, and a common ground potential is applied to the source terminal and substrate of the transistor; the voltage difference between the source and drain terminals of the transistor is controlled, the maximum amplitude of the gate voltage of the transistor is continuously searched, and the gate voltage of the transistor is regulated in a linear rapid decrease manner, with the decrease endpoint and speed set to 0 to 1 / 2 Vg and 1 ps to 10 ns, respectively. The resistance state change of the RRAM is completed through a Set operation or a Reset operation, thereby realizing multi-value storage in the non-volatile memory.

[0009] The starting point of the gate voltage of the search transistor can be set to be from 0.5V to 3V, and the variation range can be set to be from 1mV to 0.5V, so as to achieve the Set operation or Reset operation of the resistive memory.

[0010] Furthermore, the resistive memory structure is electrode-resistive layer-electrode or electrode-resistive layer-oxygen storage layer-electrode.

[0011] Furthermore, the substrate is made of silicon.

[0012] Furthermore, the resistive switching layer of the resistive switching memory is TaO x , HfO x 、SiO x , VO2, NbO2, GST or SrTiO3 and other materials, or the organic material is parylene, with a thickness of 1nm to 100nm; the electrode uses an active electrode or an inert electrode, such as W, TiN, Pt, etc. with a thickness of 10nm to 500nm.

[0013] Furthermore, the transistors are of conventional MOS, FinFET, GAA and other types.

[0014] Compared with the prior art, the method of the present invention has the following beneficial effects:

[0015] The present invention provides a method for multi-value storage in a non-volatile memory, the purpose of which is to finely control the conductance / resistance of the resistive random access memory using a non-constant voltage electric pulse method, so as to solve the problems of the resistive random access memory in the current non-volatile memory, such as the resistance being easily set to ultra-low resistance, the difficulty in continuously changing the resistance state, and the low durability. Specifically, for the non-volatile memory structure, the transistor cannot accurately control the current that can pass through, which leads to a significant reduction in the resistance range that the resistive random access memory can be set to during the Set phase; and excessively high allowed current passing through causes the device to be easily set to ultra-low resistance, requiring a higher operating voltage for Reset, further affecting the reliability of the device. The present invention controls the transistor gate through non-constant voltage electric pulses, and fine-tuning can control the current and regulate the resistance range of the resistive random access memory, thereby realizing multi-state storage in the non-volatile memory; and the higher low resistance range is conducive to reducing the operating voltage, thereby slowing the degradation of device characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the existing 1T1R connection method;

[0017] Figure 2 In the prior art, the gate adopts a fixed constant voltage operation device with increasing voltage during the Set process;

[0018] Figure 3 It is based on the potential Overset problem brought by traditional technology;

[0019] Figure 4, is a schematic diagram of the present invention controlling the transistor current by adopting a method of rapidly decreasing the gate voltage;

[0020] Figure 5 The invention is based on the rapid shutdown of the transistor to accurately place the resistive random access memory in an intermediate resistance state. DETAILED DESCRIPTION

[0021] In order to make the above features and advantages of the present invention more clearly understood, the following specifically provides an embodiment and a detailed description thereof with reference to the accompanying drawings.

[0022] The present invention uses a 1T1R reverse-connected nonvolatile memory device as an example. Pt is used as the electrode material for the resistive switching memory, and TaOx is used as the resistive switching layer. The top electrode of the resistive switching memory is connected to the drain of the transistor. The device's forming (first set step) and set step are performed at the source of the transistor, and the reset operation is performed at the drain of the transistor. The transistor with the select function is a planar transistor with a gate length of 0.18 μm.

[0023] refer to Figure 4 The present invention controls the voltage difference between the source and drain terminals of the transistor, continuously searches for the highest amplitude of the transistor gate voltage, and uses a linear rapid decline method to regulate the gate voltage of the transistor, and the decline end point and speed can be set to 0~1 / 2Vg and 1ps~10ns, more preferably 0.6V and 1ns; controls the voltage difference between the source and drain terminals (the source is Set), and continuously fine-tunes the gate voltage amplitude, and the search interval starting point can be set from 0.5V to 3V, more preferably 1.2V, and the variation amplitude can be set to 1mV to 0.5V, more preferably 10mV, so as to achieve the Set operation of the resistive memory (high resistance is set to low resistance), and the operation time is between 1ps and 10ns. When the device is Set to the middle resistance range due to the appropriate gate voltage amplitude, the device is further current-limited and placed in the middle resistance state due to the rapid shutdown of the transistor. With different settings of the decline speed and the decline amplitude, further control of the device resistance state is achieved. The present invention adopts a non-constant voltage method to regulate the gate voltage to drop rapidly, such as Figure 5 As shown, the transistor has the characteristic of being able to turn off extremely quickly, which can timely control the current and further control the resistance range of the resistive memory to achieve polymorphic storage of the non-volatile memory.

[0024] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Those skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be based on the claims.

Claims

1. A method for regulating multi-value storage in a non-volatile memory, wherein the non-volatile memory comprises a transistor and a resistive random access memory, characterized in that: The forward voltage operation terminal of Set or Reset is set at the drain terminal of the transistor, the resistive memory is placed at the source or drain terminal of the transistor, a linearly increasing forward voltage is applied to the drain terminal and the gate terminal of the transistor, and a common ground potential is applied to the source terminal and the substrate of the transistor; the voltage difference between the source and drain terminals of the transistor is controlled, and the highest amplitude of the gate voltage of the transistor is continuously searched, the starting point of the search interval of the gate voltage of the transistor is set from 0.5V to 3V, and the variation range is set from 1 mV to 0.5V, and the gate voltage of the transistor is regulated by a linear fast decline method, and the decline end point and operation time are set to 0~1 / 2 Vg and 1ps~10ns respectively. The resistance state change of the resistive memory is completed through the set operation or reset operation, realizing multi-value storage of the non-volatile memory.

2. The method for controlling multi-value storage in a non-volatile memory according to claim 1, wherein: The structure of the resistive memory is electrode-resistive layer-electrode or electrode-resistive layer-oxygen storage layer-electrode.

3. The method for controlling multi-value storage in a non-volatile memory according to claim 1, wherein: The substrate is made of silicon.

4. The method for controlling multi-value storage in a non-volatile memory according to claim 2, wherein: The resistive switching layer of the resistive switching memory is TaO x , HfO x 、SiO x、 VO2, NbO2, GST SrTiO3 or organic materials.

5. The method for controlling multi-value storage in a non-volatile memory according to claim 2, wherein: The thickness of the resistive switching layer of the resistive switching memory is in the range of 1 nm to 100 nm.

6. The method for controlling multi-value storage in a non-volatile memory according to claim 2, wherein: The electrodes are active electrodes or inert electrodes.

7. The method for controlling multi-value storage in a non-volatile memory according to claim 2, wherein: The thickness of the electrode ranges from 10 nm to 500 nm.

8. The method for controlling multi-value storage in a non-volatile memory according to claim 1, wherein: The transistors are of conventional MOS, FinFET or GAA type.

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