Semiconductor device and method of manufacturing the same

Abstract

Semiconductor devices and methods of fabrication are provided in which a fence is formed over a substrate and a III-V material is grown over the substrate, where the fence blocks growth of the III-V material. Thus, a smaller area of III-V material is grown, thereby preventing stress that can occur with growth of larger sheets.

Description

Technical Field

[0001] This disclosure relates to a fenced semiconductor device and a method of manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. Summary of the Invention

[0004] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: depositing a fence between a first region and a second region of a semiconductor substrate; growing a III-V material layer on the semiconductor substrate after depositing the fence; removing the fence after growing the III-V material layer to form a first opening; and depositing a material over the semiconductor substrate, wherein the deposited material at least partially fills the first opening.

[0005] Other embodiments of this disclosure provide a method of manufacturing a semiconductor device, the method comprising: forming a fence between a first grain region and a second grain region of a semiconductor substrate; using the fence as a mask to grow a stack of III-V material layers in the first grain region and the second grain region, wherein after growing the stack of multiple III-V material layers, a portion of the III-V material layers has a first sidewall adjacent to the fence; removing the fence from the first region to expose a plurality of sidewalls of the stack of multiple III-V material layers; depositing one or more materials in the first region; and slicing the first grain region away from the first region, wherein after slicing, a portion of the one or more materials remains adjacent to the sidewalls of the stack of multiple III-V material layers.

[0006] Further embodiments of this disclosure provide a semiconductor device comprising: a semiconductor substrate, a plurality of III-V layers, and sidewall spacers. The semiconductor substrate has a first sidewall. The plurality of III-V layers are located above the semiconductor substrate, and these III-V layers include a second sidewall offset from the first sidewall. A surface of the semiconductor substrate extends between the first sidewall and the second sidewall. The sidewall spacers are in physical contact with the second sidewall and this surface of the semiconductor substrate, and the sidewall spacers are aligned with the first sidewall. Attached Figure Description

[0007] The nature of this disclosure is best understood when read in conjunction with the accompanying drawings from the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In practice, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration.

[0008] Figures 1A to 1B The diagram illustrates the formation of a fence on a wafer according to some implementation methods;

[0009] Figures 2A to 2B The diagram illustrates the formation of multiple layers according to some implementation methods;

[0010] Figures 3A to 3B The illustration depicts the removal of a fence according to some implementation methods;

[0011] Figures 4A to 4B The illustration depicts the formation of multi-layer stacks according to some implementation methods;

[0012] Figures 5A to 5B The diagram illustrates the slicing process according to some implementation methods;

[0013] Figures 6A to 6B Illustrations of multi-layered fences according to some implementation methods;

[0014] Figure 7 The illustration depicts a fence surrounding multiple grains according to some implementation methods;

[0015] Figures 8A to 8B The diagram illustrates the formation of a fence within a semiconductor die according to some embodiments.

[0016] [Symbol Explanation]

[0017] 100: Semiconductor wafers

[0018] 101:Substrate

[0019] 103: Grain Region

[0020] 105: Fence

[0021] 107: Lined area

[0022] 200: Multi-layer stacking

[0023] 201: Buffer layer

[0024] 203: Gradient Layer

[0025] 205: First III-V compound layer

[0026] 207: Second III-V compound layer

[0027] 209: Third III-V compound layer

[0028] 211: Active Layer

[0029] 301: First Opening

[0030] 401: Semiconductor die

[0031] 403: Multiple layers

[0032] 405: First Floor

[0033] 407: Second Floor

[0034] 409: Third Floor

[0035] 411: Fourth Floor

[0036] 501: Saw Blade

[0037] 503: Sidewall spacers

[0038] 601: First Fence Layer

[0039] 603: Second fence layer

[0040] 605: Third Fence Layer

[0041] 607: Fourth Fence Layer

[0042] 801: First subregion

[0043] 803: Second subregion

[0044] B-B': line

[0045] L1: First Length

[0046] L2: Second Length

[0047] L3: Third Length

[0048] H1: First Height

[0049] W1: First width

[0050] W2: Second width

[0051] W3: Third width Detailed Implementation

[0052] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and configurations are described below to simplify this disclosure. These are, of course, merely embodiments and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity and does not, by itself, indicate any relationship between the various implementations and / or configurations discussed.

[0053] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0054] Implementations will now be described with respect to specific structures and methods, in which fences are used to help reduce stress present in III-V materials grown over semiconductor wafers. However, the implementations described herein can be carried out in a variety of structures and methods, and the specific implementations described herein are not intended to be limited to the precise discussion presented.

[0055] Now for reference Figures 1A to 1B A top view of semiconductor wafer 100 is shown. Figure 1A ) and cross-sectional view through line B-B' ( Figure 1B The semiconductor wafer 100 has a substrate 101, a plurality of grain regions 103, and a fence 105 formed on the substrate 101. In one embodiment, the substrate 101 comprises a semiconductor material, such as silicon or silicon germanium, silicon carbide, sapphire, or may be an insulating or semi-insulating material, such as amorphous silicon oxide or aluminum oxide, which has been grown on a support substrate (in Figure 1B On (not shown separately), such as a silicon substrate, it is used for structural support. In another embodiment, substrate 101 may be a semiconductor-on-insulator, wherein the insulating material is a single-crystal material, which can be grown separately and then bonded to the support substrate using, for example, a fusion bonding process. Any suitable material and suitable formation method can be used.

[0056] In a particular embodiment, substrate 101 may be a silicon substrate, such as a semiconductor wafer, wherein the silicon has a crystal orientation of (111) and a lattice constant of 3.84, or may be a silicon-carbon substrate with a lattice constant of 3.08 Å. In this embodiment, the silicon may have a thickness between about 500 µm and about 1000 µm, and may have a diameter of 150 mm, 200 mm, 300 mm, or greater. However, any suitable size may be used.

[0057] Figures 1A to 1B Additionally, multiple grain regions 103 are depicted (from which...). Figure 1A The dashed boxes in the diagram indicate the regions where semiconductor dies 401 (not yet visible at this point in the process) are to be fabricated from and / or on substrate 101. It can be seen that substrate 101 is used to form a plurality of semiconductor dies 401, although... Figure 1A The illustration shows the manufacture of sixteen semiconductor chips 401, but this is for illustrative purposes, as any suitable number of semiconductor chips 401 can be manufactured.

[0058] A scribing region 107 is drawn between the various grain regions 103. The scribing region 107 is used to separate the individual grain regions 103 from each other and to prepare for the singulation process (see below). Figure 5B (Further description). The scribing region 107 can be formed by not placing functional structures (such as active devices) in the region intended for scribing region 107. Other structures, such as test pads or dummy metals for planarization, may be placed in the scribing region 107, but are not required for the function of semiconductor die 401 once it is separated from semiconductor wafer 100. The scribing region 107 may have a width between about 20 μm and about 180 μm, such as about 80 μm. However, any suitable size may be used.

[0059] Figures 1A to 1B The diagram also illustrates the placement and / or formation of a fence 105 on the substrate 101 and within a scribe region 107 between multiple grain regions 103. In one embodiment, the fence 105 is used to help prevent subsequent epitaxial growth from occurring in at least a portion of the scribe region 107 between the multiple grain regions 103. This restriction on subsequent growth processes helps alleviate stresses within the growth material that could damage subsequently formed apparatus.

[0060] In one embodiment, the fence 105 may be a material such as a photoresist. In a particular embodiment, the photoresist may comprise a photoresist polymer resin and one or more photoactive compounds (PACs) in a photoresist solvent. In one embodiment, the photoresist polymer resin may comprise a hydrocarbon structure (such as an alicyclic hydrocarbon structure) containing one or more groups that will decompose (e.g., acidic unstable groups) or otherwise react when mixed with an acid, base, or free radical generated by the photoactive compound. In one embodiment, the hydrocarbon structure comprises repeating units that form the backbone chain of the photoresist polymer resin. This repeating unit may include acrylates, methacrylates, crotonates, vinyl esters, maleate diesters, fumarate diesters, itconate diesters, (meth)acrylonitrile, (meth)acrylamide, styrene, vinyl ethers, combinations thereof, or the like.

[0061] In addition, the photoresist also contains one or more photoactive compounds. The photoactive compound can be a photoactive component, such as a photoacid generator, a photobase generator, a free radical generator, or the like, and can have a positive or negative effect. In embodiments where the photoactive compound is a photoacid generator, the photoactive compound can include triazine halides, onium salts, diazonium salts, aromatic diazonium salts, phosphonium salts, sulfonium salts, monazine salts, imide sulfonates, oxime sulfonates, diazonium disulfones, disulfones, o-nitrobenzene sulfonates, sulfonated esters, halosulfonyloxydicarboximides, diazonium disulfones, α-cyanoamine sulfonates, imide sulfonates, ketone diazonium sulfonates, sulfonyl diazonium esters, 1,2-di(arylsulfonyl)hydrazine, nitrobenzyl esters, and symmetrical triazine derivatives, suitable combinations thereof, or the like.

[0062] Individual components of the photoresist can be placed in a photoresist solvent to aid in mixing and placement. To facilitate mixing and placement, the photoresist solvent is selected, at least in part, based on the materials chosen for the photoresist polymer resin and the photoactive compound. Specifically, the photoresist solvent is selected such that the photoresist polymer resin and the photoactive compound can be uniformly dissolved and dispersed within the solvent.

[0063] In one embodiment, the photoresist solvent may be an organic solvent and may include any suitable solvent, such as ketones, alcohols, polyols, ethers, glycol ethers, cyclic ethers, aromatic hydrocarbons, esters, propionates, lactates, milk esters, alkylene glycol monoalkyl ethers, alkyl lactates, alkyl alkoxypropionates, cyclic lactones, cyclic monoketone compounds, alkylene carbonates, alkyl alkoxyacetic acid esters, alkyl pyruvate esters, lactates, glycol alkyl ether acetates, diethylene glycol, propylene glycol alkyl ether acetates, alkylene glycol alkyl ether esters, alkylene glycol monoalkyl esters, or the like.

[0064] Optionally, a photoresist crosslinking agent may be added to the photoresist. After exposure, the photoresist crosslinking agent reacts with the photoresist polymer resin within the photoresist, helping to increase the crosslinking density of the photoresist, which helps improve the resist pattern and resistance to dry etching. In one embodiment, the photoresist crosslinking agent may be a melamine-based reagent, a urea-based reagent, an ethylene-urea-based reagent, a propylene-urea-based reagent, an acetylenoid-based reagent, an aliphatic cyclic hydrocarbon having hydroxyl, hydroxyalkyl, or a combination thereof, an oxygen-containing derivative of an aliphatic cyclic hydrocarbon, a glycourea compound, an etherified amino resin, a combination thereof, or the like.

[0065] In one embodiment, a photoresist polymer resin, a photoactive compound, a free radical inhibitor, and any desired additives or other reagents are added to a photoresist solvent for application. Once added, the mixture is then mixed to achieve a homogeneous composition throughout the photoresist, ensuring the absence of defects caused by uneven mixing or non-constant composition of the photoresist. Once mixed, the photoresist can be stored before use or used immediately.

[0066] Once ready, the photoresist can be utilized by initially applying it. The photoresist can be applied to coat the upper exposed surface of the substrate 101, and can be applied using processes such as spin coating, dip coating, air knife coating, curtain coating, wire rod coating, gravure coating, lamination, extrusion coating, combinations thereof, or similar methods. In one embodiment, the photoresist can be applied such that, after development (further described below), it has a first height H1 between about 1 µm and about 20 µm above the surface of the substrate 101.

[0067] Once the photoresist is coated onto substrate 101, a photoresist pre-baking process is performed to cure and dry the photoresist before exposure, thus completing the photoresist coating. The curing and drying of the photoresist removes the photoresist solvent component, leaving behind the photoresist polymer resin, photoactive compounds, free radical inhibitors, photoresist crosslinking agents, and other selected additives. In one embodiment, the pre-baking can be performed at a temperature suitable for evaporating the photoresist solvent, such as between about 40°C and 150°C, although the precise temperature depends on the material selected for the photoresist. The pre-baking time is sufficient to cure and dry the photoresist, such as between about 10 seconds and about 5 minutes, such as about 90 seconds.

[0068] Once the photoresist is applied and cured, it can be imaged. In one embodiment, the photoresist can be exposed to patterned energy (e.g., patterned light), wherein the energy striking the photoresist will cause the photoactive compound to generate an acid, base, or free radical. This acid, base, or free radical will then continue to react with the polymer resin (and / or any desired additives, such as crosslinking agents) to create chemical and physical differences between photoresist regions affected by the patterned energy and those unaffected by the patterned energy.

[0069] After the photoresist has been exposed, post-exposure baking can be used to assist in the generation, dispersion, and reaction of acids / bases / free radicals generated during exposure due to pattern energy impacts on the photoactive compounds. This assistance helps to generate or enhance the chemical reaction, thereby creating a chemical difference between exposed and unexposed areas within the photoresist. These chemical differences also lead to differences in solubility between the exposed and unexposed areas. In one embodiment, this post-exposure baking can be performed at temperatures of approximately 40°C and approximately 200°C for a period of approximately 10 seconds to approximately 10 minutes. However, any suitable temperature and time can be used.

[0070] After the photoresist has been exposed and post-exposure baking has occurred, it can be developed using either a negative or positive developer, depending on the desired pattern of the photoresist. In one embodiment, the developer can be applied using spin coating, immersion, mixing, spraying, combinations thereof, or similar methods. However, any suitable materials and processes can be used to develop the photoresist.

[0071] In one embodiment, a plurality of fences 105 are placed within a plurality of scribed regions 107 of the substrate 101 and extend across the substrate 101. Thus, the fences 105 may be formed having a first width W1 between about 1 µm and about 150 µm, and a first length L1 (e.g., 8 inches, 12 inches, etc.) between about 1 µm and the size of the substrate 101. However, any suitable size may be used.

[0072] Furthermore, in the illustrated embodiment, the fence 105 will surround the region containing the individual grain region 103. Therefore, the fence 105 may surround a region having a second width W2 and a second length L2, wherein the second width W2 and the second length L2 are based on the final desired size of the grain to be formed. However, any suitable size can be used.

[0073] However, while using photoresist to form the fence 105 is one feasible implementation, in another implementation, the fence 105 may contain a material whose lattice constant does not match that of the film to be grown (hereinafter referred to as...). Figures 2A to 2B(Further description). In a particular embodiment, fence 105 may comprise a layer of composite oxide, such as silicon oxide (SiO2), titanium oxide (TiO2), combinations thereof, or the like, or a layer of dielectric such as silicon nitride (Si3N4). However, any suitable material may be used.

[0074] In embodiments where a composite oxide is used to form a fence 105, the fence 105 is formed by initially depositing the composite oxide to a first height H1 using a deposition process (such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of these, or the like). However, any suitable material and any suitable process can be used.

[0075] Once the composite oxide is deposited, it can be patterned to the desired size and shape. For example, in some embodiments, the composite oxide can be patterned using an optical lithography masking and etching process, wherein it is placed, exposed, and developed with a photoresist (e.g., a three-layer photoresist), and then used as a mask during a directional etching process (such as a reactive ion etching process). However, any suitable patterning process can be used.

[0076] Furthermore, although fence 105 has been illustrated and described above as being formed as a straight line or fence shape, this is intended for illustration and not limitation of this embodiment. Rather, any suitable shape for a fence, such as a circle or triangle, or any combination of shapes, may be used, and all such shapes are fully intended to be included within the scope of this embodiment.

[0077] Figures 2A to 2B The diagram illustrates the formation of a multilayer stack 200, including a buffer layer 201, a gradient layer 203, a first III-V compound layer 205, a second III-V compound layer 207, a third III-V compound layer 209, and an active layer 211. According to some embodiments, a buffer layer 201 is first formed over a substrate 101, serving as a buffer layer and / or transition layer for subsequently formed overlays. The buffer layer 201 can be epitaxially grown using metal-organic vapor phase epitaxy (MOVPE). The buffer layer 201 can serve as an interface that reduces lattice mismatch between the substrate 101 and the subsequently formed first III-V compound layer 205. In some embodiments, the buffer layer 201 includes an aluminum nitride (AlN) layer (having a lattice constant of, for example, 3.11 Å) with a thickness between about 10 nanometers (nm) and about 300 nanometers.

[0078] The buffer layer 201 may comprise a single layer or multiple layers. For example, the buffer layer 201 may comprise a low-temperature AlN layer formed at a temperature between about 800 °C and about 1200 °C, and a high-temperature AlN layer formed at a temperature between about 1000 °C and about 1400 °C. In some embodiments, the low-temperature AlN layer has a thickness between about 10 nanometers (nm) and about 100 nanometers, and the high-temperature AlN layer has a thickness between about 100 nanometers (nm) and about 200 nanometers.

[0079] A gradient layer 203 is formed above the buffer layer 201. In one embodiment, the gradient layer 203 may also serve as a buffer layer and may be epitaxially grown, for example, using metal-organic vapor phase epitaxy. The gradient layer 203 may include an aluminum gallium nitride (AlGaN) layer having a thickness ranging from about 500 nm to about 1000 nm. The gradient layer 203 may be a gradient buffer layer, meaning that within a portion or the total thickness of the gradient layer 203, the relative amounts of individual aluminum and / or gallium contents change with depth in the layer. The relative amounts may gradually change with distance from the substrate 101 to reduce lattice parameters.

[0080] For example, in one embodiment, gradient layer 203 may comprise three or more sublayers, each containing a different percentage of aluminum and / or gallium. In some exemplary embodiments, a first sublayer has an aluminum percentage between about 65% and about 85%, a second sublayer has an aluminum percentage between about 35% and about 60%, and a third sublayer has an aluminum percentage between about 10% and about 30%. However, any suitable number of sublayers and the percentages within each sublayer can be used.

[0081] A first III-V compound layer 205 is grown over a gradient layer 203. In some embodiments, the first III-V compound layer 205 is an epitaxially grown gallium nitride (GaN) layer (having a lattice constant of, for example, 3.19 Å) using, for example, metal-organic vapor phase epitaxy, during which gallium-containing and nitrogen-containing precursors are used. Gallium-containing precursors may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable gallium-containing chemicals. Nitrogen-containing precursors may include ammonia (NH3), tributylamine (TBAm), phenylhydrazine, or other suitable chemicals. In some exemplary embodiments, the III-V compound layer 205 has a thickness ranging from about 0.5 micrometers to about 10 micrometers and may be undoped. In other embodiments, the first III-V compound layer 205 is unintentionally doped, such as by lightly doping with n-type dopants due to the precursors used to form the first III-V compound layer 205, without the intentional addition of dopants that could cause the first III-V compound layer 205 to be n-type or p-type.

[0082] A second III-V compound layer 207 is grown on and in contact with the first III-V compound layer 205. In one embodiment, the second III-V compound layer 207 has a band gap higher than that of the first III-V compound layer 205, thereby forming an interface between the first III-V compound layer 205 and the second III-V compound layer 207. In some embodiments, the second III-V compound layer 207 is an AlGaN layer and can be epitaxially grown on the first III-V compound layer 205 via, for example, metal-organic vapor phase epitaxy. When formed from AlGaN, aluminum-containing precursors, gallium-containing precursors, and nitrogen-containing precursors can be used to grow the second III-V compound layer 207. The aluminum-containing precursor may include trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals. The gallium-containing precursor and the nitrogen-containing precursor may be selected from the same candidate precursors used to form the first III-V compound layer 205. In some exemplary embodiments, the second III-V compound layer 207 has a thickness ranging from about 2 nm to about 50 nm.

[0083] Once the second III-V compound layer 207 is formed, a third III-V compound layer 209 can be grown over the second III-V compound layer 207. In one embodiment, the third III-V compound layer 209 may be a III-V compound, such as gallium nitride, grown via, for example, metal-organic vapor phase epitaxy. However, any suitable material and any suitable process can be used.

[0084] Furthermore, the third III-V compound layer 209 may be doped. In some embodiments, the third III-V compound layer 209 may be doped with p-type dopant, n-type dopant, or different regions may be doped with different dopant. Any suitable dopant or combination of dopant can be used.

[0085] Once the third III-V compound layer 209 is formed, an active layer 211 can be grown over it. In one embodiment, the active layer 211 serves as an active layer for forming active and passive devices that are part of an integrated circuit. In one embodiment, the active layer 211 may be a III-V compound, such as gallium nitride, grown via, for example, metal-organic vapor phase epitaxy. However, any suitable material and any suitable process can be used.

[0086] Furthermore, the active layer 211, as part of the layer used to form the active device, may be doped. In some embodiments, the active layer 211 may be doped with p-type dopants, n-type dopants, or different regions may be doped with different dopants. Any suitable dopant or combination of dopants may be used.

[0087] However, by utilizing the fence 105 to prevent growth between certain regions, the individual grown regions of the multiple grain regions 103 grown thereon have smaller areas. The growth of multiple smaller regions helps to reduce the stress generated when the larger region (e.g., the region above the entire substrate 101) is grown as a single, continuous sheet. By reducing the stress, these stresses will not damage the subsequently manufactured devices.

[0088] Furthermore, in some embodiments, the combined height of the multiple stacks 200 may be less than the first height H1 of the fence 105, such as in Figure 2B The illustration is shown in the figure. However, this is intended for illustrative purposes and not for limitation. Specifically, in other embodiments, the combined height of the multiple stacks 200 may be greater than the first height H1 of the fence 105.

[0089] Figures 3A to 3B The diagram illustrates the removal of fence 105 to form a plurality of first openings 301 within a multi-layer stack 200. In embodiments where fence 105 is formed using a photoresist material, an ashing process can be used to remove fence 105, thereby increasing the temperature of the photoresist until the photoresist undergoes thermal decomposition and can be easily removed.

[0090] In other embodiments using materials such as composite oxides, an etching process (such as a wet etching process) can be used to remove the fence 105. In such embodiments, a mask may optionally be used to protect the top surface of the third III-V compound layer 209, and a liquid etchant that selectively removes the material of the fence 105 may be used until the material of the fence 105 is removed. The etching process may terminate on the surface of the substrate 101, or in other embodiments, the etching process may continue and over-etch into the substrate 101. However, any suitable method and etchant may be used.

[0091] Figures 4A to 4B The illustration depicts the deposition of multiple layers 403 for forming a semiconductor die 401 using a third III-V compound layer 209. In one embodiment, the multiple layers 403 comprise one or more layers for fabricating active devices from the third III-V compound layer 209 and other passive devices, forming conductive connections to the active devices via dielectric layers, forming conductive wiring between the multiple active devices to form a functional circuit, passivating the top surface of the conductive wiring layer, and providing electrical connections through the passivation layer. However, any suitable number and type of layers can be used.

[0092] For example, in various steps of the manufacturing process of semiconductor die 401, material may be deposited, and then a portion of the deposited material may be removed to achieve the desired shape and function of different structures. For example, for active devices such as transistors, a dummy gate is formed by depositing material and then etching away the unwanted portions of this material, forming source / drain regions, depositing an interlayer dielectric layer around the dummy gate and above the source / drain regions, removing the dummy gate, and forming the gate dielectric and gate electrode.

[0093] Similarly, after fabricating the active devices, redistribution layers can be formed to provide connectivity and interconnection with various active devices. In some embodiments, one or more dielectric layers are deposited, followed by the formation of multiple openings through the dielectric layers using a damascene or dual damascene process, and then these openings are filled with a conductive material. Once formed, a passivation layer is placed to protect the structure.

[0094] However, when these materials are deposited, they will not only be deposited within the multiple grain regions 103, but also within the first opening 301. Therefore, for each deposited material, the deposited material can remain as a layer within the first opening 301, or it can be removed in a subsequent etching process, thereby allowing any desired number of material layers to remain within the first opening 301.

[0095] For example, especially Figure 4B In the illustrated embodiment, after the semiconductor die 401 is formed, the first opening 301 can be filled with four layers of material deposited at different points during the fabrication of the semiconductor die 401. For example, the first opening 301 may be filled with a first layer 405, a second layer 407, a third layer 409, and a fourth layer 411. In one embodiment, the first layer 405 may be a first dielectric material (e.g., PBO), which is deposited to surround the dummy gate electrode. Similarly, the second layer 407 may be a conductive material for forming the gate electrode, the third layer 409 may be a dielectric material for the interlayer dielectric layer, and the fourth layer 411 may be a passivation layer. All other plurality of deposited layers have been patterned to allow for the removal of this portion of the deposited material from the first opening 301.

[0096] By depositing various materials for multiple layers 403 into the first opening 301, materials that do not specifically grow from the substrate 101 are present at the bottom of the first opening 301 (and, for example, in physical contact with the substrate 101). Therefore, these materials do not share the same lattice constant as the substrate 101.

[0097] Figures 5A to 5BThe illustration shows that once the semiconductor die 401 is formed and the first opening 301 is filled, the semiconductor wafer 100 can be diced to separate the individual semiconductor dies 401. In one embodiment, this can be achieved by using a saw blade ( Figure 5B The cutter (marked by box 501) performs a single dicing by slicing through multiple layers 403 within the first opening 301 of the scribing region 107, thereby separating one individual semiconductor die 401 from another. However, as those skilled in the art will recognize, the single semiconductor wafer 100 diced using a saw blade 501 is merely an illustrative embodiment and is not intended to be limiting. Other methods for dicing can also be used, such as dicing the single semiconductor wafer 100 using one or more etching processes. These methods, and any other suitable methods, can be used to diced the single semiconductor wafer 100.

[0098] During the cut-out process, instead of simply filling the sawn opening 301, multiple layers 403 become sidewall spacers 503, which cover the sidewalls of the multilayer stack 200 and fill the area between the sidewalls of the multilayer stack 200 and the surface of the substrate 101. Furthermore, the sidewall spacers 503 are also aligned with the sidewalls of the substrate 101. In some embodiments, the sidewall spacers 503 may have a third width W3 of less than about 100 µm. However, any suitable size can be utilized.

[0099] Furthermore, in some embodiments, each of the plurality of layers 403 (e.g., first layer 405, second layer 407, third layer 409, and fourth layer 411) may be formed or shaped to have decreasing thickness as the sidewall spacers 503 extend from the multilayer stack 200. For example, the second layer 407 may be less thick than the first layer 405, the third layer 409 may be less thick than the second layer 407, and the fourth layer 411 may be less thick than the third layer 409. These thicknesses may be achieved during the manufacturing process of the respective layers (e.g., by depositing layers of different thicknesses or etching layers within the first opening 301 after deposition), or by thinning the outer layer (e.g., the fourth layer 411) with a saw blade 501 during a single-piece cutting process. Any suitable method or combination of methods may be utilized.

[0100] Figure 6A Another embodiment is illustrated, wherein instead of including as described above... Figures 1A to 1B The single-layer material described herein, the fence 105 is formed of multiple layers, such as a first fence layer 601, a second fence layer 603, a third fence layer 605, and a fourth fence layer 607. However, despite regarding Figure 6A The implementation with four layers is illustrated and described, but this is intended to be illustrative rather than limiting, as any suitable number of layers, such as two, three, or more than four layers, can be used.

[0101] In one embodiment, the first fence layer 601 may comprise one or more of the materials described above for a single-layer fence 105. For example, the first fence layer 601 may comprise a photoresist material deposited using a spin coating process, or it may be a composite oxide deposited using a deposition process. However, any suitable material and any suitable process may be used.

[0102] The second barrier layer 603 may be made of a different material than the first barrier layer 601, but may still be similar to the first barrier layer 601, such as by using a material such as a photoresist or a composite oxide. The second barrier layer 603 may be deposited on the first barrier layer 601 using one of the placement methods (e.g., spin coating or deposition process) and may be placed prior to any patterning or removal of the material of the first barrier layer 601. However, any suitable material and any suitable process may be used.

[0103] The third barrier layer 605 may be made of a different material than the second barrier layer 603, but may still be similar to the first barrier layer 601, such as by using a material such as a photoresist or a composite oxide. The third barrier layer 605 may be deposited on the second barrier layer 603 using one of the placement methods (e.g., spin coating or deposition processes), and may be placed prior to any patterning or removal of the material of the second barrier layer 603 or the first barrier layer 601. However, any suitable material and any suitable process may be used.

[0104] The fourth barrier layer 607 may be made of a different material than the third barrier layer 605, but may still be similar to the first barrier layer 601, such as by using a material such as a photoresist or a composite oxide. The fourth barrier layer 607 may be deposited on the third barrier layer 605 using one of the placement methods (e.g., spin coating or deposition processes), and may be placed prior to any patterning or removal of the materials of the third barrier layer 605, the second barrier layer 603, and the first barrier layer 601. However, any suitable material and any suitable process may be used.

[0105] Once each of the first fence layer 601, second fence layer 603, third fence layer 605, and fourth fence layer 607 has been deposited, the layers are then patterned to form a multi-layered stack of fences 105 in the desired shape. In a particular embodiment, the multi-layered stack is patterned using an optical lithography masking and etching process, thereby applying, exposing, and developing photoresist, followed by removing unprotected portions of the first fence layer 601, second fence layer 603, third fence layer 605, and fourth fence layer 607 using one or more etching processes or other removal processes. However, any suitable method for patterning the first fence layer 601, second fence layer 603, third fence layer 605, and fourth fence layer 607 may be used.

[0106] By depositing each of the first fence layer 601, the second fence layer 603, the third fence layer 605, and the fourth fence layer 607, and then patterning them all, the fence 105 will have sidewalls comprising multiple materials. For example... Figure 6A As shown, in this embodiment, the sidewalls of the fence 105 include the materials of the first fence layer 601, the second fence layer 603, the third fence layer 605, and the fourth fence layer 607.

[0107] By using a multi-layered structure to form the fence 105, all the benefits of utilizing a multi-layered structure can be obtained. For example, using a specific material with the desired etching properties allows for greater control over the overall shape that can be obtained, such as by being able to obtain more vertical sidewalls for the fence 105.

[0108] Figure 6B Another multi-layered embodiment of the fence 105 is illustrated, which utilizes a first fence layer 601, a second fence layer 603, a third fence layer 605, and a fourth fence layer 607. However, in this embodiment, instead of depositing each of the layers before any patterning, each of the layers is deposited before the overcoat layer is deposited, and then patterning is performed. For example, the first fence layer 601 is deposited as described above, and then the first fence layer 601 is patterned before the second fence layer 603 is deposited. Then the second fence layer 603 is deposited and patterned before the third fence layer 605 is deposited, the third fence layer 605 is deposited and patterned before the fourth fence layer 607 is deposited, and then the fourth fence layer 607 is deposited and patterned.

[0109] By depositing and patterning each of the first fence layer 601, the second fence layer 603, the third fence layer 605, and the fourth fence layer 607 before depositing the overcoat layer, the fence 105 will maintain a multi-layered structure. However, this multi-layered structure will have a single material along its sidewalls. For example, in Figure 6B In the embodiment shown, fence 105 will have sidewalls containing only the material of the fourth fence layer 607.

[0110] However, despite the above, according to Figures 6A to 6B The discussion and illustration of a fence 105 with a four-layer multi-story structure are provided, but this precise number of layers is for illustrative purposes only and not as a limitation. Instead, any suitable number of layers can be used as needed, such as two, three, the four shown, or five or more layers.

[0111] Furthermore, once fence 105 is formed, it can be handled according to the above-mentioned... Figures 2A to 5BThe description continues this process. Specifically, a multi-layered stack 200 can be grown, a barrier 105 can be removed to form a first opening 301, an additional layer can be deposited to fill the first opening 301, and a dicing device can be used via the first opening 301. However, by growing a multi-layered stack 200 as described above, the amount of stress within the multi-layered stack 200 is reduced, thus less damage will occur during the wafer fabrication process and the dicing process.

[0112] Figure 7 Another embodiment is illustrated, wherein the fence 105 is manufactured within a plurality of scribe regions 107 between a plurality of grain regions 103. However, in this embodiment, instead of forming the fence 105 between each and every grain region 103, the fence 105 is formed only between some grain regions 103. Thus, some scribe regions 107 have fences 105 formed within the scribe region 107, while other scribe regions 107 do not have fences 105 formed within the scribe region 107.

[0113] In addition, Figure 7 In the illustrated embodiment, a fence 105 may be formed to create a region comprising a plurality of grain regions 103. For example, in some embodiments, the fence 105 may be formed to surround two, three, four, or five of the grain regions 103. However, any suitable number of grain regions 103 may be located within a single region surrounded by the fence 105.

[0114] Figure 8A As illustrated, while the fence 105 may be formed within a plurality of scribed regions 107 surrounding a plurality of grain regions 103, the fence 105 may also be formed within each of the plurality of grain regions 103 to surround and protect a smaller region. For example, in some embodiments, the plurality of grain regions 103 may include a first sub-region 801 and a second sub-region 803. In embodiments, the first sub-region 801 may be a region such as a high-voltage region, while the second sub-region 803 may be a region such as a non-high-voltage region. However, any suitable type of sub-region may be utilized.

[0115] In one embodiment, the fence 105 may be fabricated around one or more first sub-regions 801, or around one or more second sub-regions 803, and may have a third length L3 that is less than the length of the grain region 103. Any suitable or desired combination of the multiple regions may be surrounded by the fence 105.

[0116] Figure 8B As illustrated, once a fence 105 is formed around the desired area, this process can proceed as described above. Figures 2A to 4BThe process continues. Specifically, a multi-layered stack 200 can be grown, the fence 105 can be removed to form a first opening 301, and multiple layers 403 are deposited to fill the first opening 301. However, by growing a multi-layered stack 200 as described above, the amount of stress within the multi-layered stack 200 is reduced, and therefore less damage will occur during the wafer fabrication process and the dicing process.

[0117] However, because the fence 105 in this embodiment is formed within each of the plurality of grain regions 103, and may or may not be formed within the scribing region 107, there is no single layer within the plurality of grain regions 103. Therefore, the plurality of layers 403 are held in appropriate positions within the grain regions 103 to help protect and separate the different regions (e.g., the first sub-region 801 and the second sub-region 803) formed within the plurality of grain regions 103.

[0118] By utilizing the process described herein, stresses formed during the growth of III-V layers can be reduced or eliminated. Specifically, by using fence 105 to separate a large growth region into multiple smaller growth regions, each of these separate regions will experience less stress during the growth process. Therefore, stress is eliminated during subsequent processes (such as dicing), where stress can cause undesirable damage, such as spherical defects or cracks along the wafer edge. Thus, stress-induced damage can be mitigated without the need for more expensive processes (such as superlattice processes). Furthermore, larger wafers can be utilized with less damage, thereby increasing the overall yield of the manufacturing process.

[0119] According to one embodiment, a method of manufacturing a semiconductor device includes: depositing a fence between the first region and the second region of a semiconductor substrate; growing a III-V material layer on the semiconductor substrate after depositing the fence; removing the fence to form a first opening after growing the III-V material layer; and depositing material on the semiconductor substrate, wherein the deposited material at least partially fills the first opening. In one embodiment, the method further includes cutting a single piece of material through the first region to exit the second region. In one embodiment, the first and second regions are portions of a single semiconductor grain region. In one embodiment, the III-V material is gallium nitride. In one embodiment, the fence comprises a photoresist. In one embodiment, the fence has a lattice constant different from that of the semiconductor substrate. In one embodiment, the fence comprises two or more layers of different fence materials.

[0120] According to another embodiment, a method of manufacturing a semiconductor device includes: forming a fence between a first grain region and a second grain region of a semiconductor substrate; using the fence as a mask, growing a stack of multiple III-V material layers on the first and second grain regions, wherein after growing the stack of multiple III-V material layers, a portion of these III-V material layers has a first sidewall adjacent to the fence; removing the fence from the first region to expose a plurality of sidewalls of the stack of multiple III-V material layers; depositing one or more materials into the first region; and slicing the second grain region away from the first grain region, wherein after slicing, a portion of the one or more materials remains adjacent to the sidewalls of the stack of multiple III-V material layers. In one embodiment, forming the fence includes forming multiple layers of different fence materials. In one embodiment, forming the fence involves depositing any of the different fence materials before patterning any different fence materials. In one embodiment, forming the fence involves depositing and patterning the respective layers separately. In one embodiment, forming the fence includes forming a photoresist that forms a physical contact with the semiconductor substrate. In one embodiment, the method further includes: forming a second fence between a first intergranular region and a second intergranular region; and removing the second fence from the second region. In one embodiment, cutting the second grain region away from the first grain region does not remove any material from the second region.

[0121] According to yet another embodiment, a semiconductor device includes: a semiconductor substrate having a first sidewall; a plurality of III-V layers above the semiconductor substrate, the plurality of III-V layers including a second sidewall offset from the first sidewall, a surface of the semiconductor substrate extending between the first sidewall and the second sidewall; and a sidewall spacer physically in contact with the second sidewall and the surface of the semiconductor substrate, the sidewall spacer being aligned with the first sidewall. In one embodiment, the sidewall spacer comprises a plurality of layers of different materials. In one embodiment, each of the plurality of layers of different materials has a different thickness. In one embodiment, a first layer of the plurality of layers of different materials is aligned with the first sidewall and has a thickness less than any other layer among the plurality of layers of different materials. In one embodiment, the plurality of III-V layers includes a third sidewall and a fourth sidewall, the third sidewall facing the fourth sidewall, wherein the plurality of layers of different materials extends from the second sidewall to physically contact both the third and fourth sidewalls. In one embodiment, the plurality of III-V layers comprises gallium nitride.

[0122] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A fence is deposited between a first region of a semiconductor substrate and a second region of the semiconductor substrate; After the fence is deposited, a III-V material layer is grown on the semiconductor substrate; Use a mask to cover the III-V material layer; After the III-V material layer has grown, the fence is removed while the shield is present to form a first opening; as well as A material is deposited on the semiconductor substrate, wherein the deposited material at least partially fills the first opening.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, It also includes cutting through the material, separating the first area from the second area.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first region and the second region are portions of a single semiconductor grain region.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The III-V material is gallium nitride.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The fence contains a light resist.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The fence has a lattice constant that differs from that of the semiconductor substrate.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The fence consists of two or more layers of different fencing materials.

8. A method for manufacturing a semiconductor device, characterized in that, The method includes: A fence is formed between a first grain region and a second grain region on a semiconductor substrate; Using the fence as a shield, a stack of multiple III-V material layers is grown on the first grain region and the second grain region, wherein after the stack of the multiple III-V material layers is grown, a portion of the multiple III-V material layers has a first sidewall adjacent to the fence, and the combined height of the stack of the multiple III-V material layers is less than the height of the fence. Remove the fence from a first area to expose the multiple sidewalls of the stack of the multiple III-V material layers; One or more materials are deposited in the first region; as well as The first grain region is cleaved away from the first region, wherein after the cleavage, a portion of the one or more materials remains adjacent to the multiple sidewalls of the stack of the multiple III-V material layers.

9. The method of manufacturing a semiconductor device according to claim 8, characterized in that, The steps involved in forming the fence include: forming multiple layers of different fence materials.

10. The method of manufacturing a semiconductor device according to claim 9, characterized in that, The fence is formed by depositing each of the different fence materials before patterning any of them.

11. The method of manufacturing a semiconductor device according to claim 9, characterized in that, The fence is formed by separately depositing and patterning the individual layers.

12. The method of manufacturing a semiconductor device according to claim 8, characterized in that, The step of forming the fence includes: forming a photoresist that is in physical contact with the semiconductor substrate.

13. The method of manufacturing a semiconductor device according to claim 8, characterized in that, Further includes: A second fence is formed between a first intergranular region and a second intergranular region; and Remove the second fence from the second area.

14. The method of manufacturing a semiconductor device according to claim 13, characterized in that, The cutting process does not remove any material from the second region when the first grain region leaves the second region.

15. A semiconductor device, characterized in that, Include: A semiconductor substrate having a first sidewall; A plurality of III-V group layers are disposed above the semiconductor substrate, the plurality of III-V group layers including a second sidewall that is offset from the first sidewall, and a surface of the semiconductor substrate extends between the first sidewall and the second sidewall; as well as A sidewall spacer comprises multiple layers of different materials, including a dielectric material layer, a conductive material layer, an interlayer dielectric layer, and a passivation layer. The sidewall spacer is in physical contact with the second sidewall and the surface of the semiconductor substrate, and the sidewall spacer is aligned with the first sidewall.

16. The semiconductor device according to claim 15, characterized in that, The sidewall spacer fills the area between the second sidewall of the III-V layers and the surface of the semiconductor substrate.

17. The semiconductor device according to claim 15, characterized in that, Each layer of these different materials has a different thickness.

18. The semiconductor device according to claim 17, characterized in that, A first layer of these different materials is aligned with the first sidewall and has a thickness less than any other layer among these different materials.

19. The semiconductor device according to claim 16, characterized in that, These III-V layers include a third sidewall and a fourth sidewall, the third sidewall facing the fourth sidewall, wherein the layers of different materials extend from the second sidewall to physically contact both the third and fourth sidewalls.

20. The semiconductor device according to claim 15, characterized in that, The plurality of III-V layers contain gallium nitride.

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