Semiconductor package

Abstract

A semiconductor package includes a substrate, a plurality of interposers, a plurality of chips, and a dummy interposer. The plurality of interposers are stacked on the substrate. The plurality of chips are on the plurality of interposers. The chips are electrically connected to the interposers. The dummy interposer is between the interposers and the substrate and is electrically connected to the interposers. The chips are not between the dummy interposer and the interposers.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor structure, and particularly to a semiconductor package. BACKGROUND

[0002] In the packaging process of integrated circuits, semiconductor chips can be stacked, and can be combined to other packaging components (e.g. interposer and package substrate). Thus, the resulting package can be referred to as a three-dimensional (3D) semiconductor package. However, how to further improve the design flexibility and package density of semiconductor packages is a current continuous effort. SUMMARY

[0003] The present application provides a semiconductor package, which can improve the design flexibility and package density of semiconductor packages.

[0004] The present application provides a semiconductor package, which can improve the design flexibility and package density of semiconductor packages.

[0005] According to an embodiment of the present application, in the above semiconductor package, the interposer can be electrically connected to the substrate.

[0006] According to an embodiment of the present application, in the above semiconductor package, the chip can be electrically connected to the substrate.

[0007] According to an embodiment of the present application, in the above semiconductor package, the dummy interposer can be electrically connected to the substrate.

[0008] According to an embodiment of the present application, in the above semiconductor package, the dummy interposer can be electrically connected to the chip via the interposer.

[0009] According to an embodiment of the present application, in the above semiconductor package, the dummy interposer can have a portion extending in a direction away from the base.

[0010] According to an embodiment of the present application, in the above semiconductor package, the dummy interposer can have a plurality of upper surfaces with different heights.

[0011] According to an embodiment of the present application, in the above semiconductor package, the dummy interposer can have a plurality of lower surfaces with different heights.

[0012] According to an embodiment of the present application, in the above semiconductor package, the dummy interposer can be located between two adjacent interposers in the stack.

[0013] According to an embodiment of the present application, in the semiconductor package, the dummy interposer is located between another dummy interposer and the interposer.

[0014] According to an embodiment of the present application, in the semiconductor package, the dummy interposer is located between another dummy interposer and the interposer.

[0015] According to an embodiment of the present application, in the semiconductor package, the size of the two adjacent interposers in the stack decreases in a direction away from the substrate.

[0016] According to an embodiment of the present application, in the semiconductor package, the size of the two adjacent interposers in the stack increases in a direction away from the substrate.

[0017] According to an embodiment of the present application, in the semiconductor package, a dummy chip is further included. The dummy chip is located between the interposer and the substrate and is electrically connected to the interposer.

[0018] According to an embodiment of the present application, in the semiconductor package, the chip is not located between the dummy chip and the interposer.

[0019] According to an embodiment of the present application, in the semiconductor package, the dummy chip is located between the two adjacent interposers in the stack.

[0020] According to an embodiment of the present application, in the semiconductor package, the dummy chip is located between the interposer and the dummy interposer.

[0021] According to an embodiment of the present application, in the semiconductor package, the dummy chip is located between the two adjacent dummy interposers in the stack.

[0022] According to an embodiment of the present application, in the semiconductor package, the dummy chip is electrically connected to the chip via the interposer.

[0023] According to an embodiment of the present application, in the semiconductor package, the dummy interposer is located between the dummy chip and the interposer.

[0024] Based on the above, in the semiconductor package according to the present application, since the dummy interposer has the support function and the electrical connection function and the configuration mode and the shape of the dummy interposer can be adjusted according to the requirement, the design of the semiconductor package can be more flexible, and the packaging density can be improved.

[0025] In order to make the above features and advantages of the present application more apparent, specific embodiments are described below in detail, and are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram of a semiconductor package according to an embodiment of the present application.

[0027] Figures 2A to 2I A schematic diagram of a dummy interposer according to other embodiments of the present application.

[0028] Figure 3 A schematic diagram of a semiconductor package according to another embodiment of the present application.

[0029] Symbol Explanation

[0030] 10, 20: semiconductor package

[0031] 100: substrate

[0032] 102, 102A-102L: interposer

[0033] 104, 104A-104C: chip

[0034] 106, 106A, 106B: dummy interposer

[0035] 108, 108A-108C, 112: connection terminal

[0036] 110, 110A-110D: dummy chip

[0037] BS: bottom surface

[0038] D1: direction

[0039] P: portion

[0040] TS: top surface DETAILED DESCRIPTION

[0041] Figure 1 A schematic diagram of a semiconductor package according to an embodiment of the present application. Figures 2A to 2I A schematic diagram of a dummy interposer according to other embodiments of the present application.

[0042] Reference will now be made to Figure 1 , the present application proposes a semiconductor package 10 including a substrate 100, a plurality of interposers 102, a plurality of chips 104, and a dummy interposer 106. The substrate 100 can be a package substrate. In some embodiments, the package substrate can include a substrate, a redistribution layer, a dielectric layer, and a via, but the present application is not limited thereto. The material of the substrate of the substrate 100 can be silicon (e.g., single crystal silicon or polycrystalline silicon), glass, organic material, ceramic, composite material, or a combination thereof. In addition, the semiconductor package 10 can further include a plurality of connection terminals 108. The connection terminals 108 can be bumps (e.g., tin balls), but the present application is not limited thereto.

[0043] Multiple interposers 102 are stacked on substrate 100. In some embodiments, interposers 102 may provide a fan-out function or a fan-in function. Interposers 102 may be used to carry chip 104. Two adjacent stacked interposers 102 (e.g., interposer 102A and interposer 102B) may be electrically connected to each other via connection terminals 108. In some embodiments, interposers 102 may include a substrate, a redistribution layer, a dielectric layer, and vias, but the invention is not limited thereto. The substrate of interposers 102 may be made of silicon (e.g., monocrystalline silicon or polycrystalline silicon), glass, organic materials, ceramics, composite materials, or combinations thereof. In some embodiments, interposers 102 may be interposers with redistribution layers on both sides (i.e., double-side routing interposers) or interposers with redistribution layers on one side (i.e., single-side routing interposers).

[0044] In some embodiments, such as Figure 1 As shown, the dimensions (e.g., top view area or width) of two adjacent stacked intermediate layers 102 may decrease or increase in the direction D1 away from the substrate 100. Figure 1 However, the present invention is not limited thereto. For example, the dimensions (e.g., top view area or width) of stacked and adjacent intermediate layers 102A and 102B may decrease in direction D1 away from the substrate 100. The dimensions (e.g., top view area or width) of stacked and adjacent intermediate layers 102C and 102D may increase in direction D1 away from the substrate 100. In other embodiments, the dimensions (e.g., top view area or width) of two adjacent stacked intermediate layers 102 may be the same as each other. Figure 3 ).

[0045] In some embodiments, such as Figure 1 As shown, the dimensions (e.g., radius or width) of two adjacent stacked connection terminals 108 may decrease or increase in the direction D1 away from the base 100, but the invention is not limited thereto. For example, the dimensions (e.g., radius or width) of stacked and adjacent connection terminals 108A and 108B may increase in the direction D1 away from the base 100. The dimensions (e.g., radius or width) of stacked and adjacent connection terminals 108B and 108C may decrease in the direction D1 away from the base 100. In other embodiments, the dimensions (e.g., radius or width) of two adjacent stacked connection terminals 108 may be the same as each other. Figure 3 ).

[0046] A plurality of chips 104 is located on a plurality of interposers 102. The chips 104 are electrically connected to the interposers 102. The chips 104 can be electrically connected to the corresponding interposers 102 via connection terminals (not shown), but the present application is not limited thereto. The connection terminals can be bumps (e.g., solder balls), but the present application is not limited thereto. The chips 104 can be functional chips such as power chips, radio frequency chips, graphics chips, memory chips, etc.

[0047] A virtual interposer 106 is located between the interposers 102 and the substrate 100 and is electrically connected to the interposers 102. In some embodiments, the virtual interposer 106 can provide fan-out or fan-in functionality. The virtual interposer 106 does not directly carry the chips 104, i.e., the chips 104 are not located between the virtual interposer 106 and the interposers 102. For example, the chips 104 are not located between the virtual interposer 106 and the interposer 102E. The chips 104 are not located between the virtual interposer 106 and the interposer 102F. The virtual interposer 106 can have support and electrical connection functions, thus making the design of the semiconductor package 10 flexible and helping to improve the package density. In addition, since the virtual interposer 106 can have support and electrical connection functions (e.g., to transmit signal flow, data flow, or power), the virtual interposer 106 can be placed anywhere in the semiconductor package 10 where support and electrical connection are needed, and the placement of the virtual interposer 106 is not limited. In the present embodiment, some of the virtual interposers 106 can be located between the interposer 102E and the substrate 100, some of the virtual interposers 106 can be located between the interposer 102F and the substrate 100, and some of the virtual interposers 106 can be located between the interposer 102F and the interposer 102G, but the present application is not limited thereto. Figure 1

[0048] In some embodiments, the virtual interposer 106 can include a substrate, a redistribution layer, a dielectric layer, and a via, but the present application is not limited thereto. The material of the substrate of the virtual interposer 106 can be silicon (e.g., single crystal silicon or polycrystalline silicon), glass, organic material, ceramic, composite material, or a combination thereof. In some embodiments, the virtual interposer 106 can be a virtual interposer with a redistribution layer on both sides (i.e., a double-sided redistribution virtual interposer) or a virtual interposer with a redistribution layer on one side (i.e., a single-sided redistribution virtual interposer).

[0049] In some embodiments, the virtual interposer 106 can be electrically connected to the chips 104 via the interposers 102. For example, the virtual interposer 106 can be electrically connected to the chip 104A located on the interposer 102E via the connection terminal 108 and the interposer 102E. The virtual interposer 106 can be electrically connected to the chip 104B located on the interposer 102F via the connection terminal 108 and the interposer 102F.

[0050] ​In this embodiment, the dummy interposer 106 can have a portion P extending in the direction Dl away from the substrate 100, but the present application is not limited thereto. In addition, the dummy interposer 106 can have a plurality of top surfaces TS with different heights, but the present application is not limited thereto. In addition, the dummy interposer 106 can have a plurality of bottom surfaces BS with different heights, but the present application is not limited thereto. On the other hand, the shape of the dummy interposer 106 is not limited to that shown in Figure 1 . The shape of the dummy interposer 106 can be adjusted according to the requirements of support and electrical connection. In other embodiments, the dummy interposer 106 can have a shape as shown in Figures 2A to 2I . As shown in Figure 2A , the dummy interposer 106 can have only one top surface TS and one bottom surface BS.

[0051] In addition, the semiconductor package 10 can further include a dummy chip 110. The dummy chip 110 can have support function and electrical connection function (e.g., for transmitting signal flow, data flow or power supply), thus making the design of the semiconductor package 10 more flexible and helping to further improve the packaging density. In this embodiment, the dummy chip 110 can have support function and electrical connection function, but no other functions. That is, the dummy chip 110 refers to a chip having support function and electrical connection function but no other functions. The dummy chip 110 is located between the interposer 102 and the substrate 100, and is electrically connected to the interposer 102. In this embodiment, the dummy chip 110 can be located on the interposer 102, but the present application is not limited thereto. The dummy chip 110 can be electrically connected to the corresponding interposer 102 via a connection terminal (not shown), but the present application is not limited thereto. The connection terminal can be a bump (e.g., a tin ball), but the present application is not limited thereto. In addition, the dummy chip 110 does not directly carry the chip 104, that is, the chip 104 is not located between the dummy chip 110 and the interposer 102 (e.g., the interposer 102B). In addition, since the dummy chip 110 has support function and electrical connection function, the dummy chip 110 can be arranged at any position in the semiconductor package 10 where support and electrical connection are required, and the arrangement of the dummy chip 110 is not limited Figure 1 . For example, the dummy chip 110 can be located between two adjacent interposers 102 (e.g., the interposer 102A and the interposer 102B) in the stack, but the present application is not limited thereto.

[0052] In some embodiments, the virtual chip 110 may include a substrate, a redistribution layer, a dielectric layer, and vias, but the invention is not limited thereto. The substrate of the virtual chip 110 may be made of silicon (e.g., monocrystalline silicon or polycrystalline silicon), glass, organic materials, ceramics, composite materials, or combinations thereof. In some embodiments, the virtual chip 110 may be a virtual chip with redistribution layers on both sides (i.e., a virtual chip with double-sided wiring) or a virtual chip with redistribution layers on one side (i.e., a virtual chip with single-sided wiring).

[0053] In some embodiments, the virtual chip 110 may be electrically connected to the chip 104 via the interposer 102. For example, the virtual chip 110 may be electrically connected to the chip 104C located on the interposer 102B via the connection terminal 108 and the interposer 102B.

[0054] In some embodiments, the interposer 102 may be electrically connected to the substrate 100. For example, the interposer 102 may be electrically connected to the substrate 100 via at least one of the following: connection terminal 108, other interposers 102, virtual interposer 106, and virtual chip 110. Figure 1 and Figure 3 In some embodiments, chip 104 may be electrically connected to substrate 100. For example, chip 104 may be electrically connected to substrate 100 via at least one of interposer 102, connection terminal 108, virtual interposer 106, and virtual chip 110. Figure 1 and Figure 3 The virtual interposer layer 106 can be electrically connected to the substrate 100. In this embodiment, as... Figure 1 As shown, the virtual interposer 106 can be electrically connected to the substrate 100 via the connection terminal 108, but the present invention is not limited thereto. In other embodiments, the virtual interposer 106 can be electrically connected to the substrate 100 via at least one of the interposer 102, the connection terminal 108, other virtual interposers 106, and the virtual chip 110. Figure 3 In this embodiment, as Figure 1 As shown, the virtual chip 110 can be electrically connected to the substrate 100 via the interposer 104 and the connection terminal 108, but the present invention is not limited thereto. In other embodiments, the virtual chip 110 can be electrically connected to the substrate 100 via the interposer 102, the connection terminal 108, the virtual interposer 106, and at least one of the other virtual chips 110. Figure 3 ).

[0055] Additionally, the semiconductor package 10 may further include a connection terminal 112. The connection terminal 112 is located at the bottom of the substrate 100, thereby enabling the substrate 100 to be electrically connected to other electronic components. The connection terminal 112 may be a bump (e.g., a solder ball), but the invention is not limited thereto.

[0056] In some embodiments, the semiconductor package 10 can include an encapsulant (not shown) to protect other components in the semiconductor package 10 according to product requirements. In other embodiments, the semiconductor package 10 can also not include an encapsulant.

[0057] Based on the above embodiments, it is known that in the semiconductor package 10, since the dummy interposer 106 has the support function and the electrical connection function, and the configuration manner and the shape of the dummy interposer 106 can be adjusted according to requirements, the design of the semiconductor package 10 can be more flexible, and the packaging density can be improved.

[0058] Figure 3 A schematic view of a semiconductor package according to another embodiment of the present application. Figure 3 With Figure 1 The same or similar components in the semiconductor package 20 are denoted by the same reference numerals, and the description thereof is omitted.

[0059] Please refer to Figure 3 In the semiconductor package 20, the dummy interposer 106 is located between the interposer 102 and the substrate 100, and is electrically connected to the interposer 102. For example, in the semiconductor package 20, the dummy interposer 106A can be located between two adjacent interposers 102 (for example, the interposer 102H and the interposer 102I) in the stack. The dummy interposer 106A can be located between another dummy interposer 106 (for example, the dummy interposer 106B) and the interposer 102I. The dummy interposer 106B is located between another dummy interposer 106 (for example, the dummy interposer 106A) and the substrate 100. The dummy interposer 106A is located between the dummy chip 110A and the interposer 102I.

[0060] In the semiconductor package 20, the dummy chip 110 is located between the interposer 102 and the substrate 100, and is electrically connected to the interposer 102. The dummy chip 110 can be located on the interposer 102 or the dummy interposer 106. For example, in the semiconductor package 20, the dummy chip 110B can be located between two adjacent interposers 102 (for example, the interposer 102J and the interposer 102K) in the stack. The dummy chip 110C can be located between the interposer 102L and the dummy interposer 106B. The dummy chip 110D can be located between two adjacent dummy interposers 106 (the dummy interposer 106A and the dummy interposer 106B) in the stack. The dummy chip 110 can be electrically connected to the corresponding interposer 102 or dummy interposer 106 via a connection terminal (not shown), but the present application is not limited thereto. The connection terminal can be a bump (for example, a solder ball), but the present application is not limited thereto.

[0061] In addition, in the semiconductor package 20, the size (e.g., radius or width) of the stacked two adjacent connection terminals 108 can be the same as each other. The size (e.g., upper view area or width) of the stacked two adjacent interposers 102 (e.g., the interposer 102J and the interposer 102K) can be the same as each other.

[0062] In addition, the shape of the virtual interposer 106 is not limited to Figure 3 . The shape of the virtual interposer 106 can be adjusted according to the requirements of support and electrical connection. For example, the virtual interposer 106B, the virtual chip 110C and the virtual chip 110D in Figure 3 may be replaced by the virtual interposer 106 as shown in Figure 2I .

[0063] Based on the above embodiments, in the semiconductor package 20, since the virtual interposer 106 has the functions of support and electrical connection, and the configuration manner and shape of the virtual interposer 106 can be adjusted according to the requirements, the design of the semiconductor package 20 can be more flexible, and the packaging density can be improved.

[0064] In summary, since the semiconductor package of the above embodiments has the virtual interposer, and the virtual interposer has the functions of support and electrical connection, the design flexibility and packaging density of the semiconductor package can be improved.

[0065] Although the present application is disclosed in connection with the above embodiments, it is not intended to limit the present application, and anyone skilled in the art with ordinary knowledge can make some changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be defined by the appended claims.

Claims

1. A semiconductor package, comprising: a substrate; a plurality of interposers stacked on the substrate; a plurality of chips on the plurality of interposers, wherein the chips are electrically connected to the interposers; and a dummy interposer between the interposers and the substrate and electrically connected to the interposers, wherein the chips are not between the dummy interposer and the interposers, and the dummy interposer has a first portion and a second portion extending from the first portion in a direction away from the substrate, and the dummy interposer has a meandering shape at a junction of the first portion and the second portion.

2. The semiconductor package of claim 1, wherein the interposers are electrically connected to the substrate.

3. The semiconductor package of claim 1, wherein the chips are electrically connected to the substrate.

4. The semiconductor package of claim 1, wherein the dummy interposer is electrically connected to the substrate.

5. The semiconductor package of claim 1, wherein the dummy interposer is electrically connected to the chips via the interposers.

6. The semiconductor package of claim 1, wherein the dummy interposer has a plurality of upper surfaces of different heights.

7. The semiconductor package of claim 1, wherein the dummy interposer has a plurality of lower surfaces of different heights.

8. The semiconductor package of claim 1, wherein the dummy interposer is between two adjacent interposers of the stack.

9. The semiconductor package of claim 1, wherein the dummy interposer is between another dummy interposer and the interposers.

10. The semiconductor package of claim 1, wherein the dummy interposer is between another dummy interposer and the substrate.

11. The semiconductor package of claim 1, wherein a size of two adjacent interposers of the stack decreases in a direction away from the substrate.

12. The semiconductor package of claim 1, wherein a size of two adjacent interposers of the stack increases in a direction away from the substrate.

13. The semiconductor package of claim 1, further comprising: a dummy chip between the interposers and the substrate and electrically connected to the interposers.

14. The semiconductor package of claim 13, wherein the chips are not between the dummy chip and the interposers.

15. The semiconductor package of claim 13, wherein the dummy chip is between two adjacent interposers of the stack.

16. The semiconductor package of claim 13, wherein the dummy chip is between the interposers and the dummy interposer.

17. The semiconductor package of claim 13, wherein the dummy chip is between two adjacent dummy interposers of the stack.

18. The semiconductor package of claim 13, wherein the dummy chip is electrically connected to the chips via the interposers.

19. The semiconductor package of claim 13, wherein the dummy interposer is between the dummy chip and the interposers. ​

Images