Semiconductor package with integrated and shielded transformer

Abstract

Integrated circuit (IC) packages have a ferrite-dielectric shield layer between planar transformer coils and semiconductor chips. The shield layer blocks electromagnetic interference (EMI) generated by current in the transformer coils from reaching the semiconductor chips. Multi-layer planar transformer coils that are primary or secondary coils can be connected in series or parallel using center posts and coil extensions (from the outer coil winding to the lead frame post) that are connected together, with the lead frame posts also having external package connectors such as pins or solder balls. The center winding of the upper transformer coil is connected to the semiconductor chip on the chip mount pad through a center post that passes through an opening in the shield layer above the center hole of the transformer coil. Wire bonds connect pads on the semiconductor chip to lead frame pads on the lead frame posts, with the ends of the lead frame posts being the external package connectors.

Description

TECHNICAL FIELD

[0001] The present invention relates to semiconductor-transformer packaging, and more particularly to a package that shields a semiconductor chip from an integrated transformer. BACKGROUND

[0002] Semiconductor chips are widely used and are typically packaged in a lead-frame plastic package. Bonding wires are placed between bonding pads on the semiconductor chip and bonding pads on the lead-frame. The lead-frame and chip are then encapsulated in plastic, covering and protecting the bonding wires as well as the chip and lead-frame. The ends of the lead-frame protrude from the plastic, forming pins. An electrical path is formed from the pins, through the lead-frame to the bonding pads on the lead-frame, through the bonding wires to the bonding pads on the chip.

[0003] While transistors, resistors, and capacitors can be easily integrated into a semiconductor chip using techniques such as complementary metal-oxide semiconductor (CMOS) processes, transformers cannot be integrated because the inductance is too small or the area is too large.

[0004] So external transformers are typically used. A metal core transformer is typically formed by wrapping a metal wire around a metal core multiple times. An air core transformer has lower inductance than a metal core transformer, but is easier to manufacture. An air core transformer can be formed from a small, flat spiral coil. Such planar air core transformers have low energy losses and are useful for high frequency switching, but the inductance is too low for some applications, such as power converters.

[0005] Such planar air core transformers can be physically integrated with a semiconductor chip, perhaps in a single package. However, the electromagnetic field generated by the transformer coil can induce currents in nearby metal conductors. When the transformer is placed near a semiconductor chip, the electromagnetic field can induce unwanted currents in the metal traces of the semiconductor chip. These unwanted currents can interfere with the desired signals and cause the semiconductor chip to not function properly. For higher inductances and coil currents, and for close proximity to the chip, the induced currents in the chip can even damage the chip. Thus, this electromagnetic interference (EMI) generated by the coil can prevent integration with the chip in a semiconductor package.

[0006] The package can be made larger so that the semiconductor chip and the transformer are spaced far enough apart that the EMI does not harm the semiconductor chip. However, this spacing can be several times the size of the transformer or the chip. The package has to be much larger than desired.

[0007] Multi-chip modules can have integrated transformers, but these modules are many times larger than single-chip packages. Such large modules are expensive and take up too much area on the printed circuit board (PCB) on which they are mounted. Certain applications, such as the Internet-of-Things (IoT), are limited in area and cost and cannot use large packages.

[0008] It would be desirable to have a semiconductor package that contains both a semiconductor chip and a transformer. It would be desirable to shield the semiconductor chip from electromagnetic interference generated by the coil. It would also be desirable to increase the inductance of the coil. It would be desirable to add a structure to the semiconductor package that both protects the chip from EMI and increases the inductance of the transformer. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a simplified cross-sectional view of a shielded transformer semiconductor package.

[0010] Figure 2A , 2B , 2C is a cross-sectional electromagnetic field intensity plot of the shielded transformer semiconductor package of Figure 1

[0011] Figure 3 is a three-dimensional view of a shielded transformer semiconductor package.

[0012] Figure 4 is a three-dimensional view of the shielded transformer semiconductor package of

[0013] Figure 5 is a three-dimensional view of a shielded transformer semiconductor package with the upper ferrite-dielectric shield layer and the middle dielectric layer transparent to show the upper transformer coil and the lower transformer coil.

[0014] Figure 6 is a top view of the shielded transformer semiconductor package of Figures 3-5

[0015] is a top view of the shielded transformer semiconductor package of Figure 7 Figures 3-5 is a top view of the shielded transformer semiconductor package of

[0016] Figure 8 Figures 3-5 is a top view of the shielded transformer semiconductor package of

[0017] Figure 9 is a top view of the shielded transformer semiconductor package of Figures 3-5 ​​​is a top view of a shielded transformer semiconductor package with some layers removed to show the lower transformer coil.

[0018] Figure 10 is a cross-sectional view of a shielded transformer semiconductor package mounted to a PCB using surface mount solder balls.

[0019] Figure 11 is another flip chip shielded transformer semiconductor package with solder balls.

[0020] Figure 12 shows Figure 11 the bottom of the flip chip shielded transformer semiconductor package with solder balls of

[0021] Figure 13 is a cross-sectional view of another shielded transformer semiconductor package with two coils.

[0022] Figure 14 is a cross-sectional view of another shielded transformer semiconductor package with four coils.

[0023] Figure 15 is a cross-sectional view of yet another shielded transformer semiconductor package with four coils.

[0024] Figure 16 is a three-dimensional view of a four coil shielded transformer semiconductor package. DETAILED DESCRIPTION

[0025] The present invention relates to improvements in semiconductor-transformer packages. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein can be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments described and shown, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

[0026] Figure 1 is a simplified cross-sectional view of a shielded transformer semiconductor package. Semiconductor chip 30 and transformer coils 10, 11 are integrated together in a package (not shown). Transformer coil 10 has a core 14 in its center and is spiral-shaped perpendicular to Figure 1 the plane. Although this cross-section shows a broken transformer coil 10, transformer coil 10 is actually a continuous coil perpendicular to Figure 1 the plane.

[0027] The upper transformer coil 10 can be the primary winding of a transformer, and the lower transformer coil 11 can be the secondary winding of the transformer, where the current flowing through the primary transformer coil 10 generates a magnetic field that induces a current in the secondary transformer coil 11. The transformer coils 10, 11 are separated from each other by a dielectric layer 21.

[0028] An upper ferrite-dielectric shield 24 shields the top of the transformer coil 10, and a lower ferrite-dielectric shield 26 shields the bottom of the transformer coil 11. The hollow core 14 in the center of the transformer coil 10 is aligned with the hollow core 15 in the center of the transformer coil 11. The semiconductor chip 30 can be placed above the upper ferrite-dielectric shield 24 or below the lower ferrite-dielectric shield 26.

[0029] When a primary current flows through the transformer coil 10, an electromagnetic field is generated, which can cause electromagnetic interference (EMI) in the semiconductor chip 30. However, the upper ferrite-dielectric shield 24 is placed above the transformer coil 10, between the transformer coil 10 and the semiconductor chip 30. The upper ferrite-dielectric shield 24 contains a ferrite layer 12, which is sandwiched between dielectric layers 20 on its top and bottom.

[0030] The ferrite layer 12 is a ceramic layer containing magnetized iron or ferrite metal particles, such as manganese zinc ferrite (MnZn, molecular formula Mn a Zn (1-a) Fe2O4), or nickel zinc ferrite (NiZn, molecular formula Ni a Zn (1-a) Fe2O4). The dielectric layer 20 can be a plastic laminate or other insulator, such as FR4 or PI, which is a NEMA grade glass-reinforced epoxy laminate material. FR-4 is a composite material composed of woven fiberglass cloth and an epoxy resin binder, with flame retardancy (self-extinguishing). PI is a polyimide, which is a polymer of imide monomers belonging to the class of high-performance plastics. A classic polyimide is Kapton, which is condensed from pyromellitic dianhydride and 4,4'-oxydianiline. The upper ferrite-dielectric shield 24 can be made of a sheet of ferrite layer 12, covered with dielectric layers 20 on its top and bottom, which can be cut to size as needed.

[0031] A second shield is provided by the lower ferrite-dielectric shield layer 26 to prevent the electromagnetic field from escaping from the bottom of the transformer coil 10, 11 and possibly bypassing the edges of the upper ferrite-dielectric shield layer 24 to reach the semiconductor chip 30. Since the transformer coil 10, 11 is sandwiched between the upper ferrite-dielectric shield layer 24 and the lower ferrite-dielectric shield layer 26, the electromagnetic field generated by the transformer coil 10 is confined to a small region between the ferrite layer 12 in the upper ferrite-dielectric shield layer 24 and the ferrite layer 12 in the lower ferrite-dielectric shield layer 26.

[0032] This confinement of the electromagnetic field by the ferrite layer 12 also increases the inductance of the transformer coil 10, 11. Even though the transformer coil 10 is an air-core transformer, since the center of the transformer coil 10 is the air core 14, the presence of the ferrite layer 12 above and below the plane of the transformer coil 10 also increases its inductance.

[0033] The upper ferrite-dielectric shield layer 24 can be in contact with the top of the transformer coil 10, since the dielectric layer 20 prevents an electrical short between the transformer coil 10 and the ferrite layer 12. Thus, the ferrite layer 12 can be placed very close to the transformer coil 10. The thickness of the dielectric layer 20 can be only 0.1 mm, and thus the electromagnetic field can be very tightly confined. This close spacing and confinement of the electromagnetic field can further enhance the inductance of the transformer coil 10, 11. Although an air-core transformer, the transformer coil 10, 11 surrounded by the ferrite-dielectric shield layers 24, 26 can have an appreciable inductance value, close to that of a magnetic-core transformer.

[0034] Figure 2A 、 2B , 2C shows a plot of the electromagnetic field intensity on a cross-section of the shielded transformer semiconductor package of Figure 1 . When an alternating current passes through the transformer coil 10, a time-varying electromagnetic field is generated, inducing a current in the secondary transformer coil 11. When the ferrite layer 12 is not present, as shown in Figure 2A , the intensity of the electromagnetic field is shown by the curve 104 in Figure 2C .

[0035] Figure 2B The presence of the ferrite layer 12 in Figure 2C causes the electromagnetic field to be concentrated within the ferrite layer 12 and to drop off rapidly within the dielectric layer 20 surrounding each ferrite layer 12.

[0036] Although the electromagnetic field spikes within the ferrite layer 12 are large, as shown by curve 102, these spikes provide a lower electromagnetic field strength outside the dielectric layer 20, such as near the surface of the semiconductor chip 30. Thus, EMI at the semiconductor chip 30 is reduced due to the presence of the ferrite layer 12.

[0037] The ferrite layer 12 reduces the electromagnetic field seen by the semiconductor chip 30 by a factor of approximately 2,000.

[0038] Figure 3 Figure 1 is a three-dimensional view of a shielded transformer semiconductor package. The semiconductor chip 30 is attached to the die attach pad 34, such as by epoxy or other bonding. Wire bonds 42 run between pads on the semiconductor chip 30 and the lead frame pads 40. Some wire bonds run from pads on the semiconductor chip 30 to the die attach pad 34. There is an opening in the upper ferrite-dielectric shield layer 24 above the air core 14 to allow the center post 36 to pass through.

[0039] The lead frame pads 40, 50, 52, 54 are at the top of the lead frame posts 46, 45, 55, which connect to the package pins that protrude from the bottom of the package and can fit into holes in a PCB when soldered to the PCB of a larger system. The lead frame posts 46, 45, 55 can be bent or connected to other parts of the lead frame (not shown) that lead to external package pins, solder balls, or other external connectors (not shown).

[0040] The lead frame posts 46, 45, 55 form a rectangle that surrounds the semiconductor chip 30, the die attach pad 34, and the transformer coils 10, 11, which are mostly hidden by the upper ferrite-dielectric shield layer 24. The top of the transformer coil 10 is covered by the upper ferrite-dielectric shield layer 24, while the bottom of the transformer coil 11 is covered by the lower ferrite-dielectric shield layer 26. Depending on the inductance value desired, the area of the transformer coil 10 can be larger than the area of the die attach pad 34 and the semiconductor chip 30.

[0041] Figure 4 Figure 2 is a three-dimensional view of a shielded transformer semiconductor package with the upper ferrite-dielectric shield layer removed to show the transformer coils. In this view, the upper ferrite-dielectric shield layer 24 has been removed. The transformer coil 10 is a planar coil that is wound outward from a center post 36 in the center of the coil, which electrically connects the die attach pad 34 to the center winding of the transformer coil 10. The outermost winding of the transformer coil 10 is connected to the lead frame post 46 under the lead frame pad 52 by a coil extension 58. Figure 4 ​

[0042] The transformer coils 10, 11 are separated from each other by a dielectric layer 21. The lower transformer coil 11 is a planar coil that is wound outward from a lower center post 56 in the center of the lower transformer coil 11 that extends outward below the lower transformer coil 11 to a lead frame post 55 that is electrically connected to a lead frame pad 54. The outermost winding of the lower transformer coil 11 is connected to a lead frame post 45 under the lead frame pad 50 by a coil extension wire 48.

[0043] Most of the pads on the semiconductor chip 30 are electrically connected to the package pins at the ends of the lead frame posts 45, 46, 55 by wire bonds 42 and lead frame pads 40, 50, 52, 54. However, several pads of the semiconductor chip 30 are electrically connected to the upper surface of the chip mount pad 34 by wire bonds. Electrical connections are then made from the upper surface of the chip mount pad 34 to the lower surface of the chip mount pad 34 to the center post 36. The chip mount pad 34 can be a conductive or metallic trace, a hole or via in the chip mount pad 34 can make the electrical connection from the semiconductor chip 30 to the center post 36. Thus, an electrical connection is made from the semiconductor chip 30 to the center winding of the transformer coil 10.

[0044] The outer winding of the transformer coil 10 is connected to the lead frame outer post 46 by a coil extension wire 58, the lead frame outer post 46 has a lead frame pad 52 at the top and is connected to an external package pin at the bottom. The lead frame pad 52 does not receive a wire bond 42 from the semiconductor chip 30.

[0045] The outer winding of the lower transformer coil 11 is connected to the lead frame outer post 45 by a coil extension wire 48, the lead frame outer post 45 has a lead frame pad 50 at the top and is connected to an external package pin at the bottom. The lead frame pad 50 does not receive a wire bond 42 from the semiconductor chip 30.

[0046] Thus, the transformer coil 10 provides a series inductance between several pads of the semiconductor chip 30 and an external package pin. When a varying current is passed through the upper transformer coil 10, the resulting electromagnetic field is shielded by the upper ferrite-dielectric shield layer 24( Figure 3 ) from causing EMI in the semiconductor chip 30. This electromagnetic field generated by the upper transformer coil 10 as the primary coil induces a current in the lower transformer coil 11 as the secondary coil of the transformer.

[0047] Figure 5 is a three-dimensional view of a shielded transformer semiconductor package where the upper ferrite-dielectric shield layer and the intermediate dielectric layer are made transparent to better show the upper and lower transformer coils. In Figure 5 the upper ferrite-dielectric shield layer 24 and the intermediate dielectric layer 21 are made transparent to better show the lower transformer coil 11.

[0048] When a changing current flows through the upper transformer coil 10, the electromagnetic field generated by the upper transformer coil 10, which is the primary coil, induces a current in the lower transformer coil 11, which is the secondary coil of the transformer.

[0049] The lower transformer coil 11 is a planar coil wound outward from its center post 56, which extends outward below the lower transformer coil 11 to the lead frame post 55, which is electrically connected to the lead frame pad 54. The outermost winding of the lower transformer coil 11 is connected to the lead frame post 45 below the lead frame pad 50 via a coil extension line 48. Induced secondary current flows between the lead frame pads 50 and 54.

[0050] Figure 6 yes Figures 3-5 A top view of a shielded transformer semiconductor package. A semiconductor chip 30 is attached to the top of a chip mounting pad 34 and electrically connected to a leadframe pad 40 via bonding wires 42. In this top view, the leadframe posts 46 are concealed by the leadframe pads 40.

[0051] Most of the transformer coils 10 and 11 are shielded and hidden by an upper ferrite-dielectric shielding layer 24 located between the chip mounting pad 34 and the upper transformer coil 10, providing EMI shielding for the semiconductor chip 30. However, a portion of the outer winding of the transformer coil 10 is visible. The end of the outer winding of the transformer coil 10 is connected to the outer post 46 of the lead frame (not shown) via a coil extension wire 58, and then to the lead frame pad 52. The inner winding of the transformer coil 10 is connected to the underside of the chip mounting pad 34, and then to the semiconductor chip 30 via a bonding wire 43.

[0052] Furthermore, a portion of the outer winding of the lower transformer coil 11 is visible. The end of the outer winding of the lower transformer coil 11 is connected via a coil extension 48 to an outer post 45 (not shown) of the lead frame, and then to a lead frame pad 50. Below the semiconductor chip 30, the inner winding of the lower transformer coil 11 is connected to a lower center post 56. The lower center post 56 extends outward from the center below the lower transformer coil 11, reaching a lead frame post 55 (not shown), which is electrically connected to the lead frame pad 54. Figure 6 In the middle, near the lead frame pad 54, a small portion of the lower center post 56 is visible.

[0053] Figure 7 yes Figures 3-5A top view of a shielded transformer semiconductor package, with the upper ferrite-dielectric shield removed to reveal the transformer coils. The upper transformer coil 10 is wound outward from its center to its outermost winding, which is hidden by the semiconductor chip 30 and chip mount pads 34. The ends of the outer windings of the transformer coil 10 are connected to the lead frame outer post 46 (not shown) via coil extension lines 58, and then to the lead frame pads 52.

[0054] The lower transformer coil 11 is wound outwards from its center to its outermost winding, which is concealed by the semiconductor chip 30 and chip mounting pads 34. The end of the outer winding of the lower transformer coil 11 is connected via a coil extension wire 48 to an outer lead frame post 45 (not shown), and then to lead frame pads 50. The inner winding of the lower transformer coil 11 is connected to a lower center post 56, which is concealed beneath the semiconductor chip 30. The lower center post 56 extends outwards from the center beneath the lower transformer coil 11 to the lead frame post 55 (not shown), where it is electrically connected to the lead frame pads 54. Figure 7 In the middle, near the lead frame pad 54, a large portion of the lower center post 56 is visible.

[0055] Figure 8 yes Figures 3-5 A top view of a shielded transformer semiconductor package, with some layers removed to reveal the upper transformer coil. The upper transformer coil 10 is wound outwards from its center to its outermost winding, which is hidden by the semiconductor chip 30 and chip mount pads 34. The end of the outer winding of the transformer coil 10 is connected to the lead frame outer post 46 (not shown) via coil extension wires 58, and then to the lead frame pads 52. Figure 8 In the middle section, the lower transformer coil 11 has been removed.

[0056] Figure 9 yes Figures 3-5 A top view of a shielded transformer semiconductor package, where some layers have been removed to reveal the underlying transformer coils. Figure 9 In the middle, the upper transformer coil 10 has been removed.

[0057] The lower transformer coil 11 is wound outwards from its center to its outermost winding, which is concealed by the semiconductor chip 30 and chip mounting pads 34. The end of the outer winding of the lower transformer coil 11 is connected via a coil extension wire 48 to an outer lead frame post 45 (not shown), and then to lead frame pads 50. The inner winding of the lower transformer coil 11 is connected to a lower center post 56, which is concealed beneath the semiconductor chip 30. The lower center post 56 extends outwards from the center beneath the lower transformer coil 11 to the lead frame post 55 (not shown), where it is electrically connected to the lead frame pads 54. Figure 9In this view, almost all of the shielded transformer semiconductor package is visible except for the entry portion of the lower center post 56. Note that the lower center post 56 is located in a plane lower than the plane of the lower transformer coil 11, so the intersection shown in the figure is not an electrical connection between the lower transformer coil 11 and the lower center post 56.

[0058] Figure 10 is a cross-sectional view of a shielded transformer semiconductor package mounted to a PCB using surface mount solder balls. The upper transformer coil 10 is sandwiched between the upper ferrite-dielectric shield layer 24 and the dielectric layer 21, while the lower transformer coil 11 is sandwiched between the dielectric layer 21 and the lower ferrite-dielectric shield layer 26. These layers form a flexible laminate.

[0059] The coils within the transformer coil 10 can move up or down relative to its plane because the transformer coil 10 is not a continuous sheet of metal but rather a coil that forms a metal winding. Likewise, the coils within the lower transformer coil 11 can move up or down relative to its plane because the lower transformer coil 11 is not a continuous sheet of metal but rather a coil that forms a metal winding.

[0060] The upper ferrite-dielectric shield layer 24 and the lower ferrite-dielectric shield layer 26 each contain a ferrite layer 12 that is sandwiched by a dielectric layer 20. The dielectric layer 20 prevents the ferrite layer 12 from shorting to the transformer coils 10, 11. Figure 10 The maximum bend or curvature of the transformer coils 10, 11 is shown.

[0061] The semiconductor chip 30 on the chip mount pad 34 is connected by wire bonds 42 to the lead frame pads 40 at the top of the lead frame posts 46. In this embodiment, the top of the lead frame posts 46 can be used as the lead frame pads 40. The semiconductor chip 30 is mounted on the chip mount pad 34, which is above the top of the upper ferrite-dielectric shield layer 24. The ferrite layer 12 blocks the magnetic flux generated by the transformer coils 10, 11 from reaching the semiconductor chip 30 and causing EMI.

[0062] The bottom of the lead frame posts 46 are connected with solder balls 60, which can be solder balls that form a solder joint with surface mount pads on a PCB 62 when heated. A plastic encapsulant (not shown) can encapsulate the semiconductor chip 30 and protect the wire bonds 42.

[0063] Figure 11 is another flip chip shielded transformer semiconductor package with solder balls. The semiconductor chip 30 is a surface mount chip that is flipped over and connected to the top of the package substrate 35 by solder balls 62. The patterned metal traces on the package substrate 35 connect the chip solder balls 62 to larger external solder balls 60 that connect the shielded transformer semiconductor package to a system PCB.

[0064] The upper transformer coil 10 and the lower transformer coil 11 are separated by a dielectric layer 21. The upper ferrite-dielectric shield 24 shields the top of the transformer coil 10, while the lower ferrite-dielectric shield 26 shields the bottom of the transformer coil 11. The center air core of the upper transformer coil 10 is aligned with the center air core of the lower transformer coil 11. Coil posts 16 connect the outer windings of the upper transformer coil 10 to the package substrate 35, and then to the solder balls 60 or to the semiconductor chip 30. Solder wires 65 can be added to connect one of the chip solder balls 62 on the semiconductor chip 30 to the solder balls 60 that are connected to the coil posts 16 at the outer ends of the transformer coil 10.

[0065] The center winding of the lower transformer coil 11 is connected to the lower center post 56, and then to a solder wire 66, and then to a solder ball 64 on the package substrate 35. The outer windings of the lower transformer coil 11 can be connected in a similar manner to another solder ball 65 on the package substrate 35 with another solder wire 67.

[0066] Figure 12 The bottom of the flip-chip shielded transformer semiconductor package with solder balls is shown. Figure 11 In this bottom view, the lower transformer coil 11 is visible, with the lower center post 56 connected to the center winding of the lower transformer coil 11. The solder wire 66 connects from the outer end of the lower center post 56 to the package substrate 35, and then to the solder ball 64.

[0067] The semiconductor chip 30 is a surface mount chip that is flipped over and connected to the top of the package substrate 35 by the solder balls 62. The patterned metal traces on the package substrate 35 connect the chip solder balls 62 to the larger external solder balls 60 that connect the shielded transformer semiconductor package to the system PCB.

[0068] The coil posts 16 connect the outer windings of the upper transformer coil 10 to the package substrate 35, and then the traces on the package substrate 35 can connect to the solder balls 60 or to the semiconductor chip 30. Solder wires 65 can be added to connect one of the chip solder balls 62 on the semiconductor chip 30 to the solder balls 60 that are connected to the coil posts 16 at the outer ends of the transformer coil 10.

[0069] Figure 13is a cross-sectional view of another shielded transformer semiconductor package with two coils. The two transformer coils 10, 11 are separated by a dielectric layer 21. In this variant, the air core 14 and the air core 15 are connected together by a larger hole that extends through the ferrite layer 12 and the dielectric layers 20, 21. Although there is an opening in the ferrite layer 12 through which magnetic flux can leak and cause EMI in the semiconductor die 30, the opening is still relatively small and is in the middle of the coils so the leakage is small. The larger hole provides more room for the connection of the coils 10, 11. The central opening allows the center post 36 to pass through the ferrite layer 12 and the dielectric layer 20 between the semiconductor die 30 and the transformer coil 10.

[0070] Figure 14 is a cross-sectional view of another shielded transformer semiconductor package with four coils. The upper transformer coils 10, 10' have fewer windings than the lower transformer coils 11, 11'. When a primary current is applied to the upper transformer coils 10, 10', a voltage is induced in the lower transformer coils 11, 11' as secondary coils by mutual inductance.

[0071] The upper transformer coils 10, 10' can be connected in series, the center of the upper transformer coil 10 connected to the semiconductor die 30 by the center post 36, the outer winding of the upper transformer coil 10 connected to the inner winding of the upper transformer coil 10' by, for example, an additional post similar to the lower center post 56. Then, the outer winding of the upper transformer coil 10' is connected to the lead frame pad 52 by the coil extension 58 and the lead frame post 46.

[0072] Alternatively, the upper transformer coils 10, 10' can be connected in parallel, the centers of both upper transformer coils 10, 10' connected to the semiconductor die 30 by the center post 36, and the outer windings of both upper transformer coils 10, 10' connected to the lead frame pad 52 by the coil extension 58 and the lead frame post 46.

[0073] Series connection of the coils provides more windings and inductance, but higher coil resistance. Parallel connection of the coils provides fewer windings and less inductance, but lower coil resistance.

[0074] Similarly, the lower transformer coils 11, 11' can be connected in series, the center of the lower transformer coil 11 connected to the lead frame pad 54 by the lower center post 56 and the lead frame post 55, the outer winding of the lower transformer coil 11 connected to the inner winding of the lower transformer coil 11' by, for example, an additional post similar to the lower center post 56. Then, the outer winding of the lower transformer coil 11' is connected to the lead frame pad 50 by the coil extension 48 and the lead frame post 45. The induced secondary current flows between the lead frame pads 50, 54.

[0075] Alternatively, the lower transformer windings 11, 11' can be connected in parallel, the centers of the two lower transformer windings 11, 11' being connected to the leadframe pads 54 by the lower center post 56 and the leadframe post 55. The outer windings of the two lower transformer windings 11, 11' are connected to the leadframe pads 50 by the coil extension 48 and the leadframe post 45. The induced secondary current flows between the leadframe pads 50, 54.

[0076] The voltage change from primary to secondary depends, among other things, on the ratio of the number of turns in series of the upper transformer windings 10, 10' to the number of turns in series of the lower transformer windings 11, 11'. By varying the number of turns per layer of planar windings and the number of layers of planar windings, different voltage ratios can be achieved.

[0077] The upper transformer windings 10 and the lower transformer windings 11 are paired, separated by a dielectric layer 21, but their mutual inductance is increased by the upper ferrite-dielectric shield layer 24 and the intermediate ferrite-dielectric shield layer 28. Likewise, the upper transformer windings 10' and the lower transformer windings 11' are paired, separated by another dielectric layer 21, and their mutual inductance is increased by the lower ferrite-dielectric shield layer 26 and the intermediate ferrite-dielectric shield layer 28 surrounding the pair of windings. The intermediate ferrite-dielectric shield layer 28 contains a ferrite layer 13, which is surrounded by two dielectric layers 21.

[0078] The hollow cores 14, 14' and the hollow cores 15, 15' are aligned and can be connected together by a larger hole (not shown, see Figure 13 ) that extends through the ferrite layers 12, 13 and the dielectric layers 20, 21. This central opening allows the center post 36 and the lower center post 56 to pass through the ferrite layers 12, 13 and the dielectric layers 20, 21.

[0079] Figure 15 is a cross-sectional view of another shielded transformer semiconductor package with four windings. The upper transformer windings 10, 10' have fewer windings or turns than the lower transformer windings 11, 11'. When a primary current is applied to the upper transformer windings 10, 10', a voltage is induced in the lower transformer windings 11, 11' as secondary windings by mutual inductance.

[0080] The upper transformer windings 10, 10' can be connected in series or in parallel, and the lower transformer windings 11, 11' likewise can be connected in series or in parallel, as described previously for Figure 14 .

[0081] In this variant, the intermediate ferrite-dielectric shield layer 28 is replaced by a dielectric layer 21, so there is no ferrite shield layer between the windings. Instead, a dielectric layer 21 is located between each pair of adjacent windings.

[0082] In addition, the upper transformer windings 10, 10' are stacked together, while the lower transformer windings 11, 11' are stacked separately from the upper transformer windings 10, 10'. Because there is no intervening ferrite layer 13, the mutual inductance between all four windings 10, 10', 11, 11' is high. The ferrite layers 12 in the upper ferrite-dielectric shield 24 and the lower ferrite-dielectric shield 26 serve to concentrate the magnetic flux between the upper ferrite-dielectric shield 24 and the lower ferrite-dielectric shield 26, increasing the mutual inductance of any windings located therebetween.

[0083] Figure 16 is a three-dimensional view of a four-winding shielded transformer semiconductor package. In this embodiment, as in the previous embodiment, there are four layers of windings, namely upper transformer windings 10, 10' and lower transformer windings 11, 11', which are stacked in order. A dielectric layer 21 separates each winding layer from its adjacent winding layer. Only one dielectric layer 21 is shown, between the upper transformer winding 10' and the lower transformer winding 11, but there is another dielectric layer 21 (not shown) between the upper transformer windings 10, 10' and between the lower transformer windings 11, 11'. Figure 15

[0084] The spacing between the transformer windings 10, 10', 11, 11' is exaggerated in Figure 16 for better viewing, but in practice the spacing between them would be much closer, as shown in the cross-section of Figure 15 . Thus, even with four layers of transformer windings 10, 10', 11, 11', a relatively flat, thin package is obtained.

[0085] The semiconductor chip 30 is attached to the chip-mounting pad 34, for example by epoxy or other bonding. Wire bonds 42 are routed between pads on the semiconductor chip 30 and the leadframe pads 40, 53. Some wire bonds are routed from pads on the semiconductor chip 30 to the chip-mounting pad 34.

[0086] The leadframe pads 40, 50, 52, 53, 54 are at the tops of leadframe posts 45, 46, 55, which are connected to package leads that protrude from the bottom of the package and can be seated in holes in a PCB when the package is soldered to the PCB of a larger system. The leadframe posts 45, 46, 55 can be bent or connected to other parts of the leadframe (not shown) that lead to external package leads, solder balls, or other external connectors (not shown).

[0087] ​The leadframe posts 45, 46, 55 form a rectangle around the semiconductor chip 30, the chip mount pad 34, and the transformer coils 10, 10', 11, 11'. The transformer coil 10 is covered by the upper ferrite-dielectric shield 24. The lower ferrite-dielectric shield 26 is attached to the bottom of the lower transformer coil 11'.

[0088] The bottom of the chip mount pad 34 is connected to the center post 36, which passes through a central opening of the upper ferrite-dielectric shield 24 near the air core 14. This opening of the upper ferrite-dielectric shield 24 allows the center post 36 to connect the chip mount pad 34 to the center winding of the transformer coil 10. When the transformer coils 10, 10' are electrically connected in parallel, the center post 36 can be extended downward and connected to the center winding of the upper transformer coil 10, 10'.

[0089] The upper transformer coils 10, 10' are connected in series, the center of the upper transformer coil 10 is connected to the semiconductor chip 30 through the center post 36, the outer winding of the upper transformer coil 10 is connected to the inner winding of the upper transformer coil 10' through coil extension wires to the leadframe posts, to the leadframe pads 52, and from the leadframe posts 52 to the center winding of the upper transformer coil 10' through an additional post (not visible) similar to the lower center post 56. The outer winding of the upper transformer coil 10' is connected to the leadframe pad 53 through coil extension wires and the leadframe post 46.

[0090] The lower transformer coils 11, 11' are connected in parallel, the centers of both lower transformer coils 11, 11' are connected to the leadframe pad 54 through the lower center post 56 and the leadframe post 55. The outer windings of both lower transformer coils 11, 11' are connected to the leadframe pad 50 through coil extension wires 48 and the leadframe post 45. The induced secondary current flows between the leadframe pads 50, 54.

[0091] The leadframe pads 50, 52, 54 do not receive wire bonds 42 from the semiconductor chip 30, but are connected to the transformer coils 10, 11, 11' through coil extension wires 48 or other coil extension wires. The leadframe pads 50, 52, 54 have no function other than to preserve the symmetry of the package and can be deleted.

[0092] Thus, the upper transformer coils 10, 10' provide a mutual inductance of a primary current from the semiconductor chip 30 and external package pins to the lower transformer coils 11, 11'. When a varying current flows through the transformer coils 10, 10', 11, 11', the resulting electromagnetic field is shielded by the upper ferrite-dielectric shield 24 from causing EMI in the semiconductor chip 30.

[0093] Alternative Embodiments

[0094] The inventors have supplemented several other embodiments. For example, the semiconductor chip can be a silicon chip, such as a standard CMOS chip, or silicon on another substrate, or another material, such as GaAs. There can be more than one semiconductor chip 30 and more than one transformer. Other packaging techniques can be used instead, using a lead frame or similar, or being leadless.

[0095] The semiconductor chip 30 is an integrated circuit (IC) or a discrete element, such as a MOSFET, and can be of various types, such as complementary metal-oxide-semiconductor (CMOS) or BiCMOS. A typical IC has thousands of transistors, which are formed together in semiconductor material on a substrate, connected by integrated wiring, such as metal traces. A power IC can have larger but fewer transistors, for example only 10 transistors. The semiconductor chip 30 can have power transistors, which are connected to the transformer to form a power converter.

[0096] While pins and balls have been described for mounting the shielded transformer semiconductor package to a PCB system board, many variations are possible. The pins can be leads, bent leads or bent pins, flat surface mount pads, and can be mounted to holes in the PCB or pads on the surface of the PCB.

[0097] While external package pins have been described as placed at the perimeter of the shielded transformer semiconductor package, some or all of these pins, balls or connectors can be in a grid or array, such as in a ball grid array (BGA) package.

[0098] While a plastic package has been described for the package, the shielded transformer semiconductor package can be a ceramic package or a hybrid package. The PCB can be rigid or flexible, and can be some other type of substrate or larger module or support or frame in the system.

[0099] While in Figure 6 The upper ferrite-dielectric shield layer 24 can also completely cover the transformer coil 10. Both the upper ferrite-dielectric shield layer 24 and the lower ferrite-dielectric shield layer 26 can extend beyond the transformer coils 10, 11 and be squeezed or pinched together, in contact with each other, to seal the perimeter edges of the transformer coils 10, 11.

[0100] For a typical resonant converter topology, such as a half-bridge LLC resonant converter, the ratio of primary to secondary turns (turns ratio) can be approximately 16: 1. This can be achieved with 8 upper transformer windings 10, 10' and one lower transformer winding 11, with the lower transformer winding 11 having only half the number of turns per layer as the upper transformer windings 10, 10'. Many other variations are possible for different desired input and output voltages.

[0101] While a parallel connection of the transformer windings 10, 10' has been shown, the upper transformer windings 10, 10' can be connected in series using additional leadframe elements or posts to connect the outer windings of the upper transformer winding 10 to the center winding of the upper transformer winding 10'. Likewise, the lower transformer windings 11, 11' can be connected in series or in parallel. The upper transformer windings 10, 10' can be connected in series while the lower transformer windings 11, 11' are connected in parallel, or vice versa.

[0102] Instead of using the leadframe outer post 45 for external connection from the transformer winding 10, an internal connection is made within the package from the outer winding of the transformer winding 10 back to one of the leadframe posts 46 that does not have an external connection, through a wire bond 42 to a pad on the semiconductor die 30. Other internal connections are possible. Connections both internal to the semiconductor die 30 and external to the package pins are possible.

[0103] The transformer windings 10, 11 are considered to be air core transformers because the air core 14 in the center of the planar windings has no ferrite, even though the ferrite layers 12 are above and below the plane of the transformer windings 10, increasing the inductance of the windings like a ferrite core. The center post 36 can be within the air core in the center of the transformer winding 10. Although the center post 36 is connected to the transformer winding 10, it is not considered to be a metal core of the transformer winding 10.

[0104] The transformer winding 10 is a metal winding, connected to the semiconductor die 30 through the center post 36 and the die attach pad 34, and connected to an external package pin through the leadframe outer post 45 on the other end, so the transformer winding 10 can be considered to be part of the package leadframe, along with the leadframe pads 40 and the leadframe posts 46. Thus, the transformer winding 10 is integrated with the package leadframe.

[0105] There can be more than two upper transformer windings 10, 10', and there can be more than two lower transformer windings 11, 11'. The number of windings on the primary and secondary need not be the same. While the upper transformer windings 10, 10' have been described as the primary, the lower transformer windings 11, 11' can also be the primary.

[0106] The primary and secondary can share a ground or have separate grounds. When a shared ground is used, an internal connection can be made between the primary and secondary. When the semiconductor chip 30 is part of the primary side of the power converter, it is useful to use the top transformer winding 10 as the primary because the top transformer winding 10 is closer to the semiconductor chip 30 than the bottom transformer winding 11. Alternatively, when the semiconductor chip 30 is part of the secondary side of the power converter, the top transformer winding 10 can be used as the secondary because of its proximity to the semiconductor chip 30 and the bottom transformer winding 11 can be used as the primary. Various external connections can be made between the top transformer winding 10 or the bottom transformer winding 11 and the primary or secondary side of the power converter.

[0107] By using the ferrite layer 12, the EMI generated by the current flowing through the transformer winding 10 and received by the metal traces or other components on the semiconductor chip 30 is reduced by at least 90%. The electromagnetic flux is blocked by the ferrite layer 12 placed between the transformer winding 10 and the semiconductor chip 30. The dielectric layer 20 prevents a short circuit between the transformer winding 10 and the semiconductor chip 30 or other conductors.

[0108] The background section of this patent document can contain background information not constituting the prior art. Thus, the contents of the background section are not to be taken as an admission that anything discussed in the background section is prior art with respect to this application.

[0109] Any method or process described herein is machine- or computer-implemented and is intended to be performed by a machine, computer, or other device, without the assistance of a human being. Tangible results produced can include reports or other machine-generated displays on display devices such as computer displays, projection devices, audio generation devices, and related media devices, can include hard copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0110] Any advantages and benefits described can not apply to all embodiments of the present application. In general, the word "comprise" or variations such as "comprises" or "comprising" will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers. Such a device plus function claim does not invoke 35 U.S.C. 112, sixth paragraph, unless the jurisdiction specifies that all function claims must invoke 35 U.S.C. 112, sixth paragraph. The device plus function claims recite a means plus function claim under 35 U.S.C. § 112, paragraph 6. It is believed that 35 U.S.C. § 112, paragraph 6 applies by its terms to means plus function claims regardless whether the jurisdiction specifies that all function claims must invoke 35 U.S.C. § 112, paragraph 6. Signals are typically electronic signals, but can also be optical signals, for example, that can be transmitted over fiber optic lines.

[0111] The foregoing description of embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A semiconductor package with integrated and shielded leadframe transformer, comprising: a semiconductor die having transistors formed in a semiconductor material and integrated with integrated wiring on a die substrate; die pads connected to the integrated wiring and formed on a periphery of the die substrate; a first transformer winding having a first air core, the first transformer winding being a planar transformer, the first transformer winding lying in a plane of the first transformer winding, the plane of the first transformer winding being parallel to a plane of the semiconductor die; a second transformer winding having a second air core, the second transformer winding being a planar transformer, the second transformer winding lying in a plane of the second transformer winding, the plane of the second transformer winding being parallel to the plane of the semiconductor die; an upper ferrite-dielectric shield layer having a first ferrite layer and a first dielectric layer above the first ferrite layer and a second dielectric layer below the first ferrite layer, the first transformer winding being electrically isolated from the first ferrite layer by the second dielectric layer; wherein the upper ferrite-dielectric shield layer lies in a plane parallel to a plane between the plane of the first transformer winding and the plane of the semiconductor die; a third dielectric layer for electrically isolating the first transformer winding from the second transformer winding, the third dielectric layer being between the first transformer winding and the second transformer winding; a plurality of leadframe pads placed on a periphery of the first transformer winding and on a periphery of the second transformer winding and surrounding the semiconductor die; wire bonds connecting the die pads on the semiconductor die to the plurality of leadframe pads; a plurality of leadframe posts connecting the plurality of leadframe pads to package pins for electrical connection to an external system; a first center post connected to an inner end of the first transformer winding and electrically connected to the semiconductor die; a first leadframe outer post connecting an outer end of the first transformer winding to a package pin for electrical connection to the external system; a second center post connected to an inner end of the second transformer winding and connected to a second package pin for electrical connection to the external system; a second leadframe outer post connecting an outer end of the second transformer winding to a third package pin for electrical connection to the external system.

2. The semiconductor package with integrated and shielded leadframe transformer of claim 1, wherein, electromagnetic flux produced by current flowing through the first transformer winding between the inner end and the outer end of the first transformer winding is at least 90% shielded by the first ferrite layer from the semiconductor die; wherein the electromagnetic flux produced by current flowing through the first transformer winding produces an induced current flowing through the second transformer winding; whereby the first ferrite layer reduces electromagnetic interference (EMI) produced by the first transformer winding and received by the semiconductor die by at least 90%.

3. The semiconductor package with integrated and shielded leadframe transformer of claim 2, wherein, the plurality of leadframe posts pass through the plane of the first transformer winding outside a periphery of the first transformer winding; wherein the plurality of leadframe posts pass through a plane of the second transformer coil outside a perimeter of the second transformer coil.

4. The semiconductor package with integrated and shielded leadframe transformer of claim 3, further comprising: a lower ferrite-dielectric shield layer having a second ferrite layer and a fourth dielectric layer above the second ferrite layer and a fifth dielectric layer below the second ferrite layer, the second transformer coil being electrically isolated from the second ferrite layer by the fourth dielectric layer; wherein the lower ferrite-dielectric shield layer is in a lower plane parallel to and below the second transformer coil plane and the first transformer coil plane and the semiconductor chip plane.

5. The semiconductor package with integrated and shielded leadframe transformer of claim 4, further comprising: a chip mount pad attached to a bottom of the semiconductor chip; wherein the first center post is electrically connected to the semiconductor chip through the chip mount pad.

6. The semiconductor package with integrated and shielded leadframe transformer of claim 5, further comprising: wire bonds from the chip pad to the chip mount pad to form an electrical connection from the semiconductor chip to the chip mount pad and through the first center post to a center terminal of the first transformer coil.

7. The semiconductor package with integrated and shielded leadframe transformer of claim 6, wherein, the package pins include solder balls for soldering to pads on a printed circuit board (PCB).

8. The semiconductor package with integrated and shielded leadframe transformer of claim 7, further comprising: an encapsulant placed around and between the wire bonds and used to encapsulate the semiconductor chip.

9. The semiconductor package with integrated and shielded leadframe transformer of claim 6, wherein the first air core is in a center of the first transformer coil, wherein the first center post passes through a hole in an upper ferrite-dielectric shield layer above the first air core to connect the semiconductor chip to an inner terminal of the first transformer coil, wherein the second air core is in a center of the second transformer coil; wherein the first transformer coil and the second transformer coil form an air core transformer.

10. The semiconductor package with integrated and shielded leadframe transformer of claim 9, wherein the second center post further includes a cross post connecting from the second transformer coil center to a leadframe post outside a second transformer coil outer winding, the cross post being above or below the second transformer coil plane.

11. The semiconductor package with integrated and shielded leadframe transformer of claim 9, further comprising: a third transformer coil having an air core, the third transformer coil being a planar transformer, the third transformer coil being in a third transformer coil plane, the third transformer coil plane being parallel to the semiconductor chip plane; wherein the center post further extends downward from the first transformer coil inner terminal to a third transformer coil inner terminal; the third transformer coil being electrically connected to the semiconductor chip through the third center post. wherein the leadframe outer post further comprises a coil post connected to an outer end of the third transformer coil; wherein the first transformer coil and the third transformer coil are connected in series between the semiconductor chip and the leadframe outer post.

12. The semiconductor package with integrated and shielded leadframe transformer of claim 9, further comprising: a third transformer coil having a third air core, the third transformer coil being a planar transformer having a third transformer coil plane, the third transformer coil plane being parallel to the second transformer coil plane; a third center post connected to an inner end of the third transformer coil and connected to the second package pin; a third leadframe outer post connecting an outer end of the third transformer coil to a third package pin for electrical connection to an external system; wherein the third transformer coil is connected in series with the second transformer coil.

13. A semiconductor-transformer package shielded from electromagnetic interference (EMI), comprising: a semiconductor chip having chip pads connected to semiconductor transistors through an interconnect layer, the interconnect layer being integrated entirely on a chip substrate; a chip mount pad to which the semiconductor chip is mounted; a first transformer coil located below the chip mount pad; a second transformer coil located below the first transformer coil; a third dielectric layer located between the first transformer coil and the second transformer coil; a first ferrite-dielectric shield layer located between the first transformer coil and the chip mount pad for shielding the semiconductor chip from electromagnetic interference generated by the first transformer coil; wherein the first ferrite-dielectric shield layer includes a first ferrite layer located between a first upper dielectric layer and a first lower dielectric layer, the first upper dielectric layer electrically isolating the first ferrite layer from the semiconductor chip; an opening in the first ferrite-dielectric shield layer, the opening being located below the chip mount pad, the opening being located above a central air core of the first transformer coil, the first transformer coil having a metal coil wound from an inner end at the central air core to an outer end; leadframe posts located around the first transformer coil and the semiconductor chip, each leadframe post having a top pad for receiving a wire bond from a chip pad on the semiconductor chip, each leadframe post having an outer connection end for electrical connection to an external system; whereby the first ferrite layer protects the semiconductor chip from electromagnetic interference generated by the first transformer coil.

14. The semiconductor-transformer package shielded from electromagnetic interference of claim 13, further comprising: a first center post passing through the opening in the first ferrite-dielectric shield layer to connect the chip mount pad to an inner end of the first transformer coil; wherein the chip mount pad further comprises an electrical connection from the semiconductor chip to the first center post, Thus, the semiconductor chip is electrically connected to the inner end of the first transformer coil through the chip mounting pad and the first center post.

15. The EMI shielded semiconductor-transformer package of claim 14, further comprising: a first leadframe outer post connected to an outer end of the first transformer coil, the first leadframe outer post having an external connector end for electrical connection to an external system; a second leadframe outer post connected to an outer end of the second transformer coil, the second leadframe outer post having an external connector end for electrical connection to an external system; a third leadframe outer post having an extension connected to an inner end of the second transformer coil, the third leadframe outer post having an external connector end for electrical connection to an external system; wherein the first transformer coil is electrically connected between the semiconductor chip and the external connector end of the first leadframe outer post; wherein the second transformer coil is electrically connected between the external connector end of the second leadframe outer post and the external connector end of the third leadframe outer post.

16. The EMI shielded semiconductor-transformer package of claim 15, further comprising: a second ferrite-dielectric shield layer located below the second transformer coil; wherein the second ferrite-dielectric shield layer includes a second ferrite layer between a second upper dielectric layer and a second lower dielectric layer, the second upper dielectric layer electrically isolating the second ferrite layer.

17. The EMI shielded semiconductor-transformer package of claim 13, wherein, the first transformer coil is flexible and bendable out of a plane of the first transformer coil; the second transformer coil is flexible and bendable out of a plane of the second transformer coil.

18. An integrated circuit (IC) package having integrated and shielded transformers, comprising: a first transformer coil having a first air core, the first transformer coil being a planar inductor located in a first coil plane; a second transformer coil having a second air core, the second transformer coil being a planar inductor located in a second coil plane parallel to the first coil plane; an upper ferrite-dielectric shield layer located above the first transformer coil; a lower ferrite-dielectric shield layer located below the second transformer coil; a third dielectric layer located between the first transformer coil and the second transformer coil; wherein the upper ferrite-dielectric shield layer includes an upper ferrite layer surrounded by a first upper dielectric layer and a first lower dielectric layer; the lower ferrite-dielectric shield layer includes a lower ferrite layer surrounded by a second upper dielectric layer and a second lower dielectric layer; a package substrate for mounting to a semiconductor chip; an external package connector for soldering the IC package to an external printed circuit board (PCB); wherein the upper ferrite layer protects the semiconductor chip from electromagnetic interference (EMI) generated by current flowing through the first transformer coil.

19. The IC package of claim 18, wherein, the external package connector includes solder balls located on the package substrate for external connection.

20. The IC package of claim 18, wherein, The semiconductor chip is surface-mounted to the packaging substrate. The semiconductor chip is surface-mounted to the packaging substrate.

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