Zener diodes with adjustable breakdown voltage in BCD process

Abstract

This application provides a Zener diode with freely adjustable breakdown voltage in a BCD process, comprising: an N-type buried layer and a P-type buried layer located in a P-type substrate, wherein a P-type epitaxial layer is formed on the P-type substrate; a P-well and an N-well located above the N-type buried layer and within the P-type epitaxial layer, wherein the bottom of the P-well and the bottom of the N-well are in contact with the N-type buried layer; multiple isolation components; three P-type body regions located in the P-well, wherein a first N+ injection region is formed in the middle P-type body region, and first P+ injection regions are formed in the left and right P-type body regions; a gate structure located on the surface of the P-well; a second N+ injection region located in the N-well; and a second P+ injection region located above the P-type buried layer and within the P-type epitaxial layer. The breakdown voltage of the Zener diode can be controlled by increasing the injection type of the first P+ injection region or adjusting the feature size of the gate structure, without affecting the performance of LDMOS devices fabricated on the same BCD process platform.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a Zener diode with freely adjustable breakdown voltage in a BCD process. Background Technology

[0002] A Zener diode is a surface-contact crystal diode that utilizes the avalanche breakdown effect; it is also called a Zener diode. A Zener diode works by utilizing the principle that when a PN junction operates in reverse breakdown mode, the current changes significantly near the breakdown voltage, while the voltage change is minimal. It is a semiconductor device that exhibits high resistance until the critical reverse breakdown voltage. During reverse breakdown, the terminal voltage remains almost constant within a certain current range (or a certain power loss range), exhibiting voltage regulation characteristics. When the reverse voltage of a Zener diode increases to a certain value, a small change in bias voltage will cause a considerable increase in current. At this critical breakdown point, the reverse resistance drops to a very small value; in this low-resistance region, the current increases while the voltage remains constant. The voltage that causes this effect is called the "breakdown" voltage or "Zener voltage," and it is widely used in regulated power supplies and limiting circuits.

[0003] Zener diodes are widely used in regulated power supplies as reference voltage sources or as protection diodes in overcurrent protection circuits. In low-voltage circuits, they are often used as voltage regulators. They are also used for surge protection, overvoltage protection, arc suppression, and series regulation, and can be used to suppress transient interference and extremely high-speed pulse interference. Zener diodes are also widely used in LEDs; for example, when manufacturing high-power LEDs, a Zener diode can be connected in parallel to protect against ESD, or in series to help regulate voltage and prevent damage to the LED element from current.

[0004] BCD technology is a technology that can integrate bipolar transistors, CMOS and DMOS devices onto a single chip. Its basic processes are standardized, and hybrid processes are composed of these basic processes. Those skilled in the art can add or remove corresponding process steps according to actual needs.

[0005] In the BCD process, vertical Zener diodes can be fabricated using the P-body structure of a switch NLDMOS (SNLDMOS) device.

[0006] Since the P-type body region structure is used to fabricate the source region of both SNLDMOS and other LDMOS, adjusting the Zener diode's breakdown voltage by changing the injection parameters of the P-type body region structure will also affect the performance of the LDMOS device, such as the breakdown voltage (BV) and on-resistance (Rsp). Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a Zener diode with freely adjustable breakdown voltage in BCD process, comprising:

[0008] The N-type buried layer and the P-type buried layer are located in the P-type substrate, and a P-type epitaxial layer is formed on the P-type substrate.

[0009] P-well and N-well are located above the N-type buried layer and within the P-type epitaxial layer. The bottom of P-well and N-well are in contact with the N-type buried layer.

[0010] Multiple isolation components are distributed on the surface of the P-type epitaxial layer;

[0011] Three P-type body regions are located in the P-well, wherein the first N+ injection region is formed in the middle P-type body region, and the first P+ injection region is formed in the P-type body regions on the left and right sides.

[0012] The gate structure is located on the surface of the P-well;

[0013] The second N+ injection region is located in the N-well;

[0014] The second P+ injection region is located above the P-type buried layer and within the P-type epitaxial layer.

[0015] Preferably, the first N+ injection region and the P-type body region located in the middle constitute a vertical Zener diode.

[0016] Preferably, the breakdown voltage of the Zener diode is controlled by increasing the injection type of the first P+ injection region or by adjusting the feature size of the gate structure.

[0017] Preferably, the implantation type for increasing the first P+ implantation region includes increasing a 5V P-type lightly doped drain.

[0018] Preferred process parameters for adding a 5V P-type lightly doped drain: implantation energy 10keV-30keV, implantation dose 1E13cm -2 -1E14cm -2 .

[0019] Preferably, the breakdown voltage of the Zener diode is reduced by decreasing the width of the gate structure.

[0020] Preferably, the injection parameters for the three P-type body regions are the same.

[0021] On the other hand, this application also provides a Zener diode with freely adjustable breakdown voltage in BCD process, comprising:

[0022] The N-type buried layer and the P-type buried layer are located in the P-type substrate, and a P-type epitaxial layer is formed on the P-type substrate.

[0023] P-well and N-well are located above the N-type buried layer and within the P-type epitaxial layer. The bottom of P-well and N-well are in contact with the N-type buried layer.

[0024] Multiple isolation components are distributed on the surface of the P-type epitaxial layer;

[0025] Two P-type body regions are located in a P-well, wherein a first N+ injection region is formed in the P-well between the two P-type body regions, and a first P+ injection region is formed in the two P-type body regions.

[0026] The gate structure is located on the surface of the P-well;

[0027] The second N+ injection region is located in the N-well;

[0028] The second P+ injection region is located above the P-type buried layer and within the P-type epitaxial layer.

[0029] Preferably, the first N+ injection region, the P-type body region, and the first P+ injection region constitute a lateral Zener diode.

[0030] Preferably, the breakdown voltage of the Zener diode is controlled by adjusting the feature size of the gate structure.

[0031] Preferably, the breakdown voltage of the Zener diode is increased by increasing the width of the gate structure.

[0032] Preferably, the injection parameters for the two P-type body regions are the same.

[0033] As described above, the Zener diode with freely adjustable breakdown voltage in the BCD process provided in this application has the following beneficial effects: the breakdown voltage of the Zener diode can be controlled by increasing the injection type of the first P+ injection region or adjusting the feature size of the gate structure without changing the doping situation of the P-type body region, thereby not affecting the performance of LDMOS devices fabricated on the same BCD process platform. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 The diagram shows a cross-sectional structure of a Zener diode fabricated using existing technology on a BCD process platform.

[0036] Figure 2The diagram shows a cross-sectional structure of a Zener diode with freely adjustable breakdown voltage in the BCD process provided in the embodiments of this application.

[0037] Figure 3 The diagram shown is a cross-sectional view of a Zener diode with freely adjustable breakdown voltage in a BCD process according to another embodiment of this application. Detailed Implementation

[0038] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0039] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0042] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0043] Please see Figure 1It shows a schematic cross-sectional structure of a Zener diode fabricated using existing technology on a BCD process platform.

[0044] A P-type substrate 100 is provided, on which an N-type buried layer 101 and a P-type buried layer 102 are formed. A P-type epitaxial layer (P-EPI) 103 is also formed on the P-type substrate 100, covering the entire P-type substrate 100.

[0045] N-well 105 and P-well 106 are formed in the P-type epitaxial layer 103, and the bottom of N-well 105 and the bottom of P-well 106 are in contact with the N-type buried layer 101.

[0046] A plurality of isolation members 107 are formed in the P-type epitaxial layer 103 and distributed on the surface of the P-type epitaxial layer 103. As an example, the isolation members 107 are shallow trench isolation (STI).

[0047] The P-type epitaxial layer 103 also has a P-type body region 108 and a second P+ implantation region 109, a first N+ implantation region 110 formed in the P-type body region 108, a second N+ implantation region 111 formed in the N-well 105, and a first P+ implantation region 112 formed in the P-well 106.

[0048] A gate structure 113 is formed on the P-type epitaxial layer 103 on both sides of the first N+ implantation region 110. As an example, the gate structure 113 includes a gate oxide layer 113a and a gate material layer 113b stacked from bottom to top.

[0049] The first N+ injection region 110 and the P-type body region 108 constitute a Zener diode, and the first P+ injection region 112 serves as the lead-out terminal of the P-type body region 108.

[0050] The isolation component 107 achieves surface isolation between the P-type body region 108 and the first P+ injection region 112, between the first P+ injection region 112 and the second N+ injection region 111, and between the second N+ injection region 111 and the second P+ injection region 109.

[0051] In regulation, such as Figure 1 When determining the breakdown voltage of the Zener diode shown, the injection parameters of the P-type body region 108 need to be adjusted. In the existing BCD process platform, the injection of the P-type body region 108 and the P-type body region of the LDMOS use the same mask. Therefore, adjusting the injection parameters of the P-type body region 108 will also change the doping of the P-type body region of the LDMOS, thereby affecting the performance of the LDMOS.

[0052] Please see Figure 2 The diagram shows a cross-sectional view of a Zener diode with freely adjustable breakdown voltage in the BCD process provided in this application embodiment.

[0053] A P-type substrate 200 is provided, on which an N-type buried layer 201 and a P-type buried layer 202 are formed. A P-type epitaxial layer 203 is also formed on the P-type substrate 200, covering the entire P-type substrate 200.

[0054] N-well 205 and P-well 206 are formed in the P-type epitaxial layer 203, and the bottom of N-well 205 and the bottom of P-well 206 are in contact with the N-type buried layer 201.

[0055] A plurality of isolation components 207 are formed in the P-type epitaxial layer 203 and distributed on the surface of the P-type epitaxial layer 203. As an example, the isolation components 207 are shallow trench isolations.

[0056] A second P+ injection region 209 is formed in the P-type epitaxial layer 203, a second N+ injection region 211 is formed in the N-well 205, and three P-type body regions 208 are formed in the P-well 206. A first N+ injection region 210 is formed in the middle P-type body region 208, and a first P+ injection region 212 is formed in the P-type body regions 208 on the left and right sides.

[0057] The injection parameters for the three P-shaped body regions 208 are the same, the only difference being the width of the P-shaped body regions 208 located on the left and right sides and the width of the P-shaped body region 208 located in the middle. Typically, the width of the P-shaped body regions 208 located on the left and right sides is smaller than the width of the P-shaped body region 208 located in the middle.

[0058] The isolation component 207 achieves surface isolation between the P-type body region 208 and the second N+ injection region 211, and between the second N+ injection region 211 and the second P+ injection region 212.

[0059] A gate structure 213 is formed on the surface of the P-well 206. As an example, the gate structure 213 includes a gate oxide layer 213a and a gate material layer 213b stacked from bottom to top. Sidewall structures 215 are formed on both sides of the gate structure 213.

[0060] Production Figure 2 In the process of creating the Zener diode shown, a P-type body region 208 is formed through two ion implantation processes using the gate structure 213 as a mask. Typically, the implantation energy of the second p-type ion implantation is lower than that of the first p-type ion implantation, the implantation dose of the second p-type ion implantation is greater than that of the first p-type ion implantation, and the implantation angle of the second p-type ion implantation is also larger.

[0061] Using the gate structure 213 with sidewall structure 215 as a mask, the first N+ implantation region 210 and the first P+ implantation region 212 are formed by ion implantation process.

[0062] The spacing between the gate structures 213 determines the size of the implantation window feature size for the ion implantation process that forms the P-type body region 208. Because the feature size of the spacing between the gate structures 213 is small, the P-type body regions 208 located on the left and right sides and the P-type body region 208 located in the middle will partially overlap.

[0063] The first N+ injection region 210 and the P-type body region 208 located in the middle constitute a vertical Zener diode.

[0064] The breakdown voltage of a Zener diode is typically around 5.7V. Figure 2 The Zener diode shown is suitable for applications with high breakdown voltage.

[0065] In regulation, such as Figure 2 To reduce the breakdown voltage of the Zener diode shown, in order to avoid affecting the performance of the LDMOS, without changing the injection parameters of the P-type body region 208, the breakdown voltage can be reduced by increasing the injection type of the first P+ injection region 212 or adjusting the feature size of the gate structure 213.

[0066] As an example, the implantation type for adding the first P+ implantation region 212 could be adding a 5V P-type lightly doped drain (PLDD), with the following process parameters: implantation energy 10keV-30keV, implantation dose 1E13 cm⁻¹. -2 -1E14cm -2 .

[0067] Adjusting the feature size of the gate structure 213 means reducing the width of the gate structure 213, thereby shortening the distance between the first N+ injection region 210 and the first P+ injection region 212 and reducing the breakdown voltage.

[0068] Please see Figure 3 The diagram shows a cross-sectional view of a Zener diode with freely adjustable breakdown voltage in a BCD process according to another embodiment of this application.

[0069] A P-type substrate 300 is provided, on which an N-type buried layer 301 and a P-type buried layer 302 are formed. A P-type epitaxial layer 303 is also formed on the P-type substrate 300, covering the entire P-type substrate 300.

[0070] N-well 305 and P-well 306 are formed in the P-type epitaxial layer 303, and the bottom of N-well 305 and the bottom of P-well 306 are in contact with the N-type buried layer 301.

[0071] A plurality of isolation members 307 are formed in the P-type epitaxial layer 303 and distributed on the surface of the P-type epitaxial layer 303. As an example, the isolation members 307 are shallow trench isolations.

[0072] A second P+ implantation region 309 is formed in the P-type epitaxial layer 303, a second N+ implantation region 311 is formed in the N-well 305, two P-type body regions 308 with the same implantation parameters are formed in the P-well 306, a first N+ implantation region 310 is formed in the P-well 306 between the two P-type body regions 308, and a first P+ implantation region 312 is formed in the P-type body region 308.

[0073] The isolation component 307 achieves surface isolation between the P-type body region 308 and the second N+ injection region 311, and between the second N+ injection region 311 and the second P+ injection region 312.

[0074] A gate structure 313 is formed on the surface of the P-well 306. As an example, the gate structure 313 includes a gate oxide layer 313a and a gate material layer 313b stacked from bottom to top. Sidewall structures 315 are formed on both sides of the gate structure 313.

[0075] Production Figure 3 In the process of creating the Zener diode shown, a P-type body region 308 is formed through two ion implantation processes using the gate structure 313 as a mask. Typically, the implantation energy of the second p-type ion implantation is lower than that of the first p-type ion implantation, the implantation dose of the second p-type ion implantation is greater than that of the first p-type ion implantation, and the implantation angle of the second p-type ion implantation is also larger.

[0076] Using the gate structure 313 with sidewall structure 315 as a mask, the first N+ implantation region 310 and the first P+ implantation region 312 are formed by ion implantation process.

[0077] The spacing between the gate structures 313 determines the size of the implantation window feature size for the ion implantation process that forms the P-type body region 308.

[0078] The first N+ injection region 310, the P-type body region 308, and the first P+ injection region 312 constitute a lateral Zener diode.

[0079] The breakdown voltage of a Zener diode is typically around 5.7V. Figure 3 The Zener diode shown is suitable for applications with low breakdown voltage.

[0080] In regulation, such as Figure 3 To avoid affecting the performance of the LDMOS, the breakdown voltage of the Zener diode shown is increased by adjusting the feature size of the gate structure 313 without changing the injection parameters of the P-type body region 308.

[0081] Adjusting the feature size of the gate structure 313 means increasing the width of the gate structure 313, thereby increasing the spacing between the first N+ injection region 310 and the first P+ injection region 312, and increasing the breakdown voltage.

[0082] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0083] In summary, the Zener diode with freely adjustable breakdown voltage in the BCD process provided in this application has the following advantages: the breakdown voltage of the Zener diode can be controlled by increasing the injection type of the first P+ injection region or adjusting the feature size of the gate structure, without changing the doping situation of the P-type body region, thus not affecting the performance of LDMOS devices fabricated on the same BCD process platform. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0084] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A Zener diode with freely adjustable breakdown voltage in BCD process, characterized in that, The Zener diode includes: An N-type buried layer and a P-type buried layer are located in a P-type substrate, and a P-type epitaxial layer is formed on the P-type substrate; P-well and N-well, wherein the P-well and the N-well are located above the N-type buried layer and within the P-type epitaxial layer, and the bottom of the P-well and the bottom of the N-well are in contact with the N-type buried layer; Multiple isolation components are distributed on the surface of the P-type epitaxial layer; Three P-type body regions are located in the P-well. A first N+ injection region is formed in the middle P-type body region, and first P+ injection regions are formed in the left and right P-type body regions. The first N+ injection regions and the middle P-type body region constitute a vertical Zener diode. A gate structure located on the surface of the P-well, wherein the breakdown voltage of the Zener diode is modulated by increasing the injection type of the first P+ injection region or by adjusting the feature size of the gate structure; The second N+ injection region is located in the N-well; The second P+ injection region is located above the P-type buried layer and within the P-type epitaxial layer.

2. The Zener diode according to claim 1, characterized in that, The addition of the implantation type to the first P+ implantation region includes adding a 5V P-type lightly doped drain.

3. The Zener diode according to claim 2, characterized in that, The process parameters for adding a 5V P-type lightly doped drain are: implantation energy 10keV-30keV, implantation dose 1E13 cm⁻¹. -2 -1E14cm -2 .

4. The Zener diode according to claim 1, characterized in that, The breakdown voltage of the Zener diode is reduced by decreasing the width of the gate structure.

5. The Zener diode according to claim 1, characterized in that, The injection parameters for the three P-type body regions are the same.

6. A Zener diode with freely adjustable breakdown voltage in BCD process, characterized in that, The Zener diode includes: An N-type buried layer and a P-type buried layer are located in a P-type substrate, and a P-type epitaxial layer is formed on the P-type substrate; P-well and N-well, wherein the P-well and the N-well are located above the N-type buried layer and within the P-type epitaxial layer, and the bottom of the P-well and the bottom of the N-well are in contact with the N-type buried layer; Multiple isolation components are distributed on the surface of the P-type epitaxial layer; Two P-type body regions are located in the P-well, wherein a first N+ injection region is formed in the P-well between the two P-type body regions, and a first P+ injection region is formed in the two P-type body regions. The first N+ injection region, the P-type body region, and the first P+ injection region constitute a lateral Zener diode. A gate structure located on the surface of the P-well, wherein the breakdown voltage of the Zener diode is modulated by adjusting the feature size of the gate structure; The second N+ injection region is located in the N-well; The second P+ injection region is located above the P-type buried layer and within the P-type epitaxial layer.

7. The Zener diode according to claim 6, characterized in that, The breakdown voltage of the Zener diode is increased by increasing the width of the gate structure.

8. The Zener diode according to claim 6, characterized in that, The injection parameters for the two P-type body regions are the same.

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