Switched capacitor amplification device with gain adjustment mechanism

Abstract

A switched-capacitor amplifier device with gain adjustment mechanism. The amplifier includes an input terminal and an output terminal. A capacitor circuit includes a sampling capacitor circuit, a load capacitor, and an array of level-shifting capacitors. The sampling capacitor circuit includes two input terminals and a sampling output terminal to receive an input signal from the signal input terminal for sampling and output to the input terminal of the amplifier. The load capacitor and the array of level-shifting capacitors are respectively charged according to the output of the amplifier at the output terminal. After the load capacitor is charged by the array of level-shifting capacitors, the load capacitor is charged to a level-shifting by the array of level-shifting capacitors to generate an output signal through the signal output terminal. A control circuit determines an enabled combination of level-shifting capacitors included in the array of level-shifting capacitors to determine an equivalent capacitance value, and further determines a loop gain between the output signal and the input signal.

Description

TECHNICAL FIELD

[0001] The present application relates to signal amplification technology, and in particular, to a switched-capacitor amplifier device with gain adjustment mechanism. BACKGROUND

[0002] In analog signal processing circuits, gain stage circuits are often needed to amplify input analog signals. In some technologies, switched-capacitor amplifier circuits are often used to implement gain stage circuits.

[0003] Switched-capacitor amplifier circuits need to use operational amplifiers and a set of capacitors to amplify input signals. However, due to environmental factors, operational amplifiers often cannot maintain stable DC gain. Once the DC gain changes, it will affect the loop gain between the output signal and the input signal. SUMMARY

[0004] In view of the problems in the prior art, an object of the present application is to provide a switched-capacitor amplifier device with gain adjustment mechanism and method to improve the current technology.

[0005] The present application includes a switched-capacitor amplifier device with gain adjustment mechanism, comprising an amplifier, a capacitor circuit, and a control circuit. The amplifier includes an input terminal and an output terminal. The capacitor circuit corresponds to the signal input terminal and the signal output terminal, and includes a sampling capacitor circuit, a load capacitor, and a level-shifting capacitor array. The sampling capacitor circuit includes two sampling input terminals and a sampling output terminal, wherein the two sampling input terminals receive input signals from the signal input terminal for sampling to output to the input terminal of the amplifier through the sampling output terminal. The level-shifting capacitor array includes a plurality of level-shifting capacitors. The load capacitor and the level-shifting capacitor array have a plurality of connection relationships with the output terminal of the amplifier, so that the load capacitor is first charged according to the output of the amplifier at the output terminal, and then the level-shifting capacitor array charges the load capacitor to achieve level-shifting, so that the load capacitor generates an output signal through the signal output terminal. The control circuit determines the enabled combination of the level-shifting capacitors to determine the equivalent capacitance value of the level-shifting capacitor array, and then determines the loop gain between the output signal and the input signal.

[0006] The application further includes a switched-capacitor amplification method with gain adjustment mechanism, applied to a switched-capacitor amplification device, comprising: sampling the two sampling input ends of a sampling capacitor circuit of a capacitor circuit from the input signal received by the signal input end, to output to the input end of an amplifier through the sampling output end; generating a plurality of connection relationships between a load capacitor and a level-lifting capacitor array comprising a plurality of level-lifting capacitors and the output end of the amplifier, to first charge the load capacitor according to the output of the amplifier at the output end, and then charge the load capacitor to achieve level-lifting by the level-lifting capacitor array, so that the load capacitor generates an output signal through the signal output end; and determining the enabled combination of the level-lifting capacitors by a control circuit to determine the equivalent capacitance value of the level-lifting capacitor array, and then determine the loop gain between the output signal and the input signal.

[0007] The features, implementations, and effects of the application will be described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram of a switched-capacitor amplification device with gain adjustment mechanism in an embodiment of the application is shown.

[0009] Figures 2A to 2C A more detailed circuit diagram of the switched-capacitor amplification device in different operation periods in an embodiment of the application is shown.

[0010] Figure 3 A more detailed circuit diagram of the level-lifting capacitor array in an embodiment of the application is shown.

[0011] Figure 4 A block diagram of a switched-capacitor amplification device in an embodiment of the application is shown. Figure 5 A flowchart of a switched-capacitor amplification method with gain adjustment mechanism in an embodiment of the application is shown.

[0012] SYMBOL DESCRIPTION

[0013] 100: switched-capacitor amplification device

[0014] 110: amplifier

[0015] 120: capacitor circuit

[0016] 130: control circuit

[0017] 140: sampling capacitor circuit

[0018] 400: switched-capacitor amplification device

[0019] 500: switched-capacitor amplification method

[0020] S510-S530: steps

[0021] CLD: load capacitance

[0022] CLS: level-shifting capacitor array

[0023] CLS1-CLS N : level-shifting capacitor

[0024] CS1: first sampling capacitor

[0025] CS2: second sampling capacitor

[0026] GND: ground terminal

[0027] IN1, IN2: input terminal

[0028] OUT, OUT1, OUT2: output terminal

[0029] S1, S2: sampling input terminal

[0030] S3: sampling output terminal

[0031] SIN, SIN1, SIN2: signal input terminal

[0032] SOUT, SOUT1, SOUT2: signal output terminal

[0033] SW1: first switching unit

[0034] SW2: second switching unit

[0035] SW3: third switching unit

[0036] SW4: fourth switching unit

[0037] SW5: fifth switching unit

[0038] Vin, Vin1, Vin2: input signal

[0039] Vout, Vout1, Vout2: output signal

[0040] WS: switching circuit

[0041] WS1, WS2: switching unit DETAILED DESCRIPTION

[0042] An object of the present application is to provide a switching capacitor amplification device and method with gain adjustment mechanism, by setting level-shifting capacitor array and controlling circuit control, adjusting the equivalent capacitance value of level-shifting capacitor array for the change of DC gain of amplifier, and then compensating the loop gain.

[0043] Please refer to Figure 1 .Figure 1 A block diagram of a switched-capacitor amplification device 100 with gain adjustment mechanism is shown in an embodiment of the present application. The switched-capacitor amplification device 100 comprises an amplifier 110, a capacitance circuit 120, and a control circuit 130.

[0044] In an embodiment, the amplifier 110 is an operational amplifier and comprises an input terminal IN1 and an output terminal OUT. In an embodiment, the input terminal IN1 is a non-inverting input terminal, denoted by a label '-', and the output terminal OUT is denoted by a label 'o'. In an embodiment, the amplifier 110 further comprises an input terminal IN2 which is a non-inverting input terminal, denoted by a label '+', and the input terminal IN2 is electrically coupled to a ground terminal GND.

[0045] The capacitance circuit 120 corresponds to a signal input terminal SIN and a signal output terminal SOUT, and comprises a sampling capacitance circuit 140, a load capacitance CLD, and a level-shifting capacitance array CLS.

[0046] The sampling capacitance circuit 140 comprises a sampling input terminal S1, a sampling input terminal S2, and a sampling output terminal S3. The sampling capacitance circuit 140 is configured to sample an input signal Vin received from the signal input terminal SIN by the sampling input terminal S1 and the sampling input terminal S2, and output to the input terminal IN1 of the amplifier 110 through the sampling output terminal S3.

[0047] The level-shifting capacitance array CLS comprises a plurality of level-shifting capacitances (not shown in the figure). Figure 1 Among the plurality of level-shifting capacitances, some are enabled, and some are disabled. Depending on different enabled combinations of the level-shifting capacitances, the level-shifting capacitance array CLS will have different equivalent capacitance values.

[0048] The load capacitance CLD and the level-shifting capacitance array CLS have a plurality of connection relationships with the output terminal OUT of the amplifier 110. Among the plurality of connection relationships, Figure 1 only the virtual lines of the connections are shown in the figure to indicate that the three components can be connected to each other in different ways, and the actual connection relationships are not shown. According to different connection relationships, the load capacitance CLD is first charged according to the output of the amplifier 110 at the output terminal OUT, and then the level-shifting capacitance array CLS charges the load capacitance CLD to achieve level shifting, so that the load capacitance CLD generates an output signal Vout through the signal output terminal SOUT.

[0049] The control circuit 130 determines the enabled combination of the level-shifting capacitors of the level-shifting capacitor array CLS to determine the equivalent capacitance value of the level-shifting capacitor array CLS. The equivalent capacitance value of the level-shifting capacitor array CLS will affect the amount of charge on itself and the amount of charge on the load capacitor CLD, and in turn affect the size of the output signal Vout. Therefore, the equivalent capacitance value of the level-shifting capacitor array CLS will determine the loop gain between the output signal Vout and the input signal Vin.

[0050] Please refer to Figures 2A to 2C . Figures 2A to 2C In an embodiment of the present application, the switching capacitor amplification device 100 is shown in more detail in different operation periods. The following will describe the more detailed structure and operation of the switching capacitor amplification device 100 according to Figures 2A to 2C .

[0051] As shown in Figure 2A , the sampling capacitor circuit 140 actually includes a first sampling capacitor CS1 and a second sampling capacitor CS2. The first sampling capacitor CS1 is electrically coupled between the sampling input terminal S1 and the sampling output terminal S3. The second sampling capacitor CS2 is electrically coupled between the sampling input terminal S2 and the sampling output terminal S3.

[0052] The load capacitor CLD is electrically coupled between the first connection terminal N1 and the ground terminal GND. In Figures 2A to 2C , the load capacitor CLD is shown in the form of a capacitor. The first connection terminal N1 is also electrically coupled to the signal output terminal SOUT. The level-shifting capacitor array CLS is electrically coupled between the first connection terminal N1 and the second connection terminal N2. In Figures 2A to 2C , the level-shifting capacitor array CLS is shown in the form of a variable capacitor.

[0053] In this embodiment, the switching capacitor amplification device 100 includes a first switching unit SW1, a second switching unit SW2, a third switching unit SW3, a fourth switching unit SW4, and a fifth switching unit SW5.

[0054] The first switching unit SW1 includes a first terminal electrically coupled to the sampling input terminal S1, and a second terminal switched to be electrically coupled to the signal input terminal SIN or the ground terminal GND. The second switching unit SW2 includes a first terminal electrically coupled to the sampling input terminal S2, and a second terminal switched to be electrically coupled to the signal input terminal SIN or the first connection terminal N1. The third switching unit SW3 includes a first terminal electrically coupled to the sampling output terminal S3 and the input terminal IN1 of the amplifier 110, and a second terminal switched to be electrically coupled to the ground terminal GND or electrically isolated from the ground terminal GND.

[0055] The fourth switching unit SW4 includes a first terminal electrically coupled to the first connection terminal N1, and a second terminal that switches between being electrically coupled to the output terminal OUT of amplifier 110 or electrically isolated from the output terminal OUT of amplifier 110. The fifth switching unit SW5 includes a first terminal electrically coupled to the second connection terminal N2, and a second terminal that switches between being electrically coupled to the ground terminal GND or the output terminal OUT of amplifier 110.

[0056] The switching capacitor amplification device 100 can switch between the first switching unit SW1 and the fifth switching unit SW5 according to different operating cycles, thereby achieving the function of receiving the input signal Vin and generating an amplified output signal Vout. In one embodiment, the switching capacitor amplification device 100 operates sequentially in the sampling cycle, the prediction cycle, and the level enhancement cycle.

[0057] like Figure 2A As shown, during the sampling period, the first switching unit SW1 electrically couples the sampling input terminal S1 to the signal input terminal SIN, and the second switching unit SW2 electrically couples the sampling input terminal S2 to the signal input terminal SIN. The third switching unit SW3 electrically couples the sampling output terminal S1 and the input terminal IN1 of amplifier 110 to the ground terminal GND. The fourth switching unit SW4 electrically couples the first connection terminal N1 to the output terminal OUT of amplifier 110. The fifth switching unit SW5 electrically couples the second connection terminal N2 to the ground terminal GND.

[0058] Therefore, during the sampling period, the sampling capacitor circuit 140 will receive the input signal Vin through the sampling input terminals S1 and S2 and sample the input signal Vin.

[0059] like Figure 2B As shown, during the prediction period, the first switching unit SW1 electrically couples the sampling input terminal S1 to the ground terminal GND, and the second switching unit SW2 electrically couples the sampling input terminal S2 to the first connection terminal N1. The third switching unit SW3 electrically isolates the sampling output terminal S3 and the input terminal IN1 of amplifier 110 from the ground terminal GND. The fourth switching unit SW4 electrically couples the first connection terminal N1 to the output terminal OUT of amplifier 110. The fifth switching unit SW5 electrically couples the second connection terminal N2 to the ground terminal GND.

[0060] Therefore, during the prediction period, the sampling capacitor circuit 140 outputs the sampled input signal Vin through the sampling output terminal S3 to the input terminal IN1 of the amplifier 110. Furthermore, the load capacitor CLD and the level-up capacitor array CLS are charged according to the output of the amplifier 110 at the output terminal OUT. At this time, the load capacitor CLD will cause the voltage at the signal output terminal SOUT to rise.

[0061] likeFigure 2C As shown, in the level boosting period, the first switching unit SW1 electrically couples the sampling input terminal S1 to the ground terminal GND, and the second switching unit SW2 electrically couples the sampling input terminal S2 to the first connection terminal N1. The third switching unit SW3 electrically isolates the sampling output terminal S3 and the input terminal IN1 of the amplifier 110 from the ground terminal GND. The fourth switching unit SW4 electrically isolates the first connection terminal N1 from the output terminal OUT of the amplifier 110. The fifth switching unit SW5 electrically couples the second connection terminal N2 to the output terminal OUT of the amplifier 110.

[0062] Therefore, in the level boosting period, the level boosting capacitor array CLS charges the load capacitor CLD. At this time, the load capacitor CLD will cause the voltage of the signal output terminal SOUT to rise again, achieving the effect of level boosting, to generate an output signal Vout at the signal output terminal SOUT.

[0063] In an embodiment, the relationship between the output signal Vout and the input signal Vin can be represented by the following equation:

[0064] Vout = ((CS1 + CS2) / CS2) x (1 - ((1 + λ) / (1 + A 21 β) (1 + A 22 β + λ)) Vin (Equation 1).

[0065] wherein the parameters CS1 and CS2 represent the capacitance values of the first sampling capacitor CS1 and the second sampling capacitor CS2, respectively. The parameters A 21 and A 22 represent different sizes of the DC gain of the amplifier 110 under high-swing to low-swing operation, respectively.

[0066] The parameter β is represented by the following equation:

[0067] β = (CS2 / (CS1 + CS2)) (Equation 2).

[0068] The parameter λ is represented by the following equation:

[0069] λ = CLD / CLS (Equation 3).

[0070] wherein the parameter CLD represents the capacitance value of the load capacitor CLD, and the parameter CLS represents the equivalent capacitance value of the level boosting capacitor array CLS.

[0071] In (Equation 1), the ratio between the output signal Vout and the input signal Vin is the loop gain (i.e. ((CS1 + CS2) / CS2) x (1 - ((1 + λ) / (1 + A 21 β) (1 + A 22where the loop gain includes a first term that is only related to the capacitance values of the first sampling capacitor CS1 and the second sampling capacitor CS2, and a second term that is also related to the DC gain of the amplifier 110, the capacitance value of the load capacitor CLD, and the equivalent capacitance value of the level-shifting capacitor array CLS.

[0072] As can be seen from the above equation, the DC gain of the amplifier 110 is related to the magnitude of the loop gain and the equivalent capacitance value of the level-shifting capacitor array CLS. In some application scenarios, the DC gain of the amplifier 110 can be affected by temperature, pressure, or process, and can vary by tens of decibels (dB). Therefore, the control circuit 130 can determine the enabled combination of the level-shifting capacitors according to the DC gain, so as to determine the equivalent capacitance value of the level-shifting capacitor array CLS, and further determine the loop gain between the output signal Vout and the input signal Vin.

[0073] In one embodiment, the control circuit 130 adjusts according to gain analysis between the output terminal OUT and the input terminal IN1 of the amplifier 110.

[0074] In one embodiment, the control circuit 130 determines the variation of the DC gain according to Fourier analysis between the output terminal OUT and the input terminal IN1 of the amplifier 110, so as to determine the enabled combination of the level-shifting capacitors. In one embodiment, the Fourier analysis is to feed the input terminal IN1 with a sinusoidal waveform, and analyze the output terminal OUT.

[0075] It should be noted that in some switched-capacitor amplification devices, the structure of the capacitor circuit is such that the larger the DC gain is, the better. Therefore, the control circuit 130 can increase the equivalent capacitance value (and make the parameter λ smaller) when the DC gain decreases, and decrease the equivalent capacitance value (and make the parameter λ larger) when the DC gain increases. However, in some switched-capacitor amplification devices, due to the difference in the structure of the capacitor circuit, the DC gain can achieve the best loop gain at a certain optimal value, rather than the larger the better. At this time, the control circuit 130 can adjust the equivalent capacitance value by analyzing the condition of the DC gain deviating from this optimal value.

[0076] Please refer to Figure 3 . Figure 3 A more detailed circuit diagram of the level-shifting capacitor array CLS in one embodiment of the present application is shown.

[0077] As Figure 3 shown, the level-shifting capacitor array CLS includes level-shifting capacitors CLS1-CLS N and a plurality of switching circuits. The switching circuits correspond to one of the level-shifting capacitors CLS1-CLS N , respectively. In Figure 3In the diagram, only the switching circuit WS corresponding to the level boosting capacitor CLS1 is shown as an example.

[0078] In one embodiment, the switching circuit WS includes two switching units WS1 and WS2. The control circuit 130 controls the switching circuit WS to enable or disable. When enabled, the switching circuit WS electrically couples the level-up capacitor CLS1 between the first connection terminal N1 and the second connection terminal N2, acting as an enabling capacitor. When disabled, the level-up capacitor CLS1 is electrically isolated from the first connection terminal N1 and the second connection terminal N2, acting as a disabling capacitor. Therefore, when the level-up capacitors CLS1 to CLS2 are... N When multiple capacitors are enabled, these level-up capacitors will be connected in parallel. The more capacitors enabled, the larger the effective capacitance of the level-up capacitor array CLS. The fewer capacitors enabled, the smaller the effective capacitance of the level-up capacitor array CLS.

[0079] In one embodiment, the control circuit 130 may default to enabling the level-up capacitors CLS1 to CLS. N It has a certain number of energized capacitors, so that the number of energized capacitors can be increased or decreased when needed, and the equivalent capacitance value can be adjusted up or down accordingly.

[0080] Therefore, the switching capacitor amplifier device 100 with gain adjustment mechanism in this invention can adjust the equivalent capacitance value of the level boost capacitor array CLS according to the change of DC gain of amplifier 110 by setting the level boost capacitor array CLS and controlling the control circuit 130, thereby adjusting the loop gain and compensating for the change caused by the change of DC gain.

[0081] It should be noted that the above Figures 2A to 2C The architecture of the switching capacitor amplifier 100 shown is merely an example. In different application scenarios, the detailed architecture of the switching capacitor amplifier 100 can be implemented in other different ways, and is not limited by... Figures 2A to 2C The illustrated architecture is limited. Furthermore, the architecture of the level-boosting capacitor array (CLS) can be designed differently according to actual needs and is not restricted by... Figure 3 Due to limitations in the illustrated structure.

[0082] Please refer to Figure 4 . Figure 4 This shows a block diagram of a switching capacitor amplification device 400 according to one embodiment of the present invention.

[0083] The above Figure 1 The switching capacitor amplifier 100 shown is illustrated in a single-ended input / output configuration. However, as... Figure 4 As shown in the switching capacitor amplifier device 400, in practice the switching capacitor amplifier device can also be implemented in the form of dual-ended input and output.

[0084] In this case, the switched-capacitor amplifier 400 still comprises an amplifier 110, but the amplifier 110 comprises two input terminals IN1 and IN2, and two output terminals OUT1 and OUT2. The input terminals IN1 and IN2 are denoted by labels '-' and '+', respectively, and the output terminals OUT1 and OUT2 are denoted by labels '+' and '-', respectively.

[0085] On the other hand, the switched-capacitor amplifier 400 comprises two capacitive circuits 120A and 120B. The capacitive circuit 120A corresponds to the signal input terminal SIN1 and the signal output terminal SOUT1, and is connected to the input terminal IN1 and the output terminal OUT1 of the amplifier 110. The capacitive circuit 120B corresponds to the signal input terminal SIN2 and the signal output terminal SOUT2, and is connected to the input terminal IN2 and the output terminal OUT2 of the amplifier 110. The structures and the operation modes of the capacitive circuits 120A and 120B are the same as those of the capacitive circuit 120 in Figure 1 , which are not shown in detail and will not be described again. Figure 4

[0086] Therefore, the capacitive circuit 120A is configured to receive the input signal Vin1 from the signal input terminal SIN1 and to generate the output signal Vout1 at the signal output terminal SOUT1 in the same operation mode as that of the capacitive circuit 120 in Figure 1 . The capacitive circuit 120B is configured to receive the input signal Vin2 from the signal input terminal SIN2 and to generate the output signal Vout2 at the signal output terminal SOUT2 in the same operation mode as that of the capacitive circuit 120 in Figure 1 .

[0087] The control circuit 130 can be configured to analyze the DC gain variation of the amplifier 110 according to the output signals Vout1 and Vout2 and the input signals Vin1 and Vin2, and to adjust the enabled combination of the level-shifting capacitors of the level-shifting capacitor array (not shown in Figure 4 , which is similar to the level-shifting capacitor array CLS in Figures 2A to 2C , so as to achieve the purpose of adjusting the loop gain.

[0088] Please refer to Figure 5 Figure 5 A flowchart of a switched-capacitor amplification method 500 with a gain adjustment mechanism is shown in an embodiment of the present application.

[0089] In addition to the aforementioned apparatus, the present application further discloses a switched-capacitor amplification method 500 with a gain adjustment mechanism, which is applied to, for example, but not limited to​Figure 1 The switching-capacitor amplification device 100 with the gain adjustment mechanism. An embodiment of the switching-capacitor amplification method 500 with the gain adjustment mechanism is shown in FIG. 5, which comprises the following steps.

[0090] At step S510, the two sampling input terminals S1 and S2 of the sampling capacitor circuit 140 of the capacitor circuit 120 are sampled from the input signal Vin received from the signal input terminal SIN, and output to the input terminal IN1 of the amplifier 110 through the sampling output terminal S3.

[0091] At step S520, the load capacitor CLD and the level-shifting capacitor array CLS comprising a plurality of level-shifting capacitors CLS1-CLS N are connected to the output terminal OUT of the amplifier 110, so that the load capacitor CLD is charged by the level-shifting capacitor array CLS after being charged by the output of the amplifier 110 at the output terminal OUT, to achieve level shifting, and then output the output signal Vout through the signal output terminal SOUT.

[0092] At step S530, the control circuit 130 determines the enabled combination of the level-shifting capacitors CLS1-CLS N to determine the equivalent capacitance value of the level-shifting capacitor array CLS, and then determines the loop gain between the output signal Vout and the input signal Vin.

[0093] It should be noted that the above-mentioned embodiments are only examples. In other embodiments, those skilled in the art can make changes without departing from the spirit of the present application.

[0094] In summary, the switching-capacitor amplification device and method with the gain adjustment mechanism in the present application can adjust the equivalent capacitance value of the level-shifting capacitor array according to the change of the DC gain of the amplifier, and then compensate the loop gain, by setting the level-shifting capacitor array and controlling the control circuit.

[0095] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application. Any such changes may fall within the scope of the patent protection sought by the present application, in other words, the scope of patent protection of the present application shall be subject to the claims of the present application.

Claims

1. A switching capacitor amplification device with a gain adjustment mechanism, characterized in that, The switched-capacitor amplification device comprises: an amplifier comprising an input terminal and an output terminal; a capacitor circuit corresponding to a signal input terminal and a signal output terminal, and comprising: a sampling capacitor circuit comprising two sampling input terminals and a sampling output terminal, wherein the two sampling input terminals receive an input signal from the signal input terminal for sampling to output to the input terminal of the amplifier through the sampling output terminal; a load capacitor; and a level-shifting capacitor array comprising a plurality of level-shifting capacitors; and a control circuit; wherein the load capacitor and the level-shifting capacitor array are connected to the output terminal of the amplifier to be charged first respectively according to the output of the amplifier at the output terminal, and then the level-shifting capacitor array charges the load capacitor to achieve level shifting, so that the load capacitor generates an output signal through the signal output terminal; the control circuit determines an enabled combination of the plurality of level-shifting capacitors to determine an equivalent capacitance value of the level-shifting capacitor array, and then determines a loop gain between the output signal and the input signal.

2. The switched capacitance amplification device of claim 1, wherein, The load capacitor is electrically coupled between a first connection terminal and a ground terminal, and the level-shifting capacitor array is electrically coupled between the first connection terminal and a second connection terminal, wherein the first connection terminal is also electrically coupled to the signal output terminal; in a sampling period, the first connection terminal is electrically coupled to the output terminal of the amplifier, the second connection terminal is grounded, and the two sampling input terminals are each only electrically coupled to the signal input terminal to receive the input signal for sampling, and the sampling output terminal of the sampling capacitor circuit is electrically coupled to the input terminal of the amplifier and is grounded at the same time; in a prediction period, the first connection terminal is electrically coupled to the output terminal of the amplifier, the second connection terminal is grounded, a first one of the two sampling input terminals of the sampling capacitor circuit is grounded and a second one is electrically coupled to the first connection terminal, and the sampling output terminal is electrically coupled to the input terminal of the amplifier and is not grounded, so as to feed the sampled input signal to the input terminal, and then the load capacitor and the level-shifting capacitor array are charged by the amplifier through the output terminal and the first connection terminal; and in a level-shifting period, the first one of the two sampling input terminals of the sampling capacitor circuit is grounded and the second one is electrically coupled to the first connection terminal, the sampling output terminal is electrically coupled to the input terminal of the amplifier and is not grounded, the first connection terminal is not electrically coupled to the output terminal of the amplifier, and the second connection terminal is electrically coupled to the output terminal of the amplifier, so that the level-shifting capacitor array charges the load capacitor. The switched-capacitor amplification device further comprises:

3. The switched capacitor amplification device of claim 2, wherein, a first switching unit comprising a first terminal electrically coupled to the first one of the two sampling input terminals, and a second terminal switched to be electrically coupled to the signal input terminal or the ground terminal; ​ a second switching unit including a first terminal electrically coupled to the second one of the two sampling input terminals, and a second terminal switched to be electrically coupled to the signal input terminal or the first connection terminal; a third switching unit including a first terminal electrically coupled to the sampling output terminal and the input terminal of the amplifier, and a second terminal switched to be electrically coupled to the ground terminal or electrically isolated from the ground terminal; a fourth switching unit including a first terminal electrically coupled to the first connection terminal, and a second terminal switched to be electrically coupled to the output terminal of the amplifier or electrically isolated from the output terminal of the amplifier; and a fifth switching unit including a first terminal electrically coupled to the second connection terminal, and a second terminal switched to be electrically coupled to the ground terminal or the output terminal of the amplifier. The sampling capacitor circuit further includes:

4. The switched capacitance amplification device of claim 2, wherein, a first sampling capacitor electrically coupled between the first one of the two sampling input terminals and the sampling output terminal; and a second sampling capacitor electrically coupled between the second one of the two sampling input terminals and the sampling output terminal. The level boosting capacitor array further includes a plurality of switching circuits controlled by the control circuit to be enabled or disabled, each of the plurality of switching circuits corresponding to one of the plurality of level boosting capacitors to electrically couple the one of the plurality of level boosting capacitors between the first connection terminal and the second connection terminal as an enabled capacitor when enabled, and to electrically isolate the one of the plurality of level boosting capacitors from the first connection terminal and the second connection terminal as a disabled capacitor when disabled.

5. The switched capacitor amplification device of claim 2, wherein, A DC gain of the amplifier is related to a magnitude of the loop gain and the equivalent capacitance value of the level boosting capacitor array, and the control circuit determines the enabled combination of the plurality of level boosting capacitors according to the DC gain.

6. The switched capacitance amplification device of claim 1, wherein, The control circuit determines the equivalent capacitance value to be increased when the DC gain is decreased and to be decreased when the DC gain is increased according to a gain analysis between the output terminal and the input terminal of the amplifier.

7. The switched capacitor amplification device of claim 6, wherein, The control circuit determines the enabled combination of the plurality of level boosting capacitors according to a Fourier analysis between the output terminal and the input terminal of the amplifier to determine a variation of the DC gain.

8. The switched capacitance amplification device of claim 6, wherein, The input terminal and the output terminal of the amplifier are a first input terminal and a first output terminal, respectively, and the amplifier further includes a second input terminal and a second output terminal; 9. The switched capacitor amplification device of claim 1, wherein, The switching capacitor amplifying device includes the capacitor circuit as a first capacitor circuit and corresponding signal input terminal and signal output terminal as a first signal input terminal and a first signal output terminal, respectively; The switching capacitor amplifying device further includes a second capacitor circuit having the same structure as the first capacitor circuit and corresponding to the second input terminal, the second output terminal, a second signal input terminal, and a second signal output terminal. The switching capacitor amplifying method includes:

10. A switched-capacitor amplification method with gain adjustment mechanism, applied to a switched-capacitor amplification device, characterized in that, ​ sampling, by a sampling capacitor circuit of a capacitor circuit, a sampling input terminal from a signal input terminal receiving an input signal to output to an input terminal of an amplifier through a sampling output terminal; establishing, by a load capacitor and a level-shifting capacitor array including a plurality of level-shifting capacitors, a plurality of connection relationships with the output terminal of the amplifier to charge the load capacitor to achieve level shifting by the level-shifting capacitor array after charging according to the output of the amplifier at an output terminal, respectively, to generate an output signal through a signal output terminal; and determining, by a control circuit, an enabled combination of the plurality of level-shifting capacitors to determine an equivalent capacitance value of the level-shifting capacitor array, and to determine a loop gain between the output signal and the input signal.

Images