Test system and method for reliability degradation of transistor array in radiation environment

Abstract

To address the problems of existing transistor reliability testing methods being primarily applicable to testing single devices, resulting in long test cycles and inaccurate test results due to differences in transistor annealing times during reliability degradation tests under radiation environments, the present invention provides a system and method for testing the reliability degradation of transistor arrays under radiation environments. The testing system includes a control computer, a semiconductor parameter tester connected to the control computer via a control bus, an electrical stress application device, and a matrix switch, as well as a transistor array test fixture for mounting the transistor array under test; the semiconductor parameter tester is used to measure the electrical parameters of the transistor array under test; the electrical stress application device is used to provide the required electrical stress source for the transistor array under test; each row of the matrix switch is sequentially connected to the pins of the transistor array test fixture, and each column of the matrix switch is sequentially connected to the test channels of the semiconductor parameter tester and the electrical stress application device.

Description

Technical Field

[0001] The present invention relates to a test technology for radiation effect and electric stress effect of transistors, and in particular to a test system and method for reliability degradation of a transistor array in a radiation environment. Background Art

[0002] The natural radiation environment in space can produce a cumulative effect of ionizing radiation (referred to as the total dose effect) in electronic systems or electronic devices, leading to degradation of the electrical parameters of the electronic systems or even functional failure, seriously affecting the lifespan and reliability of spacecraft and strategic weapons. Therefore, it is necessary to conduct research on the laws and mechanisms of reliability degradation of satellite electronic devices and systems in radiation environments.

[0003] Field-effect transistors (MOSFETs) are a fundamental subject of research on the mechanisms and laws of radiation effects. Research both domestically and internationally has shown that as MOSFET process dimensions reach the nanometer scale, conventional reliability effects such as charge carrier injection (HCI), negative bias temperature instability (NBTI), and time-dependent gate oxide breakdown (TDDB) intensify, leading to degradation of the device's intrinsic reliability. MOSFETs exposed to long-term space radiation environments may suffer even more severe damage due to the combined effects of radiation effects and conventional reliability degradation. However, current lifetime estimates for on-orbit electronic systems and devices fail to comprehensively consider both factors, potentially leading to premature failure of spacecraft. To address this issue, recent research has focused on the mechanisms and laws governing the interplay between radiation effects and conventional reliability in electronic devices. Testing systems that support both conventional reliability and radiation effects are fundamental to this research.

[0004] When MOSFET process sizes reached the nanometer scale, the ESD resistance of individual MOSFETs became very weak, making it difficult to package them individually for radiation effects and conventional reliability testing. Only wafer-level testing could be performed. MOSFETs were arranged in arrays on the wafer to increase the number of test samples and reduce the occupied area and tape-out costs.

[0005] This array layout will bring the following problems:

[0006] (1) When conducting reliability degradation tests, there are problems with long test cycles and low efficiency. Because the device damage caused by conventional reliability will quickly anneal after the electrical stress is removed, it is required to start measurement as soon as possible after the electrical stress is removed and to reduce the measurement time as much as possible. Therefore, most existing reliability test methods use semiconductor parameter testers to apply electrical stress to a single MOSFET and then test it. If data from N devices is required, N tests need to be carried out;

[0007] (2) When conducting reliability degradation tests in radiation environments, existing methods are not applicable. Currently, the total dose effect radiation source is global, and all MOSFETs in the array will be damaged. If the reliability degradation test of each MOSFET is carried out one by one using existing methods after radiation, the radiation effect annealing of the post-test MOSFET will result, making the test data unreliable and difficult to obtain effective test rules.

[0008] Therefore, there is an urgent need to develop a method and system for rapid reliability testing of transistor arrays in radiation environments. Summary of the Invention

[0009] The purpose of the present invention is to solve the problems that the existing transistor reliability testing method is mainly suitable for testing a single device, the test cycle is long for multiple transistors, and in the reliability degradation test under a radiation environment, the annealing time of the transistors varies, resulting in inaccurate test results or scattered test data. The present invention provides a test system and method for the reliability degradation of a transistor array under a radiation environment.

[0010] In order to achieve the above object, the technical solution adopted by the present invention is:

[0011] A test system for reliability degradation of a transistor array in a radiation environment is characterized in that it comprises a control computer, a semiconductor parameter tester, an electrical stress applying device and a matrix switch connected to the control computer via a GPIB control bus, and a transistor array test fixture for mounting the transistor array under test;

[0012] The semiconductor parameter tester is used to measure the electrical parameters of the transistor array under test; the electrical stress applying device is used to provide the required electrical stress source for the transistor array under test;

[0013] Each row of the matrix switch is sequentially connected to the pins of the transistor array test fixture, and each column of the matrix switch is sequentially connected to the test channel and electric stress applying equipment of the semiconductor parameter tester.

[0014] Furthermore, the transistor under test is a wafer-level transistor, and the transistor array test fixture is a low-leakage probe station with a probe card.

[0015] Furthermore, the electrical stress applying device is a voltage-stabilized power supply or a source meter.

[0016] The present invention also provides a method for testing reliability degradation of a transistor array in a radiation environment. The method is based on the above-mentioned system for testing reliability degradation of a transistor array in a radiation environment, and the method comprises the following steps:

[0017] Step 1) sorting the N transistors in the transistor array and determining a test method and a test sequence for measuring the electrical parameters of the transistors;

[0018] Step 2), according to the measurement method and test sequence determined in step 1), sequentially measure and record the initial electrical parameters of N transistors, as well as the time when each transistor switches to the measurement state and the measurement time; N ≥ 2, and N is a positive integer;

[0019] Step 3) Determine the magnitude of the electrical stress applied to the transistor and the first stage electrical stress application time t SILC,1 ;

[0020] Step 4), resetting the matrix switch so that all channels in the test system for transistor array reliability degradation in a radiation environment are disconnected;

[0021] Step 5) Turn on the electrical stress applying device and put it in output state; the software in the control computer automatically starts two parallel running threads: a start thread and a measurement thread;

[0022] Step 6) Start the thread

[0023] 6.1. Start the electric stress application time counter and set the timing time to the first stage electric stress application time t determined in step 3). SILC,1 ;

[0024] 6.2. Calculate the time interval t for the transistor array to switch to the electrical stress application state in sequence Δ (i) determining the time ST(i) at which the i-th transistor switches to the electrical stress application state;

[0025]

[0026] Among them, t swi1 (i) t swi1 (m) are the time taken for the i-th and m-th transistors to switch from the electrical stress application state to the test state; t test (i) t test (m) is the time required to measure the electrical parameters of the i-th and m-th transistors respectively; 2≤i≤N, and i is an integer; 1≤m≤i-1, and m is an integer;

[0027] 6.3. Switch the matrix switches in sequence according to the test sequence of the N transistors set in step 1) and the time interval t calculated in step 6.2. Δ (i) making N transistors enter the electrical stress application state in sequence;

[0028] 6.4. Until all N transistors have completed the first round of electrical stress application;

[0029] Step 7) Measure the thread

[0030] 7.1. Read the value of the electrical stress application time counter to determine whether the electrical stress application of the first transistor has been completed and whether the semiconductor parameter tester is in an idle state. If not, wait. If so, proceed to step 7.2.

[0031] Whether the first transistor has completed the electrical stress application, that is, the value of the electrical stress application time counter is greater than or equal to the first stage electrical stress application time t SILC,1 ;

[0032] 7.2. Switch the matrix switches in sequence according to the test order of the N transistors set in step 1) so that the i-th transistor is switched to the measurement state and the i-1-th transistor is in the electrical stress application state;

[0033] 7.3. Measure the electrical parameters of the N transistors in sequence using the measurement method determined in step 1);

[0034] 7.4. Until all N transistors have completed the first stage of electrical parameter measurement;

[0035] Step 8) Based on the purpose of the transistor electrical parameter degradation test, determine whether the next stage of electrical stress test is required. If so, return to step 3) and re-determine the magnitude of the electrical stress applied in the next stage and the time for applying the electrical stress in the next stage; if not, end the electrical stress test.

[0036] Furthermore, in step 6.2, the number of pins of the N transistors in the transistor array is the same, and the same electrical parameter testing method is used. The time ST(i) for the i-th transistor to switch to the electrical stress application state is:

[0037] ST(i)=(i-1)·(t swi1 +t test )

[0038] Furthermore, in step 6.3, the matrix switch is switched to put the transistor into an electrical stress application state, specifically: first, disconnecting the transistor from the measurement channel of the semiconductor parameter tester; second, connecting the transistor pin to the electrical stress application device;

[0039] In step 7.2, the matrix switch is switched to put the transistor into the measurement state, specifically: first, the connection between the transistor and the electrical stress applying device is disconnected; second, the transistor pin is connected to the measurement channel of the semiconductor parameter tester.

[0040] Furthermore, the switching of the i-th transistor to the electrical stress state in step 6.3 and the switching of the i+1-th transistor to the measurement state in step 7.2 are performed simultaneously, specifically: first, the connection between the i-th transistor and the semiconductor parameter tester is disconnected, and the connection between the i+1-th transistor and the electrical stress applying device is disconnected; secondly, the pin of the i-th transistor is connected to the corresponding channel of the electrical stress applying device, and the pin of the i+1-th transistor is connected to the measurement channel of the semiconductor parameter tester.

[0041] Furthermore, in step 8, the next stage is defined as the j-th stage, and the electric stress application time of the j-th stage satisfies:

[0042]

[0043] Wherein, j≥2, and j is an integer.

[0044] Compared with the prior art, the present invention has the following beneficial technical effects:

[0045] 1. The test system for reliability degradation of transistor arrays in radiation environments provided by the present invention addresses the problem that current MOSFET reliability performance tests can only be carried out sequentially for each test sample. A test system consisting of a control computer, a semiconductor parameter tester, an electrical stress application source, and a test fixture for the device under test is constructed. Based on this system, the principle of pipeline is adopted to achieve rapid testing of MOSFET array reliability tests, saving a large amount of test time, greatly improving test efficiency, and avoiding annealing due to electrical stress effects, laying a foundation for research on the laws and mechanisms of reliability degradation of electronic devices.

[0046] 2. The present invention's method for testing transistor array reliability degradation in radiation environments can be used for conventional transistor reliability testing and for online testing of total dose effects on electronic devices. It is particularly suitable for testing device reliability parameter degradation in radiation environments. Compared to existing methods, this method provides more accurate test results, avoids waste of test samples, and saves testing time and costs, providing technical support for evaluating the reliability degradation of electronic devices in radiation environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic structural diagram of an embodiment of a test system for reliability degradation of a transistor array in a radiation environment according to the present invention;

[0048] Figure 2 A schematic diagram of the connection mode and switch state switching of a matrix switch in a test system for reliability degradation of a transistor array under a radiation environment according to the present invention;

[0049] Figure 3A basic principle diagram of a method for testing reliability degradation of a transistor array in a radiation environment according to the present invention;

[0050] Figure 4 The figure is a flow chart of a method for testing reliability degradation of a transistor array in a radiation environment according to the present invention. DETAILED DESCRIPTION

[0051] To further clarify the objectives, advantages, and features of the present invention, the following describes in further detail a system and method for testing reliability degradation of a transistor array in a radiation environment, as proposed by the present invention, with reference to the accompanying drawings and specific embodiments. Those skilled in the art should understand that these embodiments are intended only to illustrate the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0052] like Figure 1 As shown, the test system for reliability degradation of a transistor array in a radiation environment proposed in this embodiment includes a control computer, a semiconductor parameter tester, an electrical stress applying device and a matrix switch connected to the control computer via a GPIB control bus, and a test fixture for the transistor (MOSFET) array under test.

[0053] Semiconductor parameter testers are used to measure IV curves and electrical parameters of the MOSFET array under test. Electrical stress application equipment, such as a regulated power supply and source / meter instrument, provides the necessary electrical stress for the MOSFET array under test. The MOSFET test fixture is used to mount the MOSFET array under test. For wafer-level test samples, a low-leakage probe station with a probe card can be used.

[0054] The matrix switch is a 14-column, 48-row matrix switch. Columns 1 to 6 are connected to the semiconductor parameter tester, and the other columns are connected to the electrical stress application equipment. They can be connected as needed and left idle. The 48 rows of the matrix switch are connected to the MOSFET array under test through the probe card on the low-leakage probe station. The connection method is as follows: Figure 2 shown.

[0055] like Figure 3 As shown, the basic principle of using the above-mentioned transistor array reliability degradation test system in a radiation environment to perform a rapid test on the reliability degradation of a transistor array is as follows: when the semiconductor parameter tester measures the electrical parameters of the first MOSFET in the array, ensure that N-1 MOSFETs in the array are in an electrical stress state applied by the electrical stress application device, wait for the electrical parameter measurement of the first MOSFET to be completed, control the matrix switch to put the first MOSFET into the electrical stress state, and at the same time, connect the second MOSFET to the measurement channel of the semiconductor parameter tester, and then perform electrical parameter measurement on the second MOSFET; and so on, until the reliability degradation test of all MOSFETs is completed.

[0056] like Figure 4 As shown, the test method for reliability degradation of a transistor array in a radiation environment specifically includes the following steps:

[0057] Step 1) sorting the N MOSFETs in the MOSFET array and determining a method for measuring the electrical parameters of the MOSFETs and a test sequence;

[0058] Based on user needs, determine the type of electrical parameters of concern and their corresponding test methods. Common transistor test methods are applicable.

[0059] Step 2), according to the measurement method and test sequence determined in step 1), sequentially measure and record the initial electrical parameters of the N MOSFETs, as well as the time when each MOSFET switches to the measurement state and the measurement time;

[0060] Step 3) Determine the magnitude of the electrical stress applied to the MOSFET and the first stage electrical stress application time t SILC,1 ;

[0061] The magnitude of the electrical stress and the first-stage electrical stress application time are determined based on user requirements, transistor characteristics, and test objectives. Generally, the magnitude of the electrical stress is inversely proportional to the electrical stress application time.

[0062] Step 4), resetting the matrix switch so that all channels in the test system for reliability degradation of the MOSFET array in a radiation environment are disconnected;

[0063] Step 5) Turn on the electrical stress applying device and put it in output state; the software in the control computer automatically starts two parallel running threads: a start thread and a measurement thread;

[0064] Step 6) Start the thread

[0065] 6.1. Start the electric stress application time counter and set the timing time to the first stage electric stress application time t determined in step 3). SILC,1 ;

[0066] 6.2. Calculate the time interval t for the MOSFET array to switch to the electrical stress application state in sequence Δ (i);

[0067] t Δ (i) = t swi1 (i)+t test (i)

[0068] Among them, t swi1 (i) is the time it takes for the i-th MOSFET to switch from the electrical stress application state to the test state; t test(i) is the time required to measure the electrical parameters of the i-th MOSFET; 2≤i≤N, and i is an integer;

[0069] In order to ensure that the electrical stress application time of each MOSFET is exactly the same, the time when each MOSFET starts to apply electrical stress should be different. If the electrical stress start time of the first MOSFET is zero, the time when the i-th MOSFET starts to apply electrical stress is:

[0070]

[0071] Where 1≤m≤i-1, and m is an integer; when all MOSFETs in the array have the same number of pins and the same test method, the t of each MOSFET is swi1 and t test are the same, so we have:

[0072] ST(i)=(i-1)·(t swi1 +t test )

[0073] 6.3. Switch the matrix switches in sequence according to the test sequence of the N MOSFETs set in step 1) and the time interval t calculated in step 6.2. Δ (i) making N MOSFETs enter the electrical stress application state in sequence;

[0074] 6.4. Until all N MOSFETs have completed the first round of electrical stress application;

[0075] Step 7) Measure the thread

[0076] 7.1. Read the value of the electrical stress application time counter to determine whether the electrical stress application of the first MOSFET has been completed and whether the semiconductor parameter tester is in an idle state. If not, wait. If so, proceed to step 7.2.

[0077] Whether the first MOSFET has completed the electrical stress application, that is, the value of the electrical stress application time counter is greater than or equal to the first stage electrical stress application time t SILC,1 ;

[0078] 7.2. Switch the matrix switches in sequence according to the test order of the N MOSFETs set in step 1) so that the i-th MOSFET is switched to the measurement state and the i-1-th MOSFET is in the electrical stress application state;

[0079] 7.3. Measure the electrical parameters of N MOSFETs in sequence using the measurement method determined in step 1);

[0080] 7.4. Until all N MOSFETs have completed the first stage of electrical parameter measurement;

[0081] Step 8) According to the purpose of the transistor electrical parameter degradation test, determine whether to continue the next stage of electrical stress test. If so, return to step 3) to re-determine the magnitude of the electrical stress applied in the next stage and the time for applying the electrical stress in the next stage; if not, end the electrical stress test.

[0082] Based on the actual test data, test personnel will determine whether to proceed to the next stage of electrical stress testing, depending on the amount of transistor reliability degradation, test requirements, and other related requirements. Current transistor reliability degradation testing methods primarily modify the external environment to apply electrical stress to the device, accelerating the growth of defects within the device and thereby evaluating device reliability.

[0083] The following issues should be noted when implementing the fast test method for transistor arrays:

[0084] (1) Except for the first stage of electrical stress application, the electrical stress application time in other stages should meet the following requirements:

[0085]

[0086] When all MOSFETs are measured in the same way, it can be expressed as:

[0087] T SILC,j >(N-1)·(t swi1 +t test )

[0088] (2) To ensure the safety of MOSFET devices, when the MOSFET device is switched to the test state, the switching of the matrix switch should be performed in the following two steps: ① disconnect the device from the electrical stress application equipment; ② connect the device pins to the measurement channel of the semiconductor parameter tester;

[0089] (3) To ensure the safety of the MOSFET instrument, when the MOSFET device is switched to the electrical stress state, the switching of the matrix switch should be performed in the following two steps: ① disconnect the connection between the device and the semiconductor parameter tester; ② connect the device pins to the corresponding channels of the electrical stress application equipment;

[0090] (4) In order to reduce the total measurement time, the switching of the i-th MOSFET to the electrical stress state can be carried out simultaneously with the switching of the i+1-th MOSFET to the test state. At this time, the switching of the matrix switch should be performed in the following two-step sequence: ① Disconnect the connection between device i and the semiconductor parameter tester, and disconnect the connection between device i+1 and the electrical stress application equipment; ② Connect the pin of device i to the corresponding channel of the electrical stress application equipment, and connect the pin of device i+1 to the measurement channel of the semiconductor parameter tester.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A method for testing the reliability degradation of a transistor array in a radiation environment, based on a test system comprising a control computer, a semiconductor parameter tester, an electrical stress applying device, and a matrix switch connected to the control computer via a GPIB control bus, and a transistor array test fixture for mounting the transistor array under test; The semiconductor parameter tester is used to measure the electrical parameters of the transistor array under test; the electrical stress applying device is used to provide the required electrical stress source for the transistor array under test; each row of the matrix switch is sequentially connected to the pins of the transistor array test fixture, and each column of the matrix switch is sequentially connected to the test channel of the semiconductor parameter tester and the electrical stress applying device; characterized in that The following steps are involved: Step 1) sorting the N transistors in the transistor array and determining a test method and a test sequence for measuring the electrical parameters of the transistors; Step 2), according to the measurement method and test sequence determined in step 1), the initial electrical parameters of the N transistors, as well as the time when each transistor switches to the measurement state and the measurement time are measured and recorded in sequence; N ≥ 2, and N is a positive integer; Step 3) Determine the magnitude of the electrical stress applied to the transistor and the first stage electrical stress application time t SILC,1 ; Step 4), resetting the matrix switch so that all channels in the test system for transistor array reliability degradation in a radiation environment are disconnected; Step 5) Turn on the electrical stress applying device and put it in output state; the software in the control computer automatically starts two parallel running threads: a start thread and a measurement thread; Step 6) Start the thread 6.

1. Start the electric stress application time counter and set the timing time to the first stage electric stress application time t determined in step 3). SILC,1 ; 6.

2. Calculate the time interval t for the transistor array to switch to the electrical stress application state in sequence Δ (i) determining the time ST(i) at which the i-th transistor switches to the electrical stress application state; Among them, t swi1 (i) t swi1 (m) are the time taken for the i-th and m-th transistors to switch from the electrical stress application state to the test state; t test (i) t test (m) is the time required to measure the electrical parameters of the i-th and m-th transistors respectively; 2≤i≤N, and i is an integer; 1≤m≤i-1, and m is an integer; 6.

3. Switch the matrix switches in sequence according to the test sequence of the N transistors set in step 1) and the time interval t calculated in step 6.

2. Δ (i) making N transistors enter the electrical stress application state in sequence; 6.

4. Until all N transistors have completed the first round of electrical stress application; Step 7) Measure the thread 7.

1. Read the value of the electrical stress application time counter to determine whether the electrical stress application of the first transistor has been completed and whether the semiconductor parameter tester is in an idle state. If not, wait. If so, proceed to step 7.

2. Whether the first transistor has completed the electrical stress application, that is, the value of the electrical stress application time counter is greater than or equal to the first stage electrical stress application time t SILC,1 ; 7.

2. Switch the matrix switches in sequence according to the test order of the N transistors set in step 1) so that the i-th transistor is switched to the measurement state and the i-1-th transistor is in the electrical stress application state; 7.

3. Measure the electrical parameters of the N transistors in sequence using the measurement method determined in step 1); 7.

4. Until all N transistors have completed the first stage of electrical parameter measurement; Step 8) Based on the purpose of the transistor electrical parameter degradation test, determine whether the next stage of electrical stress test is required. If so, return to step 3) and re-determine the magnitude of the electrical stress applied in the next stage and the time for applying the electrical stress in the next stage; if not, end the electrical stress test.

2. The method for testing reliability degradation of a transistor array in a radiation environment according to claim 1, wherein: In step 6.2, the number of pins of the N transistors in the transistor array is the same, and the same electrical parameter test method is used. The time ST(i) for the i-th transistor to switch to the electrical stress application state is: ST(i)=(i-1)·(t swi1 +t test )。 3. The method for testing reliability degradation of a transistor array under a radiation environment according to claim 2, wherein: In step 6.3, the matrix switch is switched to put the transistor into the electrical stress application state, specifically: first, disconnect the transistor from the measurement channel of the semiconductor parameter tester; second, connect the transistor pin to the electrical stress application device; In step 7.2, the matrix switch is switched to put the transistor into the measurement state, specifically: first, the connection between the transistor and the electrical stress applying device is disconnected; second, the transistor pin is connected to the measurement channel of the semiconductor parameter tester.

4. The method for testing reliability degradation of a transistor array under a radiation environment according to claim 3, wherein: The switching of the i-th transistor to the electrical stress state in step 6.3 and the switching of the i+1-th transistor to the measurement state in step 7.2 are performed simultaneously. Specifically, first, the connection between the i-th transistor and the semiconductor parameter tester is disconnected, and the connection between the i+1-th transistor and the electrical stress applying device is disconnected; second, the pin of the i-th transistor is connected to the corresponding channel of the electrical stress applying device, and the pin of the i+1-th transistor is connected to the measurement channel of the semiconductor parameter tester.

5. The method for testing reliability degradation of a transistor array in a radiation environment according to any one of claims 1 to 4, wherein: In step 8, the next stage is defined as the j-th stage, and the electric stress application time of the j-th stage satisfies: Wherein, j≥2, and j is an integer.

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