Bias circuits that implement currents with various temperature characteristics

Abstract

A bias circuit for realizing various temperature characteristic currents is provided by connecting a high temperature adjustment unit and a low temperature adjustment unit in parallel to the bias unit respectively. The high temperature adjustment unit and the low temperature adjustment unit share a bias voltage circuit, and temperature compensation can be performed, which is beneficial for realizing zero-temperature bias current on the bias circuit with a circuit of smaller area, and is also beneficial for realizing currents with various temperature characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of bias circuits, and in particular to a bias circuit for realizing currents with various temperature characteristics. A high temperature adjustment unit and a low temperature adjustment unit are respectively connected in parallel to the bias unit. The high temperature adjustment unit and the low temperature adjustment unit share a bias voltage circuit, so that temperature compensation can be performed, which is beneficial for realizing a zero-temperature bias current on the bias circuit with a circuit of a smaller area, and is also beneficial for realizing currents with various temperature characteristics. Background Art

[0002] In analog circuits, most bias circuits are constructed using delta (V GS ) / R, where delta(V GS ) refers to the difference between the gate-source voltage of two common-gate NMOS tubes (V GS1 -V GS2 ), R is a resistor, usually a high resistance with a negative temperature characteristic. The current generated by this structure (i.e., the bias current I bias ) is not affected by the power supply VCC, but is greatly affected by the temperature T, and cannot directly provide current to some circuits with precision requirements. For this reason, the prior art generally divides the resistor R into multiple resistors for proportional adjustment, some of which have positive temperature characteristics. For example, Figure 3 The zero temperature characteristic bias unit structure in the prior art represented by the embodiment includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5 whose gates are interconnected, the sources of Mp4 and Mp5 are interconnected and connected to the power supply voltage terminal VCC, the gate and drain of Mp5 are interconnected and connected to the drain of the second NMOS tube Mn2, the source of Mn2 is grounded through a first resistor R1 and a second resistor R2 connected in series, the drain of Mp4 is respectively connected to the drain and the gate of the first NMOS tube Mn1, the gates of Mn1 and Mn2 are interconnected, the source of Mn1 is grounded, the current IMp5 flowing through Mp5 and the current I flowing through Mp4 are mp4 The same size, both 2I. Figure 3 In the example, the original resistor R is replaced by the first resistor R1 and the second resistor R2 connected in series, where R2 is a low resistance with a positive temperature characteristic, which changes the temperature characteristic of the entire R=R1+R2 to positive and can follow V GS1 -V GS2 Changes in V GS1 is the gate-source voltage of Mn1, V GS2 is the gate-source voltage of Mn2), then the current I generated by the bias circuit bias (i.e. I Mp2 ) is the zero temperature characteristic, but the cost is that the chip area will become much larger, because the low resistance area is too large, especially the low power circuit requires more resistors. Summary of the invention

[0003] In view of the defects or shortcomings in the prior art, the present invention provides a bias circuit for realizing various temperature characteristic currents. By connecting a high temperature adjustment unit and a low temperature adjustment unit in parallel to the bias unit respectively, the high temperature adjustment unit and the low temperature adjustment unit share a bias voltage circuit, which can perform temperature compensation, is conducive to realizing zero-temperature bias current on the bias circuit with a circuit of smaller area, and is also conducive to realizing currents with various temperature characteristics.

[0004] The technical solution of the present invention is as follows:

[0005] A bias circuit for realizing various temperature characteristic currents is characterized in that it comprises a high temperature adjustment unit and a low temperature adjustment unit respectively connected in parallel to a bias unit.

[0006] The high temperature trimming unit and the low temperature trimming unit share a bias voltage circuit.

[0007] The bias unit includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5 whose gates are interconnected. The sources of Mp4 and Mp5 are interconnected and connected to the power supply voltage terminal VCC. The gate and drain of Mp5 are interconnected and connected to the drain of the second NMOS tube Mn2. The source of Mn2 is grounded through a resistor R. The drain of Mp4 is respectively connected to the drain and gate of the first NMOS tube Mn1. The gates of Mn1 and Mn2 are interconnected, and the source of Mn1 is grounded.

[0008] The high temperature adjustment unit and the low temperature adjustment unit are respectively connected in parallel with Mp4. If the current flowing through Mp4 is I, the current flowing through Mp5 is 2I.

[0009] The high temperature adjustment unit includes a third PMOS tube Mp3, the source of which is connected to VCC, the gates of Mp3 and Mp4 are interconnected, the drain of Mp3 is respectively connected to the source of the eighth PMOS tube Mp8 and the source of the ninth PMOS tube Mp9, the gate of Mp9 is connected to the positive reference voltage Vpt terminal, the Mp9 is interconnected to the drain of Mp4, the gate of Mp8 is connected to the bias voltage Vbe terminal, and the drain of Mp8 is grounded.

[0010] The low temperature adjustment unit includes a first PMOS tube Mp1, the source of Mp1 is connected to VCC, the gates of Mp1 and Mp4 are interconnected, the drain of Mp1 is respectively connected to the source of the sixth PMOS tube Mp6 and the source of the seventh PMOS tube Mp7, the gate of Mp6 is connected to the negative reference voltage Vnt terminal, the drain of Mp6 and Mp4 are interconnected, the gate of Mp7 is connected to the bias voltage Vbe terminal, and the drain of Mp7 is grounded.

[0011] The bias voltage circuit includes a second PMOS tube Mp2, the source of Mp2 is connected to VCC, the gates of Mp2 and Mp4 are interconnected, the drain of Mp2 is connected to the bias voltage Vbe terminal, the Vbe terminal is respectively connected to the collector and base of the NPN triode BJT, and the emitter of the BJT is grounded.

[0012] The Vbe has a negative temperature characteristic.

[0013] The technical effects of the present invention are as follows: the present invention realizes a bias circuit of various temperature characteristic currents, and realizes the zero-temperature characteristic of the bias current Ibias of the bias unit by means of a compensation structure of a high-temperature adjustment unit and a low-temperature adjustment unit respectively connected in parallel to the bias unit. The advantage is that the structure is simple, and not only can the desired zero-temperature characteristic current be realized, but also current curves with different temperature characteristics can be realized, and the flexibility is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The present invention is a schematic diagram of a bias circuit structure for realizing various temperature characteristic currents. Figure 1 It includes a right bias unit, a middle high temperature adjustment unit, and a left low temperature adjustment unit. The middle high temperature adjustment unit and the left low temperature adjustment unit share a bias voltage circuit, and the bias voltage circuit includes Mp2 and BJT; the right bias unit includes Mp4, Mp5, Mn1, Mn2, R; the middle high temperature adjustment unit includes Mp3, Mp8, Mp9; the left low temperature adjustment unit includes Mp1, Mp6, Mp7.

[0015] Figure 2 yes Figure 1 Schematic diagram of the changing relationship between the bias voltage Vbe, the negative reference voltage Vnt, the positive reference voltage Vpt and the temperature. Figure 2 The ordinate is voltage V, and the abscissa is temperature T.

[0016] Figure 3 It is a schematic diagram of the structure of a zero temperature characteristic bias unit in the prior art.

[0017] The reference numerals are listed as follows: VCC-power supply voltage terminal; I-current; 2I-2 times current (i.e., set bias current or stable bias reference current); Vbe-bias voltage; Vnt-negative reference voltage; Vpt-positive reference voltage; BJT-NPN transistor (BJT, Bipolar Junction Transistor); Mp1~Mp9-first PMOS tube to ninth PMOS tube; Mn1~Mn2-first NMOS tube to second NMOS tube; R1~R2-first resistor to second resistor; R-resistance (negative temperature characteristic high resistance). DETAILED DESCRIPTION

[0018] Below is the attached figure ( Figure 1-Figure 2 ) and Examples illustrate the present invention.

[0019] Figure 1 The present invention is a schematic diagram of a bias circuit structure for realizing various temperature characteristic currents. Figure 2 yes Figure 1 Schematic diagram of the relationship between the bias voltage Vbe, negative reference voltage Vnt, positive reference voltage Vpt and temperature. Figure 1 to Figure 2 As shown, a bias circuit for realizing various temperature characteristic currents includes a high temperature adjustment unit and a low temperature adjustment unit respectively connected in parallel to the bias unit. The high temperature adjustment unit and the low temperature adjustment unit share a bias voltage circuit. The bias unit includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5 whose gates are interconnected, the sources of Mp4 and Mp5 are interconnected and connected to the power supply voltage terminal VCC, the gate and drain of Mp5 are interconnected and connected to the drain of the second NMOS tube Mn2, the source of Mn2 is grounded through a resistor R, the drain of Mp4 is respectively connected to the drain and gate of the first NMOS tube Mn1, the gates of Mn1 and Mn2 are interconnected, and the source of Mn1 is grounded.

[0020] The high temperature trimming unit and the low temperature trimming unit are respectively connected in parallel with Mp4. If the current flowing through Mp4 is I, the current flowing through Mp5 is 2I. The high temperature trimming unit includes a third PMOS tube Mp3, the source of Mp3 is connected to VCC, the gates of Mp3 and Mp4 are interconnected, the drain of Mp3 is respectively connected to the source of the eighth PMOS tube Mp8 and the source of the ninth PMOS tube Mp9, the gate of Mp9 is connected to the positive reference voltage Vpt terminal, the Mp9 is interconnected to the drain of Mp4, the gate of Mp8 is connected to the bias voltage Vbe terminal, and the drain of Mp8 is grounded. The low temperature adjustment unit includes a first PMOS tube Mp1, the source of Mp1 is connected to VCC, the gate of Mp1 is interconnected with the gate of Mp4, the drain of Mp1 is respectively connected to the source of the sixth PMOS tube Mp6 and the source of the seventh PMOS tube Mp7, the gate of Mp6 is connected to the negative reference voltage Vnt terminal, the drain of Mp6 and Mp4 are interconnected, the gate of Mp7 is connected to the bias voltage Vbe terminal, and the drain of Mp7 is grounded. The bias voltage circuit includes a second PMOS tube Mp2, the source of Mp2 is connected to VCC, the gate of Mp2 is interconnected with the gate of Mp4, the drain of Mp2 is connected to the bias voltage Vbe terminal, the Vbe terminal is respectively connected to the collector and base of the NPN triode BJT, and the emitter of the BJT is grounded. The Vbe is a negative temperature characteristic.

[0021] The present invention introduces temperature compensation and realizes zero-temperature current on the bias circuit with a circuit of smaller area. In addition to zero temperature, currents with various temperature characteristics can also be realized.

[0022] The bias unit in the present invention is a normal bias circuit, and the left side is the low temperature and high temperature adjustment unit of the bias circuit. The principle is as follows: I Mp5 =I bias =(V GS1 -V GS2 ) / R, at low temperature, V GS1 The current becomes larger, so I bias becomes larger; at high temperature, V GS1 The current becomes smaller, so that I bias Become smaller, so I bias The temperature characteristics of the normal bias circuit I Mp4 and I Mp5 The current of Mp4 is the same. For high temperature adjustment, the current I of Mp4 is set to half of the current 2I of Mp5. The current source Mp2 flows through the BJT transistor, V be Negative temperature characteristic, V nt and V pt There are two potentials in the circuit. Choose the reference Figure 2 , Mp1 and Mp3 are tail current sources for trimming, Mp6 and Mp7 are comparison input pairs for low temperature trimming, and Mp8 and Mp9 are comparison input pairs for high temperature trimming.

[0023] At room temperature, Vpt is less than Vbe, I Mp3 The current flows into Mn1 through Mp9. The current of Mn1 is 2I, which is the same as that of Mn2. At this time, it is normal I bias .

[0024] At low temperatures, Vpt is smaller than Vbe, so I Mp3 The current still flows into Mn1. At this time, Vnt is less than Vbe, I Mp1 Most of the current flows into Mn1 through Mp6, so the current of Mn1 is greater than 2I, V GS1 Get bigger, I bias Get bigger.

[0025] At high temperature, Vpt is greater than Vbe, I Mp3 A small amount of current flows into Mn1, Vnt is greater than Vbe, I Mp1 The current flowing into Mn1 is zero, so the current flowing into Mn1 is less than 2I, V GS1 Get smaller, I bias Become smaller.

[0026] The present invention utilizes the compensation structure to achieve I biasThe zero-temperature characteristic has the advantage of a simple structure. It can not only achieve the desired zero-temperature characteristic current, but also achieve current curves with different temperature characteristics, with high flexibility.

[0027] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in the field. It is pointed out here that the above description helps those skilled in the art to understand the invention, but does not limit the protection scope of the invention. Any equivalent replacement, modification and / or simplification of the above description without departing from the essence of the invention falls within the protection scope of the invention.

Claims

1. A bias circuit for realizing various temperature characteristic currents, characterized in that: It includes a high temperature trimming unit and a low temperature trimming unit respectively connected in parallel to the bias unit; The high temperature trimming unit and the low temperature trimming unit share a bias voltage circuit; The bias unit includes a fourth PMOS tube Mp4 and a fifth PMOS tube Mp5 whose gates are interconnected, the source of Mp4 and the source of Mp5 are interconnected and connected to the power supply voltage terminal VCC, the gate and drain of Mp5 are interconnected and connected to the drain of the second NMOS tube Mn2, the source of Mn2 is grounded through a resistor R, the drain of Mp4 is respectively connected to the drain and gate of the first NMOS tube Mn1, the gate of Mn1 and the gate of Mn2 are interconnected, and the source of Mn1 is grounded; The high temperature adjustment unit and the low temperature adjustment unit are respectively connected in parallel with Mp4. If the current flowing through Mp4 is I, the current flowing through Mp5 is 2I. The high temperature trimming unit includes a third PMOS tube Mp3, the source of Mp3 is connected to VCC, the gate of Mp3 is interconnected with the gate of Mp4, the drain of Mp3 is respectively connected to the source of the eighth PMOS tube Mp8 and the source of the ninth PMOS tube Mp9, the gate of Mp9 is connected to the positive reference voltage Vpt terminal, the drain of Mp9 is interconnected with the drain of Mp4, the gate of Mp8 is connected to the bias voltage Vbe terminal, and the drain of Mp8 is grounded; The low temperature trimming unit comprises a first PMOS tube Mp1, the source of Mp1 is connected to VCC, the gate of Mp1 is interconnected with the gate of Mp4, the drain of Mp1 is respectively connected to the source of the sixth PMOS tube Mp6 and the source of the seventh PMOS tube Mp7, the gate of Mp6 is connected to the negative reference voltage Vnt terminal, the drain of Mp6 is interconnected with the drain of Mp4, the gate of Mp7 is connected to the bias voltage Vbe terminal, and the drain of Mp7 is grounded; The bias voltage circuit includes a second PMOS tube Mp2, the source of Mp2 is connected to VCC, the gate of Mp2 is interconnected with the gate of Mp4, the drain of Mp2 is connected to the bias voltage Vbe terminal, the Vbe terminal is respectively connected to the collector and base of the NPN triode BJT, and the emitter of the BJT is grounded.

2. The bias circuit for realizing various temperature characteristic currents according to claim 1, characterized in that: The Vbe has a negative temperature characteristic.

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