A power supply device, method, equipment, system and medium

Abstract

The present application discloses a power supply device, method, equipment, system and medium, which relates to the field of computer technology. The device includes a plurality of PSUs, an OR gate, a plurality of single-stage power supply circuits, and a BMC. Multiple input ends of the OR gate are respectively connected to the first output end and the second output end of each PSU, and are used for receiving a first signal indicating that the input end, the first output end, and the second output end of the PSU are in a normal working state, and a second signal indicating that the input end of the PSU is in a normal working state while the first output end and the second output end are in an abnormal working state; the input end of each single-stage power supply circuit is connected to the output end of the OR gate, and is used for controlling the working state of the BMC according to the control signal obtained from the output end of the OR gate, which represents the working state of the BMC; the output end of each single-stage power supply circuit serves as the input end of the next-level single-stage power supply circuit. The control signal determined by the first signal and the second signal is input into each single-stage power supply circuit to realize power-on or power-off step by step, thereby enhancing the state stability of the BMC.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a power supply device, method, equipment, system, and medium. Background Art

[0002] Currently, the architecture of domestic servers generally uses a Baseboard Management Controller (BMC) to monitor and manage the system. The power-on and power-off of the BMC are generally set through ASTxxx series chips. With the continuous upgrade of servers, the ASTxxx series of chips have evolved from AST2400 (mostly used in the Intel Purley platform), AST2500 (mostly used in the Intel Whitley platform) to the current latest AST2600 model. In this application, the AST2600 chip can be referred to as a VR chip in essence. When using the AST2600 chip to control the power-on and power-off of the BMC, the power-on and power-off methods of the AST2500 chip are followed. Among them, the power-on and power-off methods of the AST2500 chip are generally divided into two types: Power On Sequence and Power Off Sequence. Among them, the timing sequence of the ASTxxx series of chips powered on by Power On Sequence is generally: high voltage, low voltage, clock, reset, etc. The power-off timing of the ASTxxx series of chips represented by Power Off Sequence is generally not set. However, when powering off with the timing of Power Off Sequence, due to the absence of a specific power-off timing, the high voltage and low voltage will be powered off in a disorderly manner, resulting in an unstable state of the BMC.

[0003] In view of the above problems, seeking how to enhance the stability of the BMC state is a problem that those skilled in the art are striving to solve. Summary of the Invention

[0004] The purpose of this application is to provide a power supply device, method, equipment, system, and medium for enhancing the stability of the BMC state.

[0005] To solve the above technical problems, this application provides a power supply device, including: multiple PSUs, an OR gate, multiple single-stage power supply circuits, and a BMC;

[0006] The multiple input terminals of the OR gate are connected to the first output terminal of each PSU and the second output terminal of each PSU, and are used to receive a first signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU are all in a normal working state, and a second signal indicating that the input terminal of the PSU is in a normal working state and the first output terminal and the second output terminal of the PSU are in an abnormal working state; the input terminal of each single-stage power supply circuit is connected to the output terminal of the OR gate, and is used to control the working state of the BMC according to the control signal obtained from the output terminal of the OR gate indicating the working state of the BMC; the output terminal of each single-stage power supply circuit serves as the input terminal of the next single-stage power supply circuit.

[0007] Preferably, the single-stage power supply circuit includes: at least three VR chips with unequal voltages, an AND gate, a low-enable tri-state gate, and a pull-up power supply;

[0008] The first input terminal of the low-enable tri-state gate serves as the input terminal of the single-stage power supply circuit, the second input terminal of the low-enable tri-state gate is connected to one end of the first VR chip, the output terminal of the low-enable tri-state gate is connected to the first input terminal of the AND gate, the pull-up power supply is connected to the common terminal formed by the output terminal of the low-enable tri-state gate and the first input terminal of the AND gate, one end of the second VR chip is connected to the second input terminal of the AND gate, and the output terminal of the AND gate is connected to one end of the third VR chip, where the other end of the third VR chip serves as the output terminal of the single-stage power supply circuit.

[0009] Preferably, it further includes: a plurality of high-enable tri-state gates;

[0010] The first input terminal of the high-enable tri-state gate is connected to the first output terminal of the PSU; the second input terminal of the high-enable tri-state gate is connected to the second output terminal of the PSU; the output terminals of each high-enable tri-state gate are connected to the multiple input terminals of the OR gate; and the number of PSUs is equal to the number of high-enable tri-state gates.

[0011] To solve the above technical problems, the present application provides a power supply method, including:

[0012] Collect the first signal of the first output terminal of the PSU and the second signal of the second output terminal of the PSU, and transmit the first signal and the second signal to the multiple input terminals of the OR gate, where the first signal is a signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU are all in a normal working state, and the second signal is a second signal indicating that the input terminal of the PSU is in a normal working state and the first output terminal and the second output terminal of the PSU are in an abnormal working state;

[0013] Obtain a control signal through the output terminal of the OR gate, where the control signal is a signal indicating the working state of controlling the BMC;

[0014] Transmit the control signal to multiple single-stage power supply circuits to control the working state of the BMC.

[0015] Preferably, after collecting the first signal at the first output terminal of the PSU and the second signal at the second output terminal of the PSU, and before obtaining the control signal at the output terminal of the OR gate, it further includes:

[0016] Taking the logic of the high-enabled tri-state gate as a condition, generating a third signal representing the working state of the PSU according to the first signal and the second signal.

[0017] Preferably, after transmitting the control signal to multiple single-stage power supply circuits, it further includes:

[0018] Taking the logic of the low-enabled tri-state gate as a condition, generating a first level signal according to the control signal and the first state signal representing the first VR chip output from one end of the first VR chip in the single-stage power supply circuit;

[0019] Taking the logic of the AND gate as a condition, generating a second level signal according to the first level signal and the second state signal representing the second VR chip output from one end of the second VR chip in the single-stage power supply circuit;

[0020] Controlling the working state of the third VR chip in the single-stage power supply circuit according to the second level signal, and generating a third state signal representing the third VR chip, where the working states of the VR chips are powered-on states or powered-off states respectively.

[0021] Preferably, after generating the third state signal representing the third VR chip, it further includes:

[0022] When all VR chips in all single-stage power supply circuits are in the powered-on state or the powered-off state, outputting a prompt message.

[0023] To solve the above technical problems, the present application provides a power supply device, including:

[0024] A collection module, configured to collect the first signal at the first output terminal of the PSU and the second signal at the second output terminal of the PSU, and transmit the first signal and the second signal to multiple input terminals of the OR gate, where the first signal is a signal representing that the input terminal, the first output terminal, and the second output terminal of the PSU are all in normal working states, and the second signal is a second signal representing that the input terminal of the PSU is in a normal working state and the first output terminal and the second output terminal of the PSU are in abnormal working states;

[0025] An acquisition module, configured to obtain a control signal through the output terminal of the OR gate, where the control signal is a signal representing the working state of the control BMC;

[0026] A transmission module, configured to transmit the control signal to multiple single-stage power supply circuits to control the working state of the BMC.

[0027] In addition, the device further includes the following modules:

[0028] After collecting the first signal at the first output terminal of the PSU and the second signal at the second output terminal of the PSU, and before obtaining the control signal at the output terminal of the OR gate, it further includes:

[0029] A first generation module, configured to generate a third signal representing the working state of the PSU based on the first signal and the second signal, with the logic of a high-enabled tri-state gate as a condition.

[0030] Preferably, after transmitting the control signal to multiple single-stage power supply circuits, it further includes:

[0031] A second generation module, configured to generate a first level signal based on the control signal and a first status signal representing the first VR chip output from one end of the first VR chip in the single-stage power supply circuit, with the logic of a low-enabled tri-state gate as a condition;

[0032] A third generation module, configured to generate a second level signal based on the first level signal and a second status signal representing the second VR chip output from one end of the second VR chip in the single-stage power supply circuit, with the logic of an AND gate as a condition;

[0033] A fourth generation module, configured to control the working state of the third VR chip in the single-stage power supply circuit based on the second level signal and generate a third status signal representing the third VR chip, where the working states of the VR chips are powered-on states or powered-off states respectively.

[0034] Preferably, after generating the third status signal representing the third VR chip, it further includes:

[0035] An output module, configured to output a prompt message when all the VR chips in all the single-stage power supply circuits are in the powered-on state or the powered-off state.

[0036] To solve the above technical problems, the present application provides a power supply system, including:

[0037] A memory, configured to store a computer program;

[0038] A processor, configured to implement the steps of the power supply method when executing the computer program.

[0039] To solve the above technical problems, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the power supply method.

[0040] A power supply device provided by the present application includes: a plurality of PSUs, an OR gate, a plurality of single-stage power supply circuits, and a BMC. Multiple input terminals of the OR gate are connected to the first output terminal and the second output terminal of each PSU, and are used to receive a first signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU are all in a normal operating state, and a second signal indicating that the input terminal of the PSU is in a normal operating state and the first output terminal and the second output terminal of the PSU are in an abnormal operating state; the input terminal of each single-stage power supply circuit is connected to the output terminal of the OR gate, and is used to control the operating state of the BMC according to a control signal obtained from the output terminal of the OR gate, which indicates the operating state of the BMC; the output terminal of each single-stage power supply circuit serves as the input terminal of the next-stage single-stage power supply circuit. The control signal is determined by the first signal and the second signal of multiple PSUs, and the control signal is input into each single-stage power supply circuit to realize power-on or power-off step by step, further enhancing the stability of the BMC state.

[0041] The present application also provides a power supply method, which is applied to power supply devices, systems, and media, and has the same effect. Description of the Drawings

[0042] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a power-off schematic diagram of the VR chip provided in this embodiment;

[0044] Figure 2 It is a structural diagram of a power supply device provided in this embodiment;

[0045] Figure 3 It is a structural diagram of another power supply device provided in this embodiment;

[0046] Figure 4 It is a circuit diagram of a single-stage power supply circuit provided in this embodiment;

[0047] Figure 5 It is a circuit diagram of a single-stage power supply circuit of P1V8 provided in this embodiment;

[0048] Figure 6 It is a circuit diagram of a single-stage power supply circuit of P3V3 provided in this embodiment;

[0049] Figure 7 It is a circuit diagram of a single-stage power supply circuit of P2V5 provided in this embodiment;

[0050] Figure 8The circuit diagram of the single-stage power supply circuit of P1V2 provided by this embodiment;

[0051] Figure 9 The circuit diagram of the single-stage power supply circuit of P1V0 provided by this embodiment;

[0052] Figure 10 The circuit diagram of the control BMC provided by this embodiment;

[0053] Figure 11 The flowchart of a power supply method provided by this embodiment;

[0054] Figure 12 The structural diagram of a power supply device provided by this embodiment;

[0055] Figure 13 The structural diagram of a power supply system provided by this embodiment.

[0056] Among them, 20 is the PSU, 21 is the OR gate, 22 is the single-stage power supply circuit, 23 is the BMC, 30 is the high-enable tri-state gate, 40 is the VR chip, 41 is the AND gate, and 42 is the low-enable tri-state gate. Detailed implementation manners

[0057] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0058] The core of the present application is to provide a power supply device, method, equipment, system and medium, which can enhance the stability of the BMC state.

[0059] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0060] First of all, it should be noted that the ASTxxx series of chips have evolved from AST2400 (mostly used in the Intel Purley platform), AST2500 (mostly used in the Intel Whitley platform) to the current latest AST2600 model. In this application, the AST2600 chip can be referred to as a VR chip in essence. When using the AST2600 chip to control the power-on and power-off of the BMC, the power-on and power-off methods of the AST2500 chip are followed. Among them, the power-on and power-off methods of the AST2500 chip are generally divided into two types: Power On Sequence and Power Off Sequence. Among them, the timing sequence of the ASTxxx series of chips powered on by Power OnSequence is generally: high voltage, low voltage, clock, reset, etc. The timing of the ASTxxx series of chips powered off by Power Off Sequence is generally not set. However, when powering off with the timing of Power Off Sequence, due to the absence of a specific power-off timing, the high voltage and low voltage will be powered off out of order, resulting in an unstable state of the BMC.

[0061] For the AST2600 chip (VR chip), its power-off timing sequence should be: SRST#, PV10D, PV12D, PV33D_RGM, PV18D, PV33D, etc. The specific sequence of this timing can be referred to Figure 1 , Figure 1 which is the power-off schematic diagram of the VR chip provided in this embodiment.

[0062] Figure 2 which is the structural diagram of a power supply device provided in this embodiment. As Figure 2 shown, the power supply device includes: multiple PSUs, an OR gate, multiple single-stage power supply circuits, and a BMC. Multiple input terminals of the OR gate are connected to the first output terminal and the second output terminal of each PSU, and are used to receive a first signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU are all in a normal working state and a second signal indicating that the input terminal of the PSU is in a normal working state and the first output terminal and the second output terminal of the PSU are in an abnormal working state; the input terminal of each single-stage power supply circuit is connected to the output terminal of the OR gate, and is used to control the working state of the BMC according to the control signal indicating the working state of the BMC obtained from the output terminal of the OR gate; the output terminal of each single-stage power supply circuit serves as the input terminal of the next single-stage power supply circuit.

[0063] In this embodiment, the number of power supply units (PSUs) is at least two. Since in a server architecture, there are generally multiple PSUs. At the same time, in the power supply device, the number of input terminals of the OR gate is the same as the number of PSUs. As Figure 2 shown, when the number of PSUs is two, the number of input terminals of the OR gate is also two. Among them, the number of baseboard management controllers (BMCs) is one.

[0064] Figure 3 is a structural diagram of another power supply device provided in this embodiment. As Figure 3 shown, the power supply device further includes: a plurality of high-enable tri-state gates. The first input terminal of the high-enable tri-state gate is connected to the first output terminal of the PSU; the second input terminal of the high-enable tri-state gate is connected to the second output terminal of the PSU; the output terminals of each high-enable tri-state gate are connected to multiple input terminals of the OR gate; and the number of PSUs is equal to the number of high-enable tri-state gates.

[0065] At this time, the first input terminal of the high-enable tri-state gate receives a first signal, the second input terminal of the high-enable tri-state gate receives a second signal. According to the output logic of the high-enable tri-state gate, a third signal representing the working state of the PSU is obtained at the output terminal of the high-enable tri-state gate. When the third signals of all PSUs are input to all input terminals of the OR gate, according to the output logic of the OR gate, a control signal representing the working state of the control BMC is obtained at the output terminal of the OR gate to control the working state of the BMC. In this embodiment, the first signal is denoted as PSU_AC_OK; the second signal is denoted as PSU_PWR_OK; the third signal is denoted as PSU_Status; the control signal is denoted as BMC_Power_On_Off_Ctrl. In addition, in order for all input terminals of the OR gate to receive more accurate third signals of each PSU, a pull-down resistor is also connected between the output terminal of the high-enable tri-state gate and all input terminals of the OR gate. It should be noted that the model of the OR gate can be set to SN74LVC1G32; the model of the high-enable tri-state gate can be set to SN74LVC1G126. The logic of this high-enable tri-state gate should be: when its first input terminal is a high-level signal and its second input terminal is a high-level signal, the output terminal is also a high-level signal; when its first input terminal is a high-level signal and its second input terminal is a low-level signal, the output terminal is a low-level signal; when its first input terminal is a low-level signal and its second input terminal is in an indeterminate state, the output terminal is in a high-impedance state, and this high-impedance state can be understood as non-conducting, and the level of the high and low is determined by the pull-up and pull-down outside the VR chip to determine the specific state.

[0066] Figure 4 is the circuit diagram of the single-stage power supply circuit provided in this embodiment. AsFigure 4 As shown in Figure 4 , the single-stage power supply circuit includes: at least three VR chips with unequal voltages, an AND gate, a low-enable tri-state gate, and a pull-up power supply. The first input terminal of the low-enable tri-state gate serves as the input terminal of the single-stage power supply circuit. The second input terminal of the low-enable tri-state gate is connected to one end of the first VR chip. The output terminal of the low-enable tri-state gate is connected to the first input terminal of the AND gate. The pull-up power supply is connected to the common terminal formed by the output terminal of the low-enable tri-state gate and the first input terminal of the AND gate. One end of the second VR chip is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to one end of the third VR chip. The other end of the third VR chip serves as the output terminal of the single-stage power supply circuit.

[0067] When the input terminal, the first output terminal, and the second output terminal of the PSU are all in the normal working state, during the power-on process, both PSU_AC_OK and PSU_PWR_OK will change from low to high and then from high to low normally. PSU_Status changes from low to high, and BMC_Power_On_Off_Ctrl finally becomes high, which is used to execute the timing of the Power On Sequence. During the power-off process, PSU_AC_OK first becomes low, PSU_Status changes from high to low, and BMC_Power_On_Off_Ctrl finally becomes low, which is used to execute the timing of the Power Off Sequence. When the input terminal of the PSU is in the normal working state and the first output terminal and the second output terminal of the PSU are in the abnormal working state, when the first output terminal and the second output terminal of the PSU are in the abnormal working state, PSU_PWR_OK becomes low. At this time, during the power-off process, PSU_AC_OK remains high all the time, PSU_PWR_OK becomes low, PSU_Status changes from high to low, and BMC_Power_On_Off_Ctrl finally becomes low, which is used to execute the timing of the Power Off Sequence.

[0068] Due to the existence of the low-enable tri-state gate in the single-stage power supply circuit, in order for all input terminals of the AND gate to receive a more accurate first-level signal, a pull-up power supply is also connected between all input terminals of the low-enable tri-state gate and the AND gate. It should be noted that the model of the AND gate can be set to SN74LVC1G08; the model of the low-enable tri-state gate can be set to SN74LVC1G125. The logic of this low-enable tri-state gate should be: when its first input terminal is a low-level signal and the second input terminal is a high-level signal, the output terminal is also a high-level signal; when its first input terminal is a low-level signal and the second input terminal is a low-level signal, the output terminal is a low-level signal; when its first input terminal is a high-level signal and the second input terminal is in an indeterminate state, the output terminal is in a high-impedance state, and this high-impedance state can be understood as non-conducting, and the specific state of the level is determined by the pull-up and pull-down outside the VR chip.

[0069] After the control signals of all PSUs and the first status signal representing the first VR chip output from one end of the first VR chip in the single-stage power supply circuit are input to the low-enable tri-state gate, according to the obtained first-level signal and the second status signal representing the second VR chip output from one end of the second VR chip in the single-stage power supply circuit, the third status signal representing the third VR chip is obtained at the output end of the AND gate. On the basis of this embodiment, Figure 5 is the circuit diagram of the single-stage power supply circuit of P1V8 provided in this embodiment. At this time, the first status signal is denoted as PWRGD_P3V3_AUX_RGM; the first-level signal is denoted as P1V8_AUX_BUF_EN; the second status signal is denoted as PWRGD_P5V_AUX; the second-level signal is denoted as P1V8_AUX_EN; the third status signal is denoted as PWRGD_P1V8_AUX. Figure 6 is the circuit diagram of the single-stage power supply circuit of P3V3 provided in this embodiment. At this time, the first status signal is denoted as PWRGD_P2V5_AUX_RGM; the first-level signal is denoted as P3V3_AUX_RGM_BUF_EN; the second status signal is denoted as PWRGD_P1V8_AUX; the second-level signal is denoted as P3V3_AUX_RGM_EN; the third status signal is denoted as PWRGD_P3V3_AUX_RGM. Figure 7 is the circuit diagram of the single-stage power supply circuit of P2V5 provided in this embodiment. At this time, the first status signal is denoted as PWRGD_P1V2_AUX; the first-level signal is denoted as P2V5_AUX_BUF_EN; the second status signal is denoted as PWRGD_P3V3_AUX_RGM; the second-level signal is denoted as P2V5_AUX_EN; the third status signal is denoted as PWRGD_P2V5_AUX. Figure 8 is the circuit diagram of the single-stage power supply circuit of P1V2 provided in this embodiment. At this time, the first status signal is denoted as PWRGD_P1V0_AUX; the first-level signal is denoted as P1V2_AUX_BUF_EN; the second status signal is denoted as PWRGD_P2V5_AUX; the second-level signal is denoted as P1V2_AUX_EN; the third status signal is denoted as PWRGD_P1V2_AUX. Figure 9 is the circuit diagram of the single-stage power supply circuit of P1V0 provided in this embodiment. At this time, the first status signal is denoted as PWRGD_P1V8_PE_RC_AUX; the first-level signal is denoted as P1V0_AUX_BUF_EN; the second status signal is denoted as PWRGD_P1V2_AUX; the second-level signal is denoted as P1V0_AUX_EN; the third status signal is denoted as PWRGD_P1V0_AUX. Figure 10The circuit diagram for controlling the BMC provided in this embodiment is as follows. Figure 10 As shown, according to the AND gate control logic, the control signal and the third status signal PWRGD_P1V0_AUX are input to the input terminals of all AND gates, and the signal P1V8_PE_RC_AUX_EN for controlling the BMC is obtained at the output terminal of the AND gate.

[0070] In this application, the control signal is determined by the first signal and the second signal of multiple PSUs, and the control signal is input to each single-stage power supply circuit to achieve power-on or power-off step by step, further enhancing the stability of the BMC status.

[0071] Figure 11 The flowchart of a power supply method provided in this embodiment. This application also provides a power supply method, as follows. Figure 11 As shown, applied to the above power supply device, the method includes:

[0072] S110: Collect the first signal at the first output terminal of the PSU and the second signal at the second output terminal of the PSU, and transmit the first signal and the second signal to multiple input terminals of the OR gate.

[0073] Among them, the first signal is a signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU are all in a normal working state, and the second signal is a second signal indicating that the input terminal of the PSU is in a normal working state and the first output terminal and the second output terminal of the PSU are in an abnormal working state.

[0074] S111: Obtain the control signal through the output terminal of the OR gate.

[0075] Among them, the control signal is a signal indicating the working state of controlling the BMC.

[0076] S112: Transmit the control signal to multiple single-stage power supply circuits to control the working state of the BMC.

[0077] When the input terminal, the first output terminal, and the second output terminal of the PSU are all in normal working states, during the power-on process, both PSU_AC_OK and PSU_PWR_OK will normally go high and then low; PSU_Status goes from low to high, and BMC_Power_On_Off_Ctrl finally goes high to execute the timing of the Power On Sequence; during the power-off process, PSU_AC_OK goes low first, PSU_Status goes from high to low, and BMC_Power_On_Off_Ctrl finally goes low to execute the timing of the Power Off Sequence; when the input terminal of the PSU is in the normal working state and the first output terminal and the second output terminal of the PSU are in abnormal working states, when the first output terminal and the second output terminal of the PSU are in abnormal working states, it causes PSU_PWR_OK to go low; at this time, during the power-off process, PSU_AC_OK remains high all the time, PSU_PWR_OK goes low, PSU_Status goes from high to low, and BMC_Power_On_Off_Ctrl finally goes low to execute the timing of the Power Off Sequence.

[0078] Based on the above embodiments, as a more optimal embodiment, after collecting the first signal of the first output terminal of the PSU and the second signal of the second output terminal of the PSU, and before obtaining the control signal at the output terminal of the OR gate, it further includes:

[0079] Taking the logic of the high-enabled tri-state gate as a condition, a third signal representing the working state of the PSU is generated according to the first signal and the second signal.

[0080] The first input terminal of the high-enabled tri-state gate receives the first signal, the second input terminal of the high-enabled tri-state gate receives the second signal. According to the output logic of the high-enabled tri-state gate, a third signal representing the working state of the PSU is obtained at the output terminal of the high-enabled tri-state gate. When the third signals of all PSUs are input to all input terminals of the OR gate, according to the output logic of the OR gate, a control signal representing the working state of controlling the BMC is obtained at the output terminal of the OR gate to control the working state of the BMC. The logic of the high-enabled tri-state gate should be: when its first input terminal is a high-level signal and its second input terminal is a high-level signal, its output terminal is also a high-level signal; when its first input terminal is a high-level signal and its second input terminal is a low-level signal, its output terminal is a low-level signal; when its first input terminal is a low-level signal and its second input terminal is in an indeterminate state, its output terminal is in a high-impedance state, and this high-impedance state can be understood as non-conducting, and the specific state of the level is determined by the pull-up and pull-down outside the VR chip.

[0081] Based on the above embodiments, as a more optimal embodiment, after transmitting the control signal to multiple single-stage power supply circuits, it further includes:

[0082] Conditional on the logic of a low-enable tri-state gate, a first-level signal is generated based on a control signal and a first-state signal representing a first VR chip output from one end of the first VR chip in a single-stage power supply circuit;

[0083] Conditional on the logic of an AND gate, a second-level signal is generated based on the first-level signal and a second-state signal representing a second VR chip output from one end of the second VR chip in the single-stage power supply circuit;

[0084] Based on the second-level signal, the operating state of a third VR chip in the single-stage power supply circuit is controlled, and a third-state signal representing the third VR chip is generated, where the operating states of the VR chips are respectively a powered-on state or a powered-off state.

[0085] Due to the presence of a low-enable tri-state gate in the single-stage power supply circuit, in order for all input terminals of the AND gate to receive a more accurate first-level signal, a pull-up power supply is also connected between all input terminals of the low-enable tri-state gate and the AND gate. The logic of the low-enable tri-state gate should be: when its first input terminal is a low-level signal, the second input terminal is a high-level signal, and the output terminal is also a high-level signal; when its first input terminal is a low-level signal, the second input terminal is a low-level signal, and the output terminal is a low-level signal; when its first input terminal is a high-level signal and the second input terminal is in an indeterminate state, the output terminal is in a high-impedance state, and this high-impedance state can be understood as non-conductive, and the specific state of the level is determined by the pull-up and pull-down outside the VR chip.

[0086] After all control signals of the PSU and the first-state signal representing the first VR chip output from one end of the first VR chip in the single-stage power supply circuit are input to the low-enable tri-state gate, based on the obtained first-level signal and the second-state signal representing the second VR chip output from one end of the second VR chip in the single-stage power supply circuit, a third-state signal representing the third VR chip is obtained at the output terminal of the AND gate according to the second-state signal.

[0087] On the basis of the above embodiments, as a more optimal embodiment, after generating the third-state signal representing the third VR chip, it further includes:

[0088] When all VR chips in all single-stage power supply circuits are in the powered-on state or the powered-off state, output a prompt message. It should be noted that this prompt message is generally represented in the form of a data string, and the data string can be 1-bit, 2-bit, 4-bit, 8-bit, etc. When the data string is 1-bit, the prompt message can be represented as a data string in the form of "0" or "1"; when the data string is 2-bit, the prompt message can be represented as a data string in the form of "01" or "10"; when the data string is 4-bit, the prompt message can be represented as a data string in the form of "0101" or "0110"; when the data string is 8-bit, the prompt message can be represented as a data string in the form of "11001101" or "00101110".

[0089] In the above embodiments, the power supply method is described in detail. The present application also provides an embodiment corresponding to a power supply device. It should be noted that the present application describes the embodiments of the device part from two perspectives, one is from the perspective of functional modules, and the other is from the perspective of hardware.

[0090] Figure 12 The structure diagram of a power supply device provided in this embodiment. As Figure 12 shown, the present application also provides a power supply device, including:

[0091] An acquisition module 120, configured to acquire a first signal at the first output end of the PSU and a second signal at the second output end of the PSU, and transmit the first signal and the second signal to multiple input ends of an OR gate. Among them, the first signal is a signal indicating that the input end, the first output end, and the second output end of the PSU are all in a normal working state, and the second signal is a second signal indicating that the input end of the PSU is in a normal working state and the first output end and the second output end of the PSU are in an abnormal working state;

[0092] An acquisition module 121, configured to acquire a control signal through the output end of the OR gate, where the control signal is a signal indicating the working state of the control BMC;

[0093] A transmission module 122, configured to transmit the control signal to multiple single-stage power supply circuits to control the working state of the BMC.

[0094] In addition, the device further includes the following modules:

[0095] After acquiring the first signal at the first output end of the PSU and the second signal at the second output end of the PSU, and before acquiring the control signal through the output end of the OR gate, it further includes:

[0096] A first generation module, configured to generate a third signal indicating the working state of the PSU according to the first signal and the second signal on the condition of the logic of a high-enabled tri-state gate.

[0097] Preferably, after transmitting the control signal to a plurality of single-stage power supply circuits, the method further includes:

[0098] A second generation module, configured to generate a first level signal based on the control signal and a first status signal representing a first VR chip output from one end of the first VR chip in the single-stage power supply circuit, with the logic of a low-enable tri-state gate as a condition;

[0099] A third generation module, configured to generate a second level signal based on the first level signal and a second status signal representing a second VR chip output from one end of the second VR chip in the single-stage power supply circuit, with the logic of an AND gate as a condition;

[0100] A fourth generation module, configured to control the operating state of a third VR chip in the single-stage power supply circuit according to the second level signal and generate a third status signal representing the third VR chip, where the operating states of the VR chips are respectively a powered-on state or a powered-off state.

[0101] Preferably, after generating the third status signal representing the third VR chip, the method further includes:

[0102] An output module, configured to output a prompt message when all VR chips in all single-stage power supply circuits are in a powered-on state or a powered-off state.

[0103] In this embodiment, the control signal is determined by the first signal and the second signal of multiple PSUs, and the control signal is input into each single-stage power supply circuit to achieve power-on or power-off step by step, further enhancing the stability of the BMC state.

[0104] Since the embodiments of the apparatus part correspond to the embodiments of the method part, for the embodiments of the apparatus part, please refer to the description of the embodiments of the method part, which will not be elaborated here.

[0105] Figure 13 The following is a structural diagram of a power supply system provided in this embodiment, as Figure 13 shown, a power supply system includes:

[0106] A memory 130, configured to store a computer program;

[0107] A processor 131, configured to implement the steps of the power supply method mentioned in the above embodiments when executing the computer program.

[0108] The power supply system provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a notebook computer, or a desktop computer, etc.

[0109] Among them, the processor 131 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 131 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 131 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 131 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 131 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0110] The memory 130 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 130 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 130 is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor 131, the relevant steps of the power supply method disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 130 may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, the power supply method, etc. In some embodiments, the power supply system may further include a display screen, an input / output interface, a communication interface, a power supply, and a communication bus. Those skilled in the art can understand that Figure 13 the structure shown in does not constitute a limitation on the power supply system, and may include more or fewer components than shown in the figure. The power supply system provided by the embodiments of the present application includes a memory 130 and a processor 131. When the processor 131 executes the program stored in the memory 130, the power supply method can be implemented.

[0111] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps recorded in the above method embodiments are implemented.

[0112] It can be understood that if the methods in the above embodiments are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs, etc., which can store program codes.

[0113] The above has introduced in detail a power supply device, method, equipment, system, and medium provided by the present application. The embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0114] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitations, the element defined by the statement "including an..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

Claims

1. A power supply device, characterized in that, Comprising: Multiple PSUs (20), an OR gate (21), multiple single-stage power supply circuits (22), and a BMC (23); Multiple input terminals of the OR gate (21) are connected to the first output terminal and the second output terminal of each PSU (20), and are used to receive a first signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU (20) are all in a normal working state, and a second signal indicating that the input terminal of the PSU (20) is in a normal working state while the first output terminal and the second output terminal of the PSU (20) are in an abnormal working state; the input terminal of each single-stage power supply circuit (22) is connected to the output terminal of the OR gate (21), and is used to control the working state of the BMC (23) according to a control signal obtained from the output terminal of the OR gate (21) for indicating the working state of the BMC (23); the output terminal of each single-stage power supply circuit (22) serves as the input terminal of the next-level single-stage power supply circuit (22); The single-stage power supply circuit (22) comprises: at least three VR chips (40) with unequal voltages, an AND gate (41), a low-enable tri-state gate (42), and a pull-up power supply; The first input terminal of the low-enable tri-state gate (42) serves as the input terminal of the single-stage power supply circuit (22), the second input terminal of the low-enable tri-state gate (42) is connected to one end of the first VR chip (40), the output terminal of the low-enable tri-state gate (42) is connected to the first input terminal of the AND gate (41), the pull-up power supply is connected to the common terminal formed by the output terminal of the low-enable tri-state gate (42) and the first input terminal of the AND gate (41), one end of the second VR chip (40) is connected to the second input terminal of the AND gate (41), and the output terminal of the AND gate (41) is connected to one end of the third VR chip (40), wherein the other end of the third VR chip (40) serves as the output terminal of the single-stage power supply circuit (22).

2. The power supply device according to claim 1, characterized in that Further comprising: Multiple high-enable tri-state gates (30); The first input terminal of the high-enable tri-state gate (30) is connected to the first output terminal of the PSU (20); the second input terminal of the high-enable tri-state gate (30) is connected to the second output terminal of the PSU (20); the output terminals of each high-enable tri-state gate (30) are connected to multiple input terminals of the OR gate (21); and the number of PSUs (20) is equal to the number of high-enable tri-state gates (30).

3. A power supply method, characterized in that, Comprising: Collecting a first signal of the first output terminal of the PSU and a second signal of the second output terminal of the PSU, and transmitting the first signal and the second signal to multiple input terminals of the OR gate, wherein the first signal is a signal indicating that the input terminal, the first output terminal, and the second output terminal of the PSU are all in a normal working state, and the second signal is a second signal indicating that the input terminal of the PSU is in a normal working state while the first output terminal and the second output terminal of the PSU are in an abnormal working state; Obtain a control signal through the output terminal of the OR gate, where the control signal is a signal characterizing the working state of controlling the BMC; Transmit the control signal to multiple single-stage power supply circuits to control the working state of the BMC; Taking the logic of the low-enable tri-state gate as a condition, generate a first-level signal according to the control signal and the first-state signal characterizing the first VR chip output from one end of the first VR chip in the single-stage power supply circuit; Taking the logic of the AND gate as a condition, generate a second-level signal according to the first-level signal and the second-state signal characterizing the second VR chip output from one end of the second VR chip in the single-stage power supply circuit; Control the working state of the third VR chip in the single-stage power supply circuit according to the second-level signal and generate a third-state signal characterizing the third VR chip, where the working states of the VR chips are respectively the powered-on state or the powered-off state.

4. The power supply method according to claim 3, wherein After collecting the first signal at the first output terminal of the PSU and the second signal at the second output terminal of the PSU, and before obtaining the control signal through the output terminal of the OR gate, it further includes: Taking the logic of the high-enable tri-state gate as a condition, generate a third signal characterizing the working state of the PSU according to the first signal and the second signal.

5. The power supply method according to claim 3, characterized in that, After generating the third-state signal characterizing the third VR chip, it further includes: When all the VR chips in all the single-stage power supply circuits are in the powered-on state or the powered-off state, output a prompt message.

6. A power supply device, characterized in that, It includes: A collection module for collecting the first signal at the first output terminal of the PSU and the second signal at the second output terminal of the PSU, and transmitting the first signal and the second signal to multiple input terminals of the OR gate, where the first signal is a signal characterizing that the input terminal, the first output terminal, and the second output terminal of the PSU are all in the normal working state, and the second signal is a second signal characterizing that the input terminal of the PSU is in the normal working state and the first output terminal and the second output terminal of the PSU are in the abnormal working state; An obtaining module for obtaining a control signal through the output terminal of the OR gate, where the control signal is a signal characterizing the working state of controlling the BMC; A transmission module for transmitting the control signal to multiple single-stage power supply circuits to control the working state of the BMC; A second generation module for generating a first-level signal according to the control signal and the first-state signal characterizing the first VR chip output from one end of the first VR chip in the single-stage power supply circuit, taking the logic of the low-enable tri-state gate as a condition; A third generation module for generating a second-level signal according to the first-level signal and the second-state signal characterizing the second VR chip output from one end of the second VR chip in the single-stage power supply circuit, taking the logic of the AND gate as a condition; A fourth generation module, configured to control the operating state of a third VR chip in the single-stage power supply circuit according to the second level signal, and generate a third state signal characterizing the third VR chip, wherein the operating states of the VR chip are respectively a power-on state or a power-off state.

7. A power supply system, characterized in that, Comprising: A memory for storing a computer program; A processor, configured to implement the steps of the power supply method according to any one of claims 3 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the power supply method according to any one of claims 3 to 5 are implemented.

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