A BMC and server

Abstract

The application discloses a BMC, comprising a plurality of virtual VGA controllers, each of which is used for connecting a server host; a plurality of display memories, each of which is connected with a virtual VGA controller; a configuration controller, which has a plurality of input ends and an output end, each of the input ends being connected with a virtual VGA controller; and a VGA controller, which is connected with the output end of the configuration controller. The application can be applied to the scene of managing a plurality of host hosts by using one BMC chip, and only one VGA controller is used in the scene.

Description

Technical Field

[0001] This invention relates to the field of BMC (Browser Control Center), and more specifically to a BMC and a server. Background Technology

[0002] With social progress and technological development, the arrival of the big data era has led to an increasing demand for servers. The Server Management Center (BMC), as the management hub of a server, plays a crucial role, from daily server function management and remote system debugging to system log analysis. Currently, a server requires at least one BMC chip as its management chip, and multi-processor servers may require two or more BMC chips for management. Managing servers with multiple BMC chips becomes increasingly complex.

[0003] Currently, there are single BMC chips on the market that can manage multiple host servers, meaning that one BMC chip can manage multiple different servers.

[0004] BMC's VGA (Video Graphics Array) display function is crucial for servers. On one hand, BMC's VGA display saves server space, eliminating the need for an external graphics card and significantly reducing space requirements. On the other hand, BMC's VGA function can provide image information to the host operating system for remote management, thereby enabling remote control capabilities.

[0005] like Figure 1 As shown, when managing multiple host servers with a single BMC chip, such as a scenario with two hosts, two VGA IPs need to be integrated into the single BMC chip to enable VGA display on both hosts. However, in typical scenarios where the BMC manages dual-host servers, only one host can be debugged at a time; therefore, it's unnecessary for both hosts to display simultaneously. In this case, the existence of two VGA IPs would result in wasted resources. Summary of the Invention

[0006] In view of this, in order to overcome at least one aspect of the above-mentioned problems, embodiments of the present invention provide a BMC, comprising:

[0007] Multiple virtual VGA controllers, each of which is used to connect to a server host;

[0008] Multiple video memory locations, each of which is connected to one of the virtual VGA controllers;

[0009] The configuration controller has multiple inputs and one output, wherein each input is connected to one of the virtual VGA controllers;

[0010] The VGA controller is connected to the output of the configuration controller.

[0011] In some embodiments, the VGA controller includes a control register and a status register, and each of the virtual VGA controllers includes RAM;

[0012] Each of the virtual VGA controllers is configured to, in response to receiving a command to configure the VGA controller, parse the command to obtain a configuration instruction and update the corresponding control register in the VGA controller and the corresponding value in the RAM according to the configuration instruction.

[0013] In some embodiments, each of the virtual VGA controllers is further configured to:

[0014] In response to receiving a switching command, if the virtual VGA controller is the currently working virtual VGA controller, read the values ​​of all control registers and status registers in the VGA controller, and send a read completion signal to the virtual VGA controller to be worked according to the switching command;

[0015] If the virtual VGA controller is the virtual VGA controller to be operated, when it receives the read complete signal, it will synchronize the value in its own RAM to the VGA controller.

[0016] In some embodiments, the virtual VGA controller is further configured to receive image data and update the corresponding video memory.

[0017] In some embodiments, the VGA controller is also configured to read image data from the video memory and display it, and to update the value of the status register.

[0018] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a server, including a plurality of hosts and a BMC, wherein the BMC includes:

[0019] Multiple virtual VGA controllers, each of which is used to connect to a host;

[0020] Multiple video memory locations, each of which is connected to one of the virtual VGA controllers;

[0021] The configuration controller has multiple inputs and one output, wherein each input is connected to one of the virtual VGA controllers;

[0022] The VGA controller is connected to the output of the configuration controller.

[0023] In some embodiments, the VGA controller includes a control register and a status register, and each of the virtual VGA controllers includes RAM;

[0024] Each of the virtual VGA controllers is configured to, in response to receiving a command to configure the VGA controller, parse the command to obtain a configuration instruction and update the corresponding control register in the VGA controller and the corresponding value in the RAM according to the configuration instruction.

[0025] In some embodiments, each of the virtual VGA controllers is further configured to:

[0026] In response to receiving a switching command, if the virtual VGA controller is the currently working virtual VGA controller, read the values ​​of all control registers and status registers in the VGA controller, and send a read completion signal to the virtual VGA controller to be worked according to the switching command;

[0027] If the virtual VGA controller is the virtual VGA controller to be operated, when it receives the read complete signal, it will synchronize the value in its own RAM to the VGA controller.

[0028] In some embodiments, the virtual VGA controller is further configured to receive image data and update the corresponding video memory.

[0029] In some embodiments, the VGA controller is also configured to read image data from the video memory and display it, and to update the value of the status register.

[0030] The present invention has one of the following beneficial technical effects: The present invention can be applied to a scenario in which a single BMC chip is used to manage multiple host hosts at the same time, and only one VGA controller is used in this scenario. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0032] Figure 1 A structural diagram of BMC provided for the prior art;

[0033] Figure 2 A schematic diagram of the structure of BMC provided for an embodiment of the present invention;

[0034] Figure 3A flowchart illustrating the implementation of multi-host display functionality provided in an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0036] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0037] According to one aspect of the present invention, embodiments of the present invention provide a BMC that may include:

[0038] Multiple virtual VGA controllers, each of which is used to connect to a server host;

[0039] Multiple video memory locations, each of which is connected to one of the virtual VGA controllers;

[0040] The configuration controller has multiple inputs and one output, wherein each input is connected to one of the virtual VGA controllers;

[0041] The VGA controller is connected to the output of the configuration controller.

[0042] This invention is applicable to scenarios where a single BMC chip is used to manage multiple host machines simultaneously, and in such scenarios only a single VGA controller is used.

[0043] In some embodiments, the VGA controller includes a control register and a status register, and each of the virtual VGA controllers includes RAM;

[0044] Each of the virtual VGA controllers is configured to, in response to receiving a command to configure the VGA controller, parse the command to obtain a configuration instruction and update the corresponding control register in the VGA controller and the corresponding value in the RAM according to the configuration instruction.

[0045] In some embodiments, each of the virtual VGA controllers is further configured to:

[0046] In response to receiving a switching command, if the virtual VGA controller is the currently working virtual VGA controller, read the values ​​of all control registers and status registers in the VGA controller, and send a read completion signal to the virtual VGA controller to be worked according to the switching command;

[0047] If the virtual VGA controller is the virtual VGA controller to be operated, when it receives the read complete signal, it will synchronize the value in its own RAM to the VGA controller.

[0048] In some embodiments, the virtual VGA controller is further configured to receive image data and update the corresponding video memory.

[0049] In some embodiments, the VGA controller is also configured to read image data from the video memory and display it, and to update the value of the status register.

[0050] The following is based on Figure 2 The two virtual VGA controllers and two video memory units shown are used as examples to illustrate the BMC proposed in this invention in detail.

[0051] like Figure 2 As shown, the two hosts are Server Host 1 and Server Host 2. These two server hosts can run different operating systems and are physically located on the same server. Each server host is connected to the BMC via a PCIe interface (1 / 2). Image data and configuration information of the server hosts are transmitted through the PCIe interface. The EP end of the PCIe interface is connected to the virtual VGA controller.

[0052] The BMC chip can connect to both server hosts simultaneously, thereby enabling the monitoring of both server hosts and the entire server.

[0053] In some embodiments, such as Figure 3 As shown, the virtual VGA controller can receive data and commands transmitted via PCIe. The virtual VGA controller contains a RAM that stores all the internal registers and their default values. When the host server accesses the VGA via the PCIe interface, the virtual VGA controller is responsible for receiving the relevant commands and responding with the corresponding information. For example, if the host server needs to read the VGA controller's ID, the virtual VGA device parses the command and returns the ID value stored in RAM to the host server. Similarly, if the host server needs to configure a specific register on the VGA controller, the virtual VGA device parses the command, updates the value of the relevant register stored in RAM, and simultaneously updates the value of the corresponding control register in the VGA controller.

[0054] When a switch to server host display is detected, i.e., from server host 1 to server host 2, the virtual VGA controller needs to save the registers of the currently operating VGA controller (including the status register and control register, where the status register is updated in real time according to the display screen) to the RAM of virtual VGA controller 1. This process involves virtual VGA controller 1 actively reading the current VGA controller registers and updating its own RAM with the read values. After virtual VGA controller 1 updates its RAM, virtual VGA controller 2 actively updates the register data in its own RAM to the VGA controller by writing to the VGA controller, thereby switching to the control state of server host 2.

[0055] The virtual VGA controller's strategy for updating video memory is as follows: When the VGA is operating under server host 1, video memory 1 is enabled, and the virtual VGA controller updates the image data to the video memory. The VGA controller then retrieves the image data from video memory 1 for display. At the same time, server host 2 is also operating, and virtual VGA controller 2 updates the data to video memory 2.

[0056] Regarding the switching strategy for the virtual VGA controller, the VGA switching command is issued by the upper layer of the BMC software and can be switched at any time when needed. For example, when VGA virtual controller 2 is working, if the upper layer software issues a VGA switching command, VGA virtual controller 2 will save the registers in the VGA controller. After saving is complete, it will send a completion signal to VGA virtual controller 1, thereby causing VGA virtual controller 1 to begin initializing the VGA controller.

[0057] This invention is applicable to scenarios where a single BMC chip is used to manage multiple host machines simultaneously, and in such scenarios only a single VGA controller is used.

[0058] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a server, including a plurality of hosts and a BMC, wherein the BMC includes:

[0059] Multiple virtual VGA controllers, each of which is used to connect to a host;

[0060] Multiple video memory locations, each of which is connected to one of the virtual VGA controllers;

[0061] The configuration controller has multiple inputs and one output, wherein each input is connected to one of the virtual VGA controllers;

[0062] The VGA controller is connected to the output of the configuration controller.

[0063] In some embodiments, the VGA controller includes a control register and a status register, and each of the virtual VGA controllers includes RAM;

[0064] Each of the virtual VGA controllers is configured to, in response to receiving a command to configure the VGA controller, parse the command to obtain a configuration instruction and update the corresponding control register in the VGA controller and the corresponding value in the RAM according to the configuration instruction.

[0065] In some embodiments, each of the virtual VGA controllers is further configured to:

[0066] In response to receiving a switching command, if the virtual VGA controller is the currently working virtual VGA controller, read the values ​​of all control registers and status registers in the VGA controller, and send a read completion signal to the virtual VGA controller to be worked according to the switching command;

[0067] If the virtual VGA controller is the virtual VGA controller to be operated, when it receives the read complete signal, it will synchronize the value in its own RAM to the VGA controller.

[0068] In some embodiments, the virtual VGA controller is further configured to receive image data and update the corresponding video memory.

[0069] In some embodiments, the VGA controller is also configured to read image data from the video memory and display it, and to update the value of the status register.

[0070] This invention is applicable to scenarios where a single BMC chip is used to manage multiple host machines simultaneously, and in such scenarios only a single VGA controller is used.

[0071] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0072] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0073] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0074] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0075] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0076] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A BMC, characterized in that, include: Multiple virtual VGA controllers, each of which is used to connect to a server host; Multiple video memory locations, each of which is connected to one of the virtual VGA controllers; The configuration controller has multiple inputs and one output, wherein each input is connected to one of the virtual VGA controllers; The VGA controller is connected to the output of the configuration controller and is configured to read image data from the video memory connected to the currently working virtual VGA controller, display it, and update the value of the status register. Each of the virtual VGA controllers is further configured as follows: Receive image data and update the corresponding video memory; In response to receiving a switching command, if the virtual VGA controller is the currently working virtual VGA controller, read the values ​​of all control registers and status registers in the VGA controller, and send a read completion signal to the virtual VGA controller to be worked according to the switching command; If the virtual VGA controller is the virtual VGA controller to be operated, when it receives the read complete signal, it will synchronize the value in its own RAM to the VGA controller.

2. The BMC as described in claim 1, characterized in that, The VGA controller includes a control register and a status register, and each of the virtual VGA controllers includes RAM; Each of the virtual VGA controllers is configured to, in response to receiving a command to configure the VGA controller, parse the command to obtain a configuration instruction and update the corresponding control register in the VGA controller and the corresponding value in the RAM according to the configuration instruction.

3. A server, characterized in that, Includes multiple hosts and BMCs, wherein the BMCs include: Multiple virtual VGA controllers, each of which is used to connect to a host; Multiple video memory locations, each of which is connected to one of the virtual VGA controllers; The configuration controller has multiple inputs and one output, wherein each input is connected to one of the virtual VGA controllers; The VGA controller is connected to the output of the configuration controller and is configured to read image data from the video memory connected to the currently working virtual VGA controller, display it, and update the value of the status register. Each of the virtual VGA controllers is further configured as follows: Receive image data and update the corresponding video memory; In response to receiving a switching command, if the virtual VGA controller is the currently working virtual VGA controller, read the values ​​of all control registers and status registers in the VGA controller, and send a read completion signal to the virtual VGA controller to be worked according to the switching command; If the virtual VGA controller is the virtual VGA controller to be operated, when it receives the read complete signal, it will synchronize the value in its own RAM to the VGA controller.

4. The server as described in claim 3, characterized in that, The VGA controller includes a control register and a status register, and each of the virtual VGA controllers includes RAM; Each of the virtual VGA controllers is configured to, in response to receiving a command to configure the VGA controller, parse the command to obtain a configuration instruction and update the corresponding control register in the VGA controller and the corresponding value in the RAM according to the configuration instruction.

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