Configurable arithmetic unit within memory

Abstract

A configurable operation unit in a memory is provided, including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first read bit line and a common signal line, wherein the first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first read bit line and the common signal line, wherein the second input transistor is coupled to a second input bit line, and the second weight transistor receives a second weight bit.

Description

TECHNICAL FIELD

[0001] The present application relates to an operation unit, and particularly to a configurable operation unit in memory. BACKGROUND

[0002] Computing in memory (CIM) technology is considered as one of the effective technologies to solve the memory wall, which uses computing in memory to reduce the number of data movement, which can greatly improve the instruction cycle to several hundred or even several thousand times of the traditional architecture. Today's large artificial intelligence (AI) networks, such as deep neural networks (DNNs), consume a large part of energy in data movement, but the CIM technology can also greatly reduce the energy wasted by data movement, which is a future AI potential technology that can increase computing power and reduce power consumption.

[0003] The potential of computing in memory makes many manufacturers and research units invest and publish many novel technologies, most of which change the operation unit to an analog state and determine the number of open analog accumulation values as the result of the multiply-accumulate operation (MAC) of data and weights. Most static random access memories (SRAMs) use the discharge time after charging the bit line (BL) to determine the MAC value. For example, the more the number of open cells, the faster the discharge speed; the fewer the number of open cells, the slower the discharge speed. Therefore, after measuring the remaining amount of electricity on the bit line at a fixed time, the current MAC value can be deduced.

[0004] However, because the amount of charge that the bit line itself can store is not much, when the number of simultaneously open cells is too many, it will be difficult to determine the problem within a fixed time due to the too fast leakage speed, so the CIM of the static random access memory cannot usually open too many data channel input data to perform C CIM at the same time. In this way, although the static random access memory operates at a very fast speed, the parallelism is difficult to improve, and if the memory cell is changed, it may cause problems such as a decrease in the yield of the memory.

[0005] Another novel technique is to use the product-sum operation of in-memory operation using resistive memory (e.g. Resistive random-access memory (RRAM)) to use the current flowing through the equivalent resistance of different opening numbers as the value of the product-sum operation, which can increase the number of simultaneously openable data channels. However, due to the R / N ratio of the rapid reduction of the equivalent resistance after the parallel connection of the cells, when the equivalent resistance is reduced to a certain extent, the parasitic resistance on the line will become the dominant value, so that if a sufficient number is to be opened, the resistance of the cell must be high enough, usually reaching the level of ten k ohms, which is not easy to achieve for resistive memory, Magnetoresistive Random Access Memory (MRAM) and other resistive memory. Therefore, the current technology for in-memory operation in resistive memory is still at the level of tens of data channels. SUMMARY

[0006] The present application is directed to a configurable operation unit in memory, which can achieve the function of product-sum operation without changing the memory array.

[0007] According to an embodiment of the present application, the configurable operation unit in memory includes a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor. The first input transistor has a first end, a control end coupled to a first input bit line, and a second end. The first weight transistor has a first end coupled to the second end of the first input transistor, a control end receiving a first weight bit, and a second end coupled to a first readout bit line. The first resistor is coupled between the first end of the first input transistor and a common signal line. The second input transistor has a first end, a control end coupled to a second input bit line, and a second end. The second weight transistor has a first end coupled to the second end of the second input transistor, a control end receiving the first weight bit, and a second end coupled to the first readout bit line. The second resistor is coupled between the first end of the second input transistor and the common signal line. The resistance value of the second resistor is different from the resistance value of the first resistor.

[0008] According to an embodiment of the present application, a configurable operation unit in a memory includes a first weight transistor, at least one first input transistor, and at least one second input transistor. The first weight transistor has a first end coupled to a first read bit line, a control end receiving a first weight bit, and a second end. The at least one first input transistor has a first end coupled to the second end of the first weight transistor, a control end coupled to a first input bit line, and a second end coupled to a common signal line. The at least one second input transistor has a first end coupled to the second end of the first weight transistor, a control end coupled to a second input bit line, and a second end coupled to the common signal line. The number of the at least one first input transistor is different from the number of the at least one second input transistor.

[0009] Based on the above, the configurable operation unit of the embodiments of the present application achieves the function of multiply-accumulate operation by connecting the weight transistor, the input transistor and the resistor in series and setting different resistance values of the resistors. Thus, since the configurable operation unit is an additional functional block, the multiply-accumulate operation (MAC) of the data bit and the weight bit can be achieved without changing the memory array. Alternatively, the function of multiply-accumulate operation is achieved by connecting the weight transistor and the input transistors in series.

[0010] In order to make the above features and advantages of the present application more apparent, the following embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 The circuit schematic diagram of the configurable operation unit according to the first embodiment of the present application coupled to the weight memory cell.

[0012] Figure 2 The circuit schematic diagram of the configurable operation unit according to the second embodiment of the present application.

[0013] Figure 3 The circuit schematic diagram of the configurable operation unit according to the third embodiment of the present application.

[0014] Figure 4 The circuit schematic diagram of the configurable operation unit according to the fourth embodiment of the present application.

[0015] Figure 5 The circuit schematic diagram of the configurable operation unit according to the fifth embodiment of the present application coupled to the weight memory cell.

[0016] Figure 6 The circuit schematic diagram of the configurable operation unit according to the sixth embodiment of the present application.

[0017] Figure 7 The circuit schematic diagram of the configurable operation unit according to the seventh embodiment of the present application.

[0018] Figure 8 Circuit schematic diagram of configurable operation unit according to the eighth embodiment of the present application. DETAILED DESCRIPTION

[0019] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0020] The concept of the present application is to add a functional block required for in-memory operation in a conventional memory, to convert the conventional memory from digital data to analog data available for CIM operation, and to use resistors with different impedance values to achieve operation sum current for different operations, to reduce process drift, and to increase operation parallelism, so that the technology of the present application can simultaneously have the fast operation of its own memory, the high parallelism operation capability of in-memory operation, and is extremely suitable for inference use of edge operation.

[0021] In other words, the concept of the present application discloses an architecture for artificial intelligence (AI) computing in memory, which can output stored data to a weight reader block from a sense amplifier (SA) of a conventional memory or using a bit line (BL), and combine the proposed operation cell to use the total current of the operation cell with the input transistor and the weight transistor simultaneously turned on as the operation value, to achieve the operation function of the product-sum operation of in-memory operation. The concept of the present application only needs to add an operation cell in the peripheral circuit of the memory cell without changing the architecture of the memory cell, to reduce the risk of read drift.

[0022] Figure 1 Circuit schematic diagram of configurable operation unit according to the first embodiment of the present application coupled with a weight memory cell. Please refer to Figure 1 In this embodiment, the memory subarray 10 and the configurable operation unit 100 are configured in a memory (not shown), and the configurable operation unit 100 at least includes transistors M0-M5, a resistor R01 (corresponding to a first resistor), and a resistor R11 (corresponding to a second resistor).

[0023] The transistor M2 (corresponding to a first input transistor) has a first end, a control end coupled to one of the plurality of input bit lines (e.g., INBL_0 to INBL_3) (here, the input bit line INBL_2 is taken as an example, corresponding to a first input bit line), and a second end. The transistor M3 (corresponding to a first weight transistor) has a first end coupled to the second end of the transistor M2, a control end receiving a first weight bit W0 from the memory sub-array 10, and a second end coupled to a first read bit line R_RBL<0> coupled to a high voltage power supply line Vdd through an external resistor Rx. The resistor R01 is coupled between the first end of the transistor M2 and a common signal line, which can be either a global inverted bit line GBLB<0> or a low voltage power supply line VSS according to operation, depending on the circuit design.

[0024] The transistor M5 (corresponding to a second input transistor) has a first end, a control end coupled to another one of the plurality of input bit lines (e.g., INBL_0 to INBL_3) (here, the input bit line INBL_3 is taken as an example, corresponding to a second input bit line), and a second end. The transistor M4 (corresponding to a second weight transistor) has a first end coupled to the second end of the transistor M5, a control end receiving the first weight bit W0, and a second end coupled to the first read bit line R_RBL<0>. The resistor R11 is coupled between the first end of the transistor M5 and the common signal line (e.g., GBLB<0> / VSS).

[0025] In the present embodiment, the resistor R11 has a resistance value different from that of the resistor R01, so that the total current flowing through the first read bit line R_RBL<0> is the sum of the weight product of the first weight bit W0 and the bit (i.e., logic level) transmitted by the input bit line INBL_2 and the weight product of the first weight bit W0 and the bit (i.e., logic level) transmitted by the input bit line INBL_3. According to the above, the operation unit 100 is an additional functional block, so that the multiplication-accumulation operation (MAC) of 2 data bits and 1 weight bit can be implemented without modifying the memory array.

[0026] In the present embodiment, the resistor R11 can have a resistance value that is 2 raised to the power of n times the resistance value of the resistor R01, where n is a positive integer greater than or equal to 1. For example, the resistor R11 can have a resistance value that is 2 times the resistance value of the resistor R01, but the present embodiment is not limited thereto.

[0027] In this embodiment, transistors M0 and M2 control whether the memory subarray 10 is written to based on the management word line HWL, that is, determine the global bit line GBL. <0> Whether the transmitted bits are written to weighted memory cells (such as WBC_1 to WBC_n) in memory subarray 10. Furthermore, transistor M0 has a connection to the global bit line GBL. <0> The first terminal of transistor M1 is coupled to the control terminal of the management word line HWL, and the second terminal is coupled to the local bit line LBL of memory subarray 10. Transistor M1 has a connection to GBLB as a global anti-phase line. <0> The first end of the common signal line, the control terminal of the management word line HWL, and the second end of the local anti-phase line LBLB of the memory subarray 10 are coupled.

[0028] In this embodiment, the memory subarray 10 includes, for example, multiple weighted memory cells WBC_1 to WBC_n, wherein the weighted memory cells are, for example, Static Random Access Memory (SRAM), but this embodiment of the invention is not limited thereto. In this embodiment, the weighted memory cell (taking WBC_1 as an example) includes, for example, transistors T1 to T6. Transistor T1 has a first terminal coupled to the local bit line LBL, a control terminal coupled to the word line WL, and a second terminal. Transistor T2 has a first terminal coupled to the high-voltage power line Vdd, a control terminal, and a second terminal coupled to the second terminal of transistor T1. Transistor T3 has a first terminal coupled to the second terminal of transistor T1, a control terminal coupled to the control terminal of transistor T2, and a second terminal coupled to the ground line.

[0029] Transistor T4 has a first terminal coupled to the high-voltage power supply line Vdd, a control terminal coupled to the second terminal of transistor T1, and a second terminal coupled to the control terminal of transistor T2. Transistor T5 has a first terminal coupled to the control terminal of transistor T2, a control terminal coupled to the second terminal of transistor T1, and a second terminal coupled to the ground line. Transistor T6 has a first terminal coupled to the control terminal of transistor T2, a control terminal coupled to the word line WL, and a second terminal coupled to the local anti-phase line LBLB.

[0030] Figure 2 This is a circuit diagram of a configurable arithmetic unit according to a second embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The same or similar components use the same or similar labels. The configurable arithmetic unit 200 is generally the same as the configurable arithmetic unit 100, except that the configurable arithmetic unit 200 further includes transistors M6-M9, resistor R02 (corresponding to the third resistor) and resistor R12 (corresponding to the fourth resistor).

[0031] Transistor M6 (corresponding to the third input transistor) has a first terminal, a control terminal coupled to another input bit line among multiple input bit lines (such as INBL_0 to INBL_3) (taking input bit line INBL_0 as an example, corresponding to the third input bit line), and a second terminal. Transistor M7 (corresponding to the third weighting transistor) has a first terminal coupled to the second terminal of transistor M6, a control terminal receiving the first weighting bit W0, and a second readout bit line R_RBL. <1> The second terminal. Resistor R02 is coupled to the first terminal of transistor M6 and the common signal line (such as GBLB). <0> (as shown in / VSS) between.

[0032] Transistor M9 (corresponding to the fourth input transistor) has a first terminal, a control terminal coupled to another input bit line among multiple input bit lines (such as INBL_0 to INBL_3) (taking input bit line INBL_1 as an example, corresponding to the fourth input bit line), and a second terminal. Transistor M8 (corresponding to the fourth weighting transistor) has a first terminal coupled to the second terminal of transistor M9, a control terminal for receiving the first weighting bit W0, and a second readout bit line R_RBL. <1> The second terminal. Resistor R12 is coupled to the first terminal of transistor M9 and the common signal line (such as GBLB). <0> (as shown in / VSS) between.

[0033] In this embodiment, the resistance value of resistor R12 differs from that of resistor R02, and the configurable arithmetic unit 200 can perform a multiplicative accumulation (MAC) operation on 4 data bits and 1 weight bit. In this embodiment, the resistance value of resistor R11 is a power of 2 times the resistance value of resistor R01, and the resistance value of resistor R12 is a power of 2 times the resistance value of resistor R02, where n is a positive integer greater than or equal to 1. The resistance value of resistor R11 can be the same as the resistance value of resistor R12, and the resistance value of resistor R02 can also be the same as the resistance value of resistor R02.

[0034] Figure 3 This is a circuit diagram of a configurable arithmetic unit according to a third embodiment of the present invention. Please refer to... Figure 2 and Figure 3 The same or similar components use the same or similar designations. The configurable arithmetic unit 300 is generally the same as the configurable arithmetic unit 200, except that the configurable arithmetic unit 300 further includes transistors M10-M19, resistor R13 (corresponding to the fifth resistor), resistor R21 (corresponding to the sixth resistor), resistor R14 (corresponding to the seventh resistor), and resistor R22 (corresponding to the eighth resistor). Transistors M10 and M11 can be referred to as transistors M0 and M1, and will not be described again here.

[0035] The transistor M12 (corresponding to a fifth input transistor) has a first end, a control end coupled to one of the plurality of input bit lines (e.g., INBL_0 ~ INBL_3) (herein, the input bit line INBL_2 is taken as an example, corresponding to a first input bit line), and a second end. The transistor M13 (corresponding to a fifth weight transistor) has a first end coupled to the second end of the transistor M12, a control end receiving the second weight bit W1 from the memory sub-array 10, and a second end coupled to the first readout bit line R_RBL<0>. The resistor R13 is coupled between the first end of the first input transistor M12 and a common signal line (e.g., GBLB<0> / VSS).

[0036] The transistor M15 (corresponding to a sixth input transistor) has a first end, a control end coupled to another one of the plurality of input bit lines (e.g., INBL_0 ~ INBL_3) (herein, the input bit line INBL_3 is taken as an example, corresponding to a second input bit line), and a second end. The transistor M14 (corresponding to a sixth weight transistor) has a first end coupled to the second end of the transistor M15, a control end receiving the second weight bit W1, and a second end coupled to the first readout bit line R_RBL<0>. The resistor R21 is coupled between the first end of the sixth input transistor M15 and the common signal line (e.g., GBLB<0> / VSS). The resistor R21 has a resistance value different from that of the resistor R13, but the resistance value of the resistor R13 can be the same as that of the resistor R11.

[0037] The transistor M16 (corresponding to a seventh input transistor) has a first end, a control end coupled to still another one of the plurality of input bit lines (e.g., INBL_0 ~ INBL_3) (herein, the input bit line INBL_0 is taken as an example, corresponding to a third input bit line), and a second end. The transistor M17 (corresponding to a seventh weight transistor) has a first end coupled to the second end of the transistor M16, a control end receiving the second weight bit W1, and a second end coupled to the second readout bit line R_RBL<1>. The resistor R14 is coupled between the first end of the transistor M16 and the common signal line (e.g., GBLB<0> / VSS).

[0038] The transistor M19 (corresponding to the eighth input transistor) has a first end, a control end coupled to another one of the plurality of input bit lines (for example, INBL_0 to INBL_3) (for example, the fourth input bit line INBL_1), and a second end. The transistor M18 (corresponding to the eighth weight transistor) has a first end coupled to the second end of the transistor M19, a control end receiving the second weight bit W1, and a second end coupled to the second readout bit line R_RBL<1>. The resistor R22 is coupled between the first end of the transistor M19 and a common signal line (for example, GBLB<0> / VSS). The resistor R22 has a resistance value different from that of the resistor R14, but the resistance value of the resistor R14 can be the same as that of the resistor R12.

[0039] According to the above, the configurable operation unit 300 can implement the multiplication and accumulation operation (MAC) of 4 data bits and 2 weight bits, that is, each of the first readout bit line R_RBL<0> and the second readout bit line R_RBL<1> is the accumulation of two times of multiplication and accumulation operations.

[0040] In the embodiment of the application, the resistance value of the resistor R12 is different from that of the resistor R02, and in the embodiment of the application, the resistance value of the resistor R11 is 2n times that of the resistor R01, and the resistance value of the resistor R12 is 2n times that of the resistor R02, where n is a positive integer greater than or equal to 1. The resistance value of the resistor R11 can be the same as that of the resistor R12, and the resistance value of the resistor R01 can be the same as that of the resistor R02.

[0041] In the embodiment of the application, the resistance value of the resistor R21 is 2n times that of the resistor R13, and the resistance value of the resistor R22 is 2n times that of the resistor R14. In addition, the resistance value of the resistor R13 is 2n times that of the resistor R01, the resistance value of the resistor R21 is 2n times that of the resistor R11, the resistance value of the resistor R14 is 2n times that of the resistor R02, and the resistance value of the resistor R22 is 2n times that of the resistor R12.

[0042] In the embodiment of the application, the ratio of the resistance value of the resistor R11 to that of the first resistor R01 can be different from the ratio of the resistance value of the resistor R21 to that of the resistor R13, and the ratio of the resistance value of the resistor R12 to that of the resistor R02 can be different from the ratio of the resistance value of the resistor R22 to that of the resistor R14.

[0043] Figure 4This is a circuit diagram of a configurable arithmetic unit according to a fourth embodiment of the present invention. Please refer to... Figure 2 and Figure 4 In this embodiment, the configurable arithmetic unit 400 includes at least transistors M0a-M0n, M1a-M1n, M2a-M2n, M3a-M3n, M4a-M4n, M5a-M5n, M6a-M6n, M7a-M7n, M8a-M8n, M9a-M9n, and resistors R01a-R01n, R02a-R02n, R11a-R11n, and R12a-R12n. The configurable arithmetic unit 400 can be considered as a combination of multiple configurable arithmetic units 200. That is, the coupling relationship of transistors M0a-M0n, M1a-M1n, M2a-M2n, M3a-M3n, M4a-M4n, M5a-M5n, M6a-M6n, M7a-M7n, M8a-M8n, M9a-M9n, resistors R01a-R01n, R02a-R02n, R11a-R11n, and R12a-R12n can be referred to Figure 2 The coupling relationships of transistors M0 to M9 and resistors R01, R02, R11, and R12 shown will not be described again here.

[0044] In this embodiment, the configurable arithmetic unit 400 can perform a multiplication-accumulation (MAC) operation on 4 data bits and n weight bits (i.e., the first weight bit W0 to the nth weight bit Wn), i.e., the first readout bit line R_RBL. <0> and the second readout bit line R_RBL <1> Each of them is the sum of n multiplication-accumulation operations. Furthermore, each row can be a different combination of weights, for example, the resistance value of resistor R11a can be different from the resistance value of resistor R11b and / or the resistance value of resistor R01a can be different from the resistance value of resistor R01b.

[0045] Figure 5 This is a circuit diagram of a configurable arithmetic unit coupled to a weighted memory cell according to a fifth embodiment of the present invention. Please refer to... Figure 1 and Figure 5 Components that are identical or similar use the same or similar designations. In this embodiment, the configurable arithmetic unit 500 within the memory includes transistors M0, M1, M20, two M21s, and M22. The coupling relationship between transistors M0 and M1 can be referred to... Figure 1 As shown, it will not be repeated here.

[0046] The transistor M20 (corresponding to the first weight transistor) has a first terminal coupled to the first readout bit line R_RBL<0>, a control terminal receiving the first weight bit W0, and a second terminal. The transistor M22 (corresponding to the first input transistor) has a first terminal coupled to the second terminal of the transistor M20, a control terminal coupled to one of the plurality of input bit lines (e.g., INBL_0 ~ INBL_3), and a second terminal coupled to the common signal line (e.g., GBLB<0> / VSS). Each of the transistors M21 (corresponding to the second input transistor) has a first terminal coupled to the second terminal of the transistor M20, a control terminal coupled to one of the plurality of input bit lines (e.g., INBL_0 ~ INBL_3), and a second terminal coupled to the common signal line (e.g., GBLB<0> / VSS).

[0047] In the present embodiment, the number of the transistors M22 is different from the number of the transistors M21, and thus the total current flowing through the first readout bit line R_RBL<0> is the sum of the weight product of the first weight bit W0 and the bit (i.e., logic level) carried by the input bit line INBL_2 and the weight product of the first weight bit W0 and the bit (i.e., logic level) carried by the input bit line INBL_3.

[0048] In the present embodiment, the number of the transistors M22 is one and the number of the transistors M21 is two, but in other embodiments, the number of the transistors M22 can be two or other number, and the number of the transistors M21 can be four or other number. Moreover, the number of the transistors M21 can be 2n times of the number of the transistors M22.

[0049] Figure 6 A circuit schematic diagram of a configurable operation unit according to the sixth embodiment of the present application is shown in FIG. 6. Please refer to Figure 5 and Figure 6 wherein the same or similar components use the same or similar reference numerals, the configurable operation unit 600 is substantially the same as the configurable operation unit 500, except that the configurable operation unit 600 further includes a transistor M23, two transistors M24, and a transistor M25.

[0050] Transistor M23 (corresponding to the second weighted transistor) is coupled to the second readout bit line R_RBL <1> The transistor M25 has a first terminal coupled to the second terminal of transistor M23, a control terminal coupled to another input bit line (INBL_0 to INBL_3) among multiple input bit lines (taking input bit line INBL_0 as an example, corresponding to the third input bit line), and a control terminal coupled to a common signal line (such as GBLB). <0> The second terminal of transistor M24 (corresponding to the fourth input transistor) is coupled to the second terminal of transistor M23, a control terminal coupled to another input bit line (INBL_1, corresponding to the fourth input bit line) among multiple input bit lines (such as INBL_0 to INBL_3), and a common signal line (such as GBLB). <0> The second end (as shown in / VSS).

[0051] In this embodiment, the number of transistors M25 differs from the number of transistors M24. Furthermore, the example given is one transistor M25 and two transistors M24; however, in other embodiments, the number of transistors M25 can be two or other numbers, and the number of transistors M24 can be four or other numbers. In this embodiment, the number of transistors M24 can be a power of 2 multiple of the number of transistors M25.

[0052] Figure 7 This is a circuit diagram of a configurable arithmetic unit according to a seventh embodiment of the present invention. Please refer to... Figure 6 and Figure 7 The same or similar components use the same or similar labels. The configurable arithmetic unit 700 is generally the same as the configurable arithmetic unit 600, except that the configurable arithmetic unit 700 further includes transistors M26, M27, M28, four M29, two M30, M31, four M32, and two M33.

[0053] The transistor M28 (corresponding to a third weight transistor) has a first end coupled to the first readout bit line R_RBL<0>, a control end receiving the second weight bit W1, and a second end. Each transistor M30 (corresponding to a fifth input transistor) has a first end coupled to the second end of the transistor M28, a control end coupled to one of the plurality of input bit lines (e.g., INBL_0 to INBL_3), and a second end coupled to a common signal line (e.g., GBLB<0> / VSS). Each transistor M29 (corresponding to a sixth input transistor) has a first end coupled to the second end of the transistor M28, a control end coupled to another of the plurality of input bit lines (e.g., INBL_0 to INBL_3), and a second end coupled to the common signal line (e.g., GBLB<0> / VSS).

[0054] The transistor M31 (corresponding to a fourth weight transistor) has a first end coupled to the second readout bit line R_RBL<1>, a control end receiving the second weight bit W1, and a second end. Each transistor M33 (corresponding to a seventh input transistor) has a first end coupled to the second end of the transistor M31, a control end coupled to still another of the plurality of input bit lines (e.g., INBL_0 to INBL_3), and a second end coupled to the common signal line (e.g., GBLB<0> / VSS). The transistor M32 (corresponding to an eighth input transistor) has a first end coupled to the second end of the transistor M31, a control end coupled to yet another of the plurality of input bit lines (e.g., INBL_0 to INBL_3), and a second end coupled to the common signal line (e.g., GBLB<0> / VSS).

[0055] In the present embodiment, the number of transistors M30 is different from the number of transistors M29. Also, the number of transistors M30 is exemplified as 2 and the number of transistors M29 is exemplified as 4, but in other embodiments, the number of transistors M30 can be 4 or another number and the number of transistors M29 can be 8 or another number. In the present embodiment, the number of transistors M29 can be 2n times the number of transistors M30.

[0056] In the embodiment, the number of transistors M33 is different from the number of transistors M32. In addition, the number of transistors M33 is taken as an example of 2, and the number of transistors M32 is taken as an example of 4, but in other embodiments, the number of transistors M33 can be 4 or other numbers, and the number of transistors M32 can be 8 or other numbers. In the embodiment of the application, the number of transistors M32 can be 2n times the number of transistors M33.

[0057] In the embodiment of the application, the number of transistors M30 can be 2n times the number of transistors M22, the number of transistors M29 can be 2n times the number of transistors M21, the number of transistors M33 can be 2n times the number of transistors M25, and the number of transistors M32 can be 2n times the number of transistors M24.

[0058] In the embodiment of the application, the ratio of the number of transistors M21 to the number of transistors M22 can be different from the ratio of the number of transistors M29 to the number of transistors M30, and the ratio of the number of transistors M24 to the number of transistors M25 can be different from the ratio of the number of transistors M32 to the number of transistors M33.

[0059] Figure 8 The circuit schematic diagram of the configurable operation unit according to the eighth embodiment of the application is shown in FIG. 8. Please refer to Figure 6 and Figure 8 In the embodiment, the configurable operation unit 800 includes at least transistors M0a-M0n, M1a-M1n, M20a-M20n, M21a-M21n, M22a-M22n, M23a-M23n, M24a-M24n, M25a-M25n. The configurable operation unit 800 can be regarded as a combination of multiple configurable operation units 600, that is, the coupling relationship of transistors M0a-M0n, M1a-M1n, M20a-M20n, M21a-M21n, M22a-M22n, M23a-M23n, M24a-M24n, M25a-M25n can refer to the coupling relationship of transistors M0, M1, M20, M21, M22, M23, M24, M25 shown in FIG. 6, which will not be described here. Figure 2

[0060] ​In the present embodiment, the configurable operation unit 800 can implement a multiply-accumulate operation (MAC) of 4 data bits and n weight bits, that is, each of the first read bit line R_RBL<0> and the second read bit line R_RBL<1> is an accumulation of n times multiply-accumulate operation. Moreover, each row can be a different weight combination, for example, the number of transistors M21a can be different from the number of transistors M21b and / or the number of transistors M22a can be different from the number of transistors M22b.

[0061] In summary, the configurable operation unit of the embodiments of the present application achieves the function of multiply-accumulate operation by concatenating weight transistors, input transistors and resistors and setting different resistance values of the resistors. In this way, since the configurable operation unit is an additional functional block, the multiply-accumulate operation (MAC) of data bits and weight bits can be implemented without changing the memory array. Alternatively, the function of multiply-accumulate operation is achieved by concatenating weight transistors and different numbers of input transistors.

[0062] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A configurable arithmetic unit in a memory, characterized by comprises: a first input transistor having a first terminal, a control terminal coupled to a first input bit line, and a second terminal; a first weight transistor having a first terminal coupled to the second terminal of the first input transistor, a control terminal receiving a first weight bit, and a second terminal coupled to a first readout bit line; a first resistor coupled between the first terminal of the first input transistor and a common signal line; a second input transistor having a first terminal, a control terminal coupled to a second input bit line, and a second terminal; a second weight transistor having a first terminal coupled to the second terminal of the second input transistor, a control terminal receiving the first weight bit, and a second terminal coupled to the first readout bit line; and a second resistor coupled between the first terminal of the second input transistor and the common signal line, wherein a resistance value of the second resistor is different from a resistance value of the first resistor. The resistance value of the second resistor is 2 raised to the power of n times the resistance value of the first resistor, n being a positive integer greater than or equal to 1.

2. The configurable arithmetic unit of claim 1, wherein, Further comprising:

3. The configurable arithmetic unit of claim 1, wherein, a third input transistor having a first terminal, a control terminal coupled to a third input bit line, and a second terminal; a third weight transistor having a first terminal coupled to the second terminal of the third input transistor, a control terminal receiving the first weight bit, and a second terminal coupled to a second readout bit line; a third resistor coupled between the first terminal of the third input transistor and the common signal line; a fourth input transistor having a first terminal, a control terminal coupled to a fourth input bit line, and a second terminal; a fourth weight transistor having a first terminal coupled to the second terminal of the fourth input transistor, a control terminal receiving the first weight bit, and a second terminal coupled to the second readout bit line; and a fourth resistor coupled between the first terminal of the fourth input transistor and the common signal line, wherein a resistance value of the fourth resistor is different from a resistance value of the third resistor. The resistance value of the second resistor is 2 raised to the power of n times the resistance value of the first resistor, and the resistance value of the fourth resistor is 2 raised to the power of n times the resistance value of the third resistor, n being a positive integer greater than or equal to 1.

4. The configurable arithmetic unit of claim 3, wherein, Further comprising:

5. The configurable arithmetic unit of claim 3, wherein, a fifth input transistor having a first terminal, a control terminal coupled to the first input bit line, and a second terminal; a fifth weight transistor having a first terminal coupled to the second terminal of the fifth input transistor, a control terminal receiving a second weight bit, and a second terminal coupled to the first readout bit line; a fifth resistor coupled between the first terminal of the fifth input transistor and the common signal line; a sixth input transistor having a first terminal, a control terminal coupled to the second input bit line, and a second terminal; a sixth weight transistor having a first terminal coupled to the second terminal of the sixth input transistor, a control terminal receiving the second weight bit, and a second terminal coupled to the first readout bit line; and a sixth resistor coupled between the first terminal of the sixth input transistor and the common signal line, ​ ​ a seventh input transistor having a first terminal, a control terminal coupled to the third input bit line, and a second terminal; a seventh weight transistor having a first terminal coupled to the second terminal of the seventh input transistor, a control terminal receiving the second weight bit, and a second terminal coupled to the second readout bit line; a seventh resistor coupled between the first terminal of the seventh input transistor and the common signal line; an eighth input transistor having a first terminal, a control terminal coupled to the fourth input bit line, and a second terminal; an eighth weight transistor having a first terminal coupled to the second terminal of the eighth input transistor, a control terminal receiving the second weight bit, and a second terminal coupled to the second readout bit line; a seventh resistor coupled between the first terminal of the seventh input transistor and the common signal line, wherein a resistance value of the sixth resistor is different from a resistance value of the fifth resistor, and a resistance value of the eighth resistor is different from a resistance value of the seventh resistor. a resistance value of the second resistor is 2n times of a resistance value of the first resistor, a resistance value of the fourth resistor is 2n times of a resistance value of the third resistor, a resistance value of the sixth resistor is 2n times of a resistance value of the fifth resistor, and a resistance value of the eighth resistor is 2n times of a resistance value of the seventh resistor, n being a positive integer greater than or equal to 1.

6. The configurable arithmetic unit of claim 5, wherein, a resistance value of the fifth resistor is 2n times of a resistance value of the first resistor, a resistance value of the sixth resistor is 2n times of a resistance value of the second resistor, a resistance value of the seventh resistor is 2n times of a resistance value of the third resistor, and a resistance value of the eighth resistor is 2n times of a resistance value of the fourth resistor, n being a positive integer greater than or equal to 1.

7. The configurable arithmetic unit of claim 5, wherein, a ratio of a resistance value of the second resistor to a resistance value of the first resistor is different from a ratio of a resistance value of the sixth resistor to a resistance value of the fifth resistor, and a ratio of a resistance value of the fourth resistor to a resistance value of the third resistor is different from a ratio of a resistance value of the eighth resistor to a resistance value of the seventh resistor.

8. The configurable arithmetic unit of claim 5, wherein, comprising:

9. A configurable arithmetic unit in a memory, characterized by a first weight transistor having a first terminal coupled to a first readout bit line, a control terminal receiving a first weight bit, and a second terminal; at least one first input transistor having a first terminal coupled to the second terminal of the first weight transistor, a control terminal coupled to a first input bit line, and a second terminal coupled to a common signal line; and at least one second input transistor having a first terminal coupled to the second terminal of the first weight transistor, a control terminal coupled to a second input bit line, and a second terminal coupled to the common signal line; wherein a number of the at least one first input transistor is different from a number of the at least one second input transistor. a number of the at least one second input transistor is 2n times of a number of the at least one first input transistor, n being a positive integer greater than or equal to 1.

10. The configurable arithmetic unit of claim 9, wherein, further comprising:

11. The configurable arithmetic unit of claim 9 wherein, ​ a second weight transistor having a first end coupled to the second readout bit line, a control end receiving the first weight bit, and a second end; at least one third input transistor having a first end coupled to the second end of the second weight transistor, a control end coupled to a third input bit line, and a second end coupled to the common signal line; and at least one fourth input transistor having a first end coupled to the second end of the second weight transistor, a control end coupled to a fourth input bit line, and a second end coupled to the common signal line; wherein a number of the at least one third input transistor is different from a number of the at least one fourth input transistor.

12. The configurable arithmetic unit of claim 11, wherein, a number of the at least one second input transistor is 2n times a number of the at least one first input transistor, a number of the at least one fourth input transistor is 2n times a number of the at least one third input transistor, and n is a positive integer greater than or equal to 1.

13. The configurable arithmetic unit of claim 11, wherein, further comprising: a third weight transistor having a first end coupled to the first readout bit line, a control end receiving a second weight bit, and a second end; at least one fifth input transistor having a first end coupled to the second end of the third weight transistor, a control end coupled to the first input bit line, and a second end coupled to the common signal line; and at least one sixth input transistor having a first end coupled to the second end of the third weight transistor, a control end coupled to the second input bit line, and a second end coupled to the common signal line; a fourth weight transistor having a first end coupled to the second readout bit line, a control end receiving a second weight bit, and a second end; at least one seventh input transistor having a first end coupled to the second end of the fourth weight transistor, a control end coupled to the third input bit line, and a second end coupled to the common signal line; and at least one eighth input transistor having a first end coupled to the second end of the fourth weight transistor, a control end coupled to the fourth input bit line, and a second end coupled to the common signal line; wherein a number of the at least one fifth input transistor is different from a number of the at least one sixth input transistor, and wherein a number of the at least one seventh input transistor is different from a number of the at least one eighth input transistor.

14. The configurable arithmetic unit of claim 13, wherein, a number of the at least one second input transistor is 2n times a number of the at least one first input transistor, a number of the at least one fourth input transistor is 2n times a number of the at least one third input transistor, a number of the at least one sixth input transistor is 2n times a number of the at least one fifth input transistor, and a number of the at least one eighth input transistor is 2n times a number of the at least one seventh input transistor, and n is a positive integer greater than or equal to 1.

15. The configurable arithmetic unit of claim 13, wherein, The number of the at least one fifth input transistor is 2 raised to the power of n times the number of the at least one first input transistor, the number of the at least one sixth input transistor is 2 raised to the power of n times the number of the at least one second input transistor, the number of the at least one seventh input transistor is 2 raised to the power of n times the number of the at least one third input transistor, and the number of the at least one eighth input transistor is 2 raised to the power of n times the number of the at least one fourth input transistor, n being a positive integer greater than or equal to 1.

16. The configurable arithmetic unit of claim 13, wherein, The ratio of the number of the at least one second input transistor to the number of the at least one first input transistor is different from the ratio of the number of the at least one sixth input transistor to the number of the at least one fifth input transistor, and the ratio of the number of the at least one fourth input transistor to the number of the at least one third input transistor is different from the ratio of the number of the at least one eighth input transistor to the number of the at least one seventh input transistor.

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